Lines Matching full:dmic

439 	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL1,
446 	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER0_CTRL2,
453 	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL1,
460 	SOC_DAPM_SINGLE("DMIC Switch", RT5514_DOWNFILTER1_CTRL2,
466 /* DMIC Source */
476 	SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5514_stereo1_dmic_enum);
483 	SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5514_stereo2_dmic_enum);
486  * rt5514_calc_dmic_clk - Calculate the frequency divider parameter of dmic.
491  * Choose divider parameter that gives the highest possible DMIC frequency in
505 		/* find divider that gives DMIC frequency below 3.072MHz */  in rt5514_calc_dmic_clk()
523 		dev_err(component->dev, "Failed to set DMIC clock\n");  in rt5514_set_dmic_clk()
569 	SND_SOC_DAPM_SUPPLY_S("DMIC CLK", 1, SND_SOC_NOPM, 0, 0,
632 	SND_SOC_DAPM_MUX("Stereo1 DMIC Mux", SND_SOC_NOPM, 0, 0,
634 	SND_SOC_DAPM_MUX("Stereo2 DMIC Mux", SND_SOC_NOPM, 0, 0,
675 	{ "DMIC1L", NULL, "DMIC CLK" },
676 	{ "DMIC1R", NULL, "DMIC CLK" },
677 	{ "DMIC2L", NULL, "DMIC CLK" },
678 	{ "DMIC2R", NULL, "DMIC CLK" },
680 	{ "Stereo1 DMIC Mux", "DMIC1", "DMIC1" },
681 	{ "Stereo1 DMIC Mux", "DMIC2", "DMIC2" },
683 	{ "Sto1 ADC MIXL", "DMIC Switch", "Stereo1 DMIC Mux" },
685 	{ "Sto1 ADC MIXR", "DMIC Switch", "Stereo1 DMIC Mux" },
729 	{ "Stereo2 DMIC Mux", "DMIC1", "DMIC1" },
730 	{ "Stereo2 DMIC Mux", "DMIC2", "DMIC2" },
732 	{ "Sto2 ADC MIXL", "DMIC Switch", "Stereo2 DMIC Mux" },
734 	{ "Sto2 ADC MIXR", "DMIC Switch", "Stereo2 DMIC Mux" },
1224 	device_property_read_u32(dev, "realtek,dmic-init-delay-ms",  in rt5514_parse_dp()