Lines Matching +full:0 +full:xca00
31 { 0xc003, 0xe0 },
32 { 0xc01b, 0xfc },
33 { 0xc5c3, 0xf2 },
34 { 0xc5c2, 0x00 },
35 { 0xc5c6, 0x10 },
36 { 0xc5c4, 0x12 },
37 { 0xc5c8, 0x03 },
38 { 0xc5d8, 0x0a },
39 { 0xc5f7, 0x22 },
40 { 0xc5f6, 0x22 },
41 { 0xc5d0, 0x0f },
42 { 0xc5d1, 0x89 },
43 { 0xc057, 0x51 },
44 { 0xc054, 0x35 },
45 { 0xc053, 0x55 },
46 { 0xc052, 0x55 },
47 { 0xc051, 0x13 },
48 { 0xc050, 0x15 },
49 { 0xc060, 0x77 },
50 { 0xc061, 0x55 },
51 { 0xc063, 0x55 },
52 { 0xc065, 0xa5 },
53 { 0xc06b, 0x0a },
54 { 0xca05, 0xd6 },
55 { 0xca25, 0xd6 },
56 { 0xcd00, 0x05 },
57 { 0xc604, 0x40 },
58 { 0xc609, 0x40 },
59 { 0xc046, 0xff },
60 { 0xc045, 0xff },
61 { 0xc044, 0xff },
62 { 0xc043, 0xff },
63 { 0xc042, 0xff },
64 { 0xc041, 0xff },
65 { 0xc040, 0xff },
66 { 0xcc10, 0x01 },
67 { 0xc700, 0xf0 },
68 { 0xc701, 0x13 },
69 { 0xc901, 0x04 },
70 { 0xc900, 0x73 },
71 { 0xde03, 0x05 },
72 { 0xdd0b, 0x0d },
73 { 0xdd0a, 0xff },
74 { 0xdd09, 0x0d },
75 { 0xdd08, 0xff },
76 { 0xc570, 0x08 },
77 { 0xe803, 0xbe },
78 { 0xc003, 0xc0 },
79 { 0xc081, 0xfe },
80 { 0xce31, 0x0d },
81 { 0xce30, 0xae },
82 { 0xce37, 0x0b },
83 { 0xce36, 0xd2 },
84 { 0xce39, 0x04 },
85 { 0xce38, 0x80 },
86 { 0xce3f, 0x00 },
87 { 0xce3e, 0x00 },
88 { 0xd470, 0x8b },
89 { 0xd471, 0x18 },
90 { 0xc019, 0x10 },
91 { 0xd487, 0x3f },
92 { 0xd486, 0xc3 },
93 { 0x3fc2bfc7, 0x00 },
94 { 0x3fc2bfc6, 0x00 },
95 { 0x3fc2bfc5, 0x00 },
96 { 0x3fc2bfc4, 0x01 },
97 { 0x0000d486, 0x43 },
98 { 0x1000db00, 0x02 },
99 { 0x1000db01, 0x00 },
100 { 0x1000db02, 0x11 },
101 { 0x1000db03, 0x00 },
102 { 0x1000db04, 0x00 },
103 { 0x1000db05, 0x82 },
104 { 0x1000db06, 0x04 },
105 { 0x1000db07, 0xf1 },
106 { 0x1000db08, 0x00 },
107 { 0x1000db09, 0x00 },
108 { 0x1000db0a, 0x40 },
109 { 0x0000d540, 0x01 },
110 { 0xd172, 0x2a },
111 { 0xc5d6, 0x01 },
112 { 0xd478, 0xff },
116 { 0xc003, 0xe0 },
117 { 0xe80a, 0x01 },
118 { 0xc5c3, 0xf3 },
119 { 0xc057, 0x51 },
120 { 0xc054, 0x35 },
121 { 0xca05, 0xd6 },
122 { 0xca07, 0x07 },
123 { 0xca25, 0xd6 },
124 { 0xca27, 0x07 },
125 { 0xc604, 0x40 },
126 { 0xc609, 0x40 },
127 { 0xc046, 0xff },
128 { 0xc045, 0xff },
129 { 0xda81, 0x14 },
130 { 0xda8d, 0x14 },
131 { 0xc044, 0xff },
132 { 0xc043, 0xff },
133 { 0xc042, 0xff },
134 { 0xc041, 0x7f },
135 { 0xc040, 0xff },
136 { 0xcc10, 0x01 },
137 { 0xc700, 0xf0 },
138 { 0xc701, 0x13 },
139 { 0xc901, 0x09 },
140 { 0xc900, 0xd0 },
141 { 0xde03, 0x05 },
142 { 0xdd0b, 0x0d },
143 { 0xdd0a, 0xff },
144 { 0xdd09, 0x0d },
145 { 0xdd08, 0xff },
146 { 0xc570, 0x08 },
147 { 0xc086, 0x02 },
148 { 0xc085, 0x7f },
149 { 0xc084, 0x00 },
150 { 0xc081, 0xfe },
151 { 0xf084, 0x0f },
152 { 0xf083, 0xff },
153 { 0xf082, 0xff },
154 { 0xf081, 0xff },
155 { 0xf080, 0xff },
156 { 0xe802, 0xf8 },
157 { 0xe803, 0xbe },
158 { 0xc003, 0xc0 },
159 { 0xd470, 0xec },
160 { 0xd471, 0x3a },
161 { 0xd474, 0x11 },
162 { 0xd475, 0x32 },
163 { 0xd478, 0xff },
164 { 0xd479, 0x20 },
165 { 0xd47a, 0x10 },
166 { 0xd47c, 0xff },
167 { 0xc019, 0x10 },
168 { 0xd487, 0x0b },
169 { 0xd487, 0x3b },
170 { 0xd486, 0xc3 },
171 { 0xc598, 0x04 },
172 { 0xdb03, 0xf0 },
173 { 0xdb09, 0x00 },
174 { 0xdb08, 0x7a },
175 { 0xdb19, 0x02 },
176 { 0xdb07, 0x5a },
177 { 0xdb05, 0x45 },
178 { 0xd500, 0x00 },
179 { 0xd500, 0x17 },
180 { 0xd600, 0x01 },
181 { 0xd601, 0x02 },
182 { 0xd602, 0x03 },
183 { 0xd603, 0x04 },
184 { 0xd64c, 0x03 },
185 { 0xd64d, 0x03 },
186 { 0xd64e, 0x03 },
187 { 0xd64f, 0x03 },
188 { 0xd650, 0x03 },
189 { 0xd651, 0x03 },
190 { 0xd652, 0x03 },
191 { 0xd610, 0x01 },
192 { 0xd608, 0x03 },
193 { 0xd609, 0x00 },
194 { 0x3fc2bf83, 0x00 },
195 { 0x3fc2bf82, 0x00 },
196 { 0x3fc2bf81, 0x00 },
197 { 0x3fc2bf80, 0x00 },
198 { 0x3fc2bfc7, 0x00 },
199 { 0x3fc2bfc6, 0x00 },
200 { 0x3fc2bfc5, 0x00 },
201 { 0x3fc2bfc4, 0x00 },
202 { 0x3fc2bfc3, 0x00 },
203 { 0x3fc2bfc2, 0x00 },
204 { 0x3fc2bfc1, 0x00 },
205 { 0x3fc2bfc0, 0x03 },
206 { 0x0000d486, 0x43 },
207 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x00 },
208 { 0x1000db00, 0x07 },
209 { 0x1000db01, 0x00 },
210 { 0x1000db02, 0x11 },
211 { 0x1000db03, 0x00 },
212 { 0x1000db04, 0x00 },
213 { 0x1000db05, 0x82 },
214 { 0x1000db06, 0x04 },
215 { 0x1000db07, 0xf1 },
216 { 0x1000db08, 0x00 },
217 { 0x1000db09, 0x00 },
218 { 0x1000db0a, 0x40 },
219 { 0x1000db0b, 0x02 },
220 { 0x1000db0c, 0xf2 },
221 { 0x1000db0d, 0x00 },
222 { 0x1000db0e, 0x00 },
223 { 0x1000db0f, 0xe0 },
224 { 0x1000db10, 0x00 },
225 { 0x1000db11, 0x10 },
226 { 0x1000db12, 0x00 },
227 { 0x1000db13, 0x00 },
228 { 0x1000db14, 0x45 },
229 { 0x1000db15, 0x0d },
230 { 0x1000db16, 0x01 },
231 { 0x1000db17, 0x00 },
232 { 0x1000db18, 0x00 },
233 { 0x1000db19, 0xbf },
234 { 0x1000db1a, 0x13 },
235 { 0x1000db1b, 0x09 },
236 { 0x1000db1c, 0x00 },
237 { 0x1000db1d, 0x00 },
238 { 0x1000db1e, 0x00 },
239 { 0x1000db1f, 0x12 },
240 { 0x1000db20, 0x09 },
241 { 0x1000db21, 0x00 },
242 { 0x1000db22, 0x00 },
243 { 0x1000db23, 0x00 },
244 { 0x0000d540, 0x01 },
245 { 0x0000c081, 0xfc },
246 { 0x0000f01e, 0x80 },
247 { 0xc01b, 0xfc },
248 { 0xc5d1, 0x89 },
249 { 0xc5d8, 0x0a },
250 { 0xc5f7, 0x22 },
251 { 0xc5f6, 0x22 },
252 { 0xc065, 0xa5 },
253 { 0xc06b, 0x0a },
254 { 0xd172, 0x2a },
255 { 0xc5d6, 0x01 },
256 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
260 { 0x0000c003, 0xf0 },
261 { 0x0000c01b, 0xfc },
262 { 0x0000c5c3, 0xf2 },
263 { 0x0000c5c2, 0x00 },
264 { 0x0000c5c1, 0x10 },
265 { 0x0000c5c0, 0x04 },
266 { 0x0000c5c7, 0x03 },
267 { 0x0000c5c6, 0x10 },
268 { 0x0000c526, 0x47 },
269 { 0x0000c5c4, 0x12 },
270 { 0x0000c5c5, 0x60 },
271 { 0x0000c520, 0x10 },
272 { 0x0000c521, 0x32 },
273 { 0x0000c5c7, 0x00 },
274 { 0x0000c5c8, 0x03 },
275 { 0x0000c5d3, 0x08 },
276 { 0x0000c5d2, 0x0a },
277 { 0x0000c5d1, 0x49 },
278 { 0x0000c5d0, 0x0f },
279 { 0x0000c580, 0x10 },
280 { 0x0000c581, 0x32 },
281 { 0x0000c582, 0x01 },
282 { 0x0000cb00, 0x03 },
283 { 0x0000cb02, 0x52 },
284 { 0x0000cb04, 0x80 },
285 { 0x0000cb0b, 0x01 },
286 { 0x0000c682, 0x60 },
287 { 0x0000c019, 0x10 },
288 { 0x0000c5f0, 0x01 },
289 { 0x0000c5f7, 0x22 },
290 { 0x0000c5f6, 0x22 },
291 { 0x0000c057, 0x51 },
292 { 0x0000c054, 0x55 },
293 { 0x0000c053, 0x55 },
294 { 0x0000c052, 0x55 },
295 { 0x0000c051, 0x01 },
296 { 0x0000c050, 0x15 },
297 { 0x0000c060, 0x99 },
298 { 0x0000c030, 0x55 },
299 { 0x0000c061, 0x55 },
300 { 0x0000c063, 0x55 },
301 { 0x0000c065, 0xa5 },
302 { 0x0000c06b, 0x0a },
303 { 0x0000ca05, 0xd6 },
304 { 0x0000ca07, 0x07 },
305 { 0x0000ca25, 0xd6 },
306 { 0x0000ca27, 0x07 },
307 { 0x0000cd00, 0x05 },
308 { 0x0000c604, 0x40 },
309 { 0x0000c609, 0x40 },
310 { 0x0000c046, 0xf7 },
311 { 0x0000c045, 0xff },
312 { 0x0000c044, 0xff },
313 { 0x0000c043, 0xff },
314 { 0x0000c042, 0xff },
315 { 0x0000c041, 0xff },
316 { 0x0000c040, 0xff },
317 { 0x0000c049, 0xff },
318 { 0x0000c028, 0x3f },
319 { 0x0000c020, 0x3f },
320 { 0x0000c032, 0x13 },
321 { 0x0000c033, 0x01 },
322 { 0x0000cc10, 0x01 },
323 { 0x0000dc20, 0x03 },
324 { 0x0000de03, 0x05 },
325 { 0x0000dc00, 0x00 },
326 { 0x0000c700, 0xf0 },
327 { 0x0000c701, 0x13 },
328 { 0x0000c900, 0xc3 },
329 { 0x0000c570, 0x08 },
330 { 0x0000c086, 0x02 },
331 { 0x0000c085, 0x7f },
332 { 0x0000c084, 0x00 },
333 { 0x0000c081, 0xff },
334 { 0x0000f084, 0x0f },
335 { 0x0000f083, 0xff },
336 { 0x0000f082, 0xff },
337 { 0x0000f081, 0xff },
338 { 0x0000f080, 0xff },
339 { 0x20003003, 0x3f },
340 { 0x20005818, 0x81 },
341 { 0x20009018, 0x81 },
342 { 0x2000301c, 0x81 },
343 { 0x0000c003, 0xc0 },
344 { 0x0000c047, 0x80 },
345 { 0x0000d541, 0x80 },
346 { 0x0000d487, 0x0b },
347 { 0x0000d487, 0x3b },
348 { 0x0000d486, 0xc3 },
349 { 0x0000d470, 0x89 },
350 { 0x0000d471, 0x3a },
351 { 0x0000d472, 0x1d },
352 { 0x0000d478, 0xff },
353 { 0x0000d479, 0x20 },
354 { 0x0000d47a, 0x10 },
355 { 0x0000d73c, 0xb7 },
356 { 0x0000d73d, 0xd7 },
357 { 0x0000d73e, 0x00 },
358 { 0x0000d73f, 0x10 },
359 { 0x3fc2dfc3, 0x00 },
360 { 0x3fc2dfc2, 0x00 },
361 { 0x3fc2dfc1, 0x00 },
362 { 0x3fc2dfc0, 0x07 },
363 { 0x3fc2dfc7, 0x00 },
364 { 0x3fc2dfc6, 0x00 },
365 { 0x3fc2dfc5, 0x00 },
366 { 0x3fc2dfc4, 0x01 },
367 { 0x3fc2df83, 0x00 },
368 { 0x3fc2df82, 0x00 },
369 { 0x3fc2df81, 0x00 },
370 { 0x3fc2df80, 0x00 },
371 { 0x0000d541, 0x40 },
372 { 0x0000d486, 0x43 },
373 { 0x1000db00, 0x03 },
374 { 0x1000db01, 0x00 },
375 { 0x1000db02, 0x10 },
376 { 0x1000db03, 0x00 },
377 { 0x1000db04, 0x00 },
378 { 0x1000db05, 0x45 },
379 { 0x1000db06, 0x12 },
380 { 0x1000db07, 0x09 },
381 { 0x1000db08, 0x00 },
382 { 0x1000db09, 0x00 },
383 { 0x1000db0a, 0x00 },
384 { 0x1000db0b, 0x13 },
385 { 0x1000db0c, 0x09 },
386 { 0x1000db0d, 0x00 },
387 { 0x1000db0e, 0x00 },
388 { 0x1000db0f, 0x00 },
389 { 0x0000d540, 0x21 },
390 { 0x41000189, 0x00 },
391 { 0x4100018a, 0x00 },
392 { 0x41001988, 0x00 },
393 { 0x41081400, 0x09 },
394 { 0x40801508, 0x03 },
395 { 0x40801588, 0x03 },
396 { 0x40801809, 0x00 },
397 { 0x4080180a, 0x00 },
398 { 0x4080180b, 0x00 },
399 { 0x4080180c, 0x00 },
400 { 0x40801b09, 0x00 },
401 { 0x40801b0a, 0x00 },
402 { 0x40801b0b, 0x00 },
403 { 0x40801b0c, 0x00 },
404 { 0x0000d714, 0x17 },
405 { 0x20009012, 0x00 },
406 { 0x0000dd0b, 0x0d },
407 { 0x0000dd0a, 0xff },
408 { 0x0000dd09, 0x0d },
409 { 0x0000dd08, 0xff },
410 { 0x0000d172, 0x2a },
411 { 0x41001988, 0x03 },
415 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
416 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
417 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
418 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
419 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
420 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
421 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x0b },
422 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
423 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_01), 0x01 },
424 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_MUTE, CH_02), 0x01 },
425 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
426 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0x03 },
427 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0x00 },
428 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0), 0x09 },
429 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), 0x03 },
433 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
434 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU113, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
435 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
436 { SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_FU14, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
437 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_01), 0x0000 },
438 { SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_FU21, RT1320_SDCA_CTL_FU_VOLUME, CH_02), 0x0000 },
444 case 0xc000 ... 0xc086:
445 case 0xc400 ... 0xc409:
446 case 0xc480 ... 0xc48f:
447 case 0xc4c0 ... 0xc4c4:
448 case 0xc4e0 ... 0xc4e7:
449 case 0xc500:
450 case 0xc560 ... 0xc56b:
451 case 0xc570:
452 case 0xc580 ... 0xc59a:
453 case 0xc5b0 ... 0xc60f:
454 case 0xc640 ... 0xc64f:
455 case 0xc670:
456 case 0xc680 ... 0xc683:
457 case 0xc700 ... 0xc76f:
458 case 0xc800 ... 0xc801:
459 case 0xc820:
460 case 0xc900 ... 0xc901:
461 case 0xc920 ... 0xc921:
462 case 0xca00 ... 0xca07:
463 case 0xca20 ... 0xca27:
464 case 0xca40 ... 0xca4b:
465 case 0xca60 ... 0xca68:
466 case 0xca80 ... 0xca88:
467 case 0xcb00 ... 0xcb0c:
468 case 0xcc00 ... 0xcc12:
469 case 0xcc80 ... 0xcc81:
470 case 0xcd00:
471 case 0xcd80 ... 0xcd82:
472 case 0xce00 ... 0xce4d:
473 case 0xcf00 ... 0xcf25:
474 case 0xd000 ... 0xd0ff:
475 case 0xd100 ... 0xd1ff:
476 case 0xd200 ... 0xd2ff:
477 case 0xd300 ... 0xd3ff:
478 case 0xd400 ... 0xd403:
479 case 0xd410 ... 0xd417:
480 case 0xd470 ... 0xd497:
481 case 0xd4dc ... 0xd50f:
482 case 0xd520 ... 0xd543:
483 case 0xd560 ... 0xd5ef:
484 case 0xd600 ... 0xd663:
485 case 0xda00 ... 0xda6e:
486 case 0xda80 ... 0xda9e:
487 case 0xdb00 ... 0xdb7f:
488 case 0xdc00:
489 case 0xdc20 ... 0xdc21:
490 case 0xdd00 ... 0xdd17:
491 case 0xde00 ... 0xde09:
492 case 0xdf00 ... 0xdf1b:
493 case 0xe000 ... 0xe847:
494 case 0xf01e:
495 case 0xf717 ... 0xf719:
496 case 0xf720 ... 0xf723:
497 case 0x1000cd91 ... 0x1000cd96:
499 case 0x1000f008:
500 case 0x1000f021:
501 case 0x2000300f:
502 case 0x2000301c:
503 case 0x2000900f:
504 case 0x20009018:
505 case 0x3fc29d80 ... 0x3fc29d83:
506 case 0x3fe2e000 ... 0x3fe2e003:
507 case 0x3fc2ab80 ... 0x3fc2abd4:
508 case 0x3fc2bfc0 ... 0x3fc2bfc8:
509 case 0x3fc2d300 ... 0x3fc2d354:
510 case 0x3fc2dfc0 ... 0x3fc2dfc8:
511 /* 0x40801508/0x40801809/0x4080180a/0x40801909/0x4080190a */
512 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
517 /* 0x40880900/0x40880980 */
518 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
519 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
520 /* 0x40881500 */
521 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
522 /* 0x41000189/0x4100018a */
525 /* 0x41001388 */
526 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE27, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
527 /* 0x41001988 */
528 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0):
529 /* 0x41080000 */
530 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
531 /* 0x41080200 */
532 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0):
533 /* 0x41080900 */
534 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
535 /* 0x41080980 */
536 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
537 /* 0x41081080 */
538 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0):
539 /* 0x41081480/0x41081488 */
540 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
541 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
542 /* 0x41081980 */
543 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
553 case 0xc000:
554 case 0xc003:
555 case 0xc081:
556 case 0xc402 ... 0xc406:
557 case 0xc48c ... 0xc48f:
558 case 0xc560:
559 case 0xc5b5 ... 0xc5b7:
560 case 0xc5fc ... 0xc5ff:
561 case 0xc680 ... 0xc683:
562 case 0xc820:
563 case 0xc900:
564 case 0xc920:
565 case 0xca42:
566 case 0xca62:
567 case 0xca82:
568 case 0xcd00:
569 case 0xce03:
570 case 0xce10:
571 case 0xce14 ... 0xce17:
572 case 0xce44 ... 0xce49:
573 case 0xce4c ... 0xce4d:
574 case 0xcf0c:
575 case 0xcf10 ... 0xcf25:
576 case 0xd486 ... 0xd487:
577 case 0xd4e5 ... 0xd4e6:
578 case 0xd4e8 ... 0xd4ff:
579 case 0xd530:
580 case 0xd540 ... 0xd541:
581 case 0xd543:
582 case 0xdb58 ... 0xdb5f:
583 case 0xdb60 ... 0xdb63:
584 case 0xdb68 ... 0xdb69:
585 case 0xdb6d:
586 case 0xdb70 ... 0xdb71:
587 case 0xdb76:
588 case 0xdb7a:
589 case 0xdb7c ... 0xdb7f:
590 case 0xdd0c ... 0xdd13:
591 case 0xde02:
592 case 0xdf14 ... 0xdf1b:
593 case 0xe83c ... 0xe847:
594 case 0xf01e:
595 case 0xf717 ... 0xf719:
596 case 0xf720 ... 0xf723:
597 case 0x10000000 ... 0x10008fff:
598 case 0x1000c000 ... 0x1000dfff:
599 case 0x1000f008:
600 case 0x1000f021:
601 case 0x2000300f:
602 case 0x2000301c:
603 case 0x2000900f:
604 case 0x20009018:
605 case 0x3fc2ab80 ... 0x3fc2abd4:
606 case 0x3fc2b780:
607 case 0x3fc2bf80 ... 0x3fc2bf83:
608 case 0x3fc2bfc0 ... 0x3fc2bfc8:
609 case 0x3fc2d300 ... 0x3fc2d354:
610 case 0x3fc2dfc0 ... 0x3fc2dfc8:
611 case 0x3fe2e000 ... 0x3fe2e003:
612 case SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_PDE11, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
613 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0):
614 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_MODE, 0):
615 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_SAPU, RT1320_SDCA_CTL_SAPU_PROTECTION_STATUS, 0):
616 case SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0):
643 .max_register = 0x41081980,
656 .max_register = 0x41000192,
694 i = 0;
712 j = 0;
726 /* BIOS may set wake_capable. Make sure it is 0 as wake events are disabled. */
727 prop->wake_capable = 0;
729 return 0;
742 SDW_SDCA_CTL(func, entity, RT1320_SDCA_CTL_ACTUAL_POWER_STATE, 0), &val);
754 return 0;
776 min_addr = 0x10007000;
777 max_addr = 0x10007fff;
781 min_addr = 0x10008000;
782 max_addr = 0x10008fff;
793 regmap_write(rt1320->regmap, 0xc598, 0x00);
794 regmap_write(rt1320->regmap, min_addr, 0x67);
795 regmap_write(rt1320->regmap, min_addr + 0x1, 0x80);
796 regmap_write(rt1320->regmap, min_addr + 0x2, 0x00);
797 regmap_write(rt1320->regmap, min_addr + 0x3, 0x00);
799 regmap_write(rt1320->regmap, 0xd73c, 0x67);
800 regmap_write(rt1320->regmap, 0xd73d, 0x80);
801 regmap_write(rt1320->regmap, 0xd73e, 0x00);
802 regmap_write(rt1320->regmap, 0xd73f, 0x00);
806 if ((patch->size % 8) == 0) {
807 for (i = 0; i < patch->size; i += 8) {
808 addr = (ptr[i] & 0xff) | (ptr[i + 1] & 0xff) << 8 |
809 (ptr[i + 2] & 0xff) << 16 | (ptr[i + 3] & 0xff) << 24;
810 val = (ptr[i + 4] & 0xff) | (ptr[i + 5] & 0xff) << 8 |
811 (ptr[i + 6] & 0xff) << 16 | (ptr[i + 7] & 0xff) << 24;
814 dev_err(&slave->dev, "%s: the address 0x%x is wrong", __func__, addr);
817 if (val > 0xff) {
818 dev_err(&slave->dev, "%s: the value 0x%x is wrong", __func__, val);
833 for (i = 0; i < ARRAY_SIZE(rt1320_blind_write); i++) {
838 if (reg == 0x3fc2bfc7)
852 for (i = 0; i < ARRAY_SIZE(rt1320_vc_blind_write); i++) {
857 if (reg == 0x3fc2bf83)
860 if ((reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0)) &&
861 (val == 0x00)) {
865 dev_dbg(&slave->dev, "%s, RT1320_KR0_INT_READY=0x%x\n", __func__, tmp);
866 if (tmp == 0x1f)
878 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
887 for (i = 0; i < ARRAY_SIZE(rt1321_blind_write); i++) {
892 if (reg == 0x3fc2dfc3)
900 if (reg == SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PDE23, RT1320_SDCA_CTL_REQ_POWER_STATE, 0))
911 return 0;
928 if (rt1320->version_id < 0) {
937 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0), &_func_status);
938 dev_dbg(dev, "%s amp func_status=0x%x\n", __func__, amp_func_status);
957 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT0, RT1320_SDCA_CTL_FUNC_STATUS, 0),
962 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 0);
970 dev_dbg(dev, "%s ROM version=0x%x\n", __func__, val);
978 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), 3);
980 dev_dbg(dev, "%s version_id=%d, dev_id=0x%x\n", __func__, rt1320->version_id, rt1320->dev_id);
996 return 0;
1012 return 0;
1024 unsigned char ps0 = 0x0, ps3 = 0x3;
1030 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1036 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1043 return 0;
1052 unsigned char ps0 = 0x0, ps3 = 0x3;
1058 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps0);
1064 RT1320_SDCA_CTL_REQ_POWER_STATE, 0), ps3);
1071 return 0;
1083 const unsigned int interval_offset = 0xc0;
1084 unsigned int changed = 0, reg_base;
1096 gain_l_val = ucontrol->value.integer.value[0];
1099 gain_l_val = 0 - ((mc->max - gain_l_val) * interval_offset);
1100 gain_l_val &= 0xffff;
1106 gain_r_val = 0 - ((mc->max - gain_r_val) * interval_offset);
1107 gain_r_val &= 0xffff;
1110 return 0;
1122 for (i = 0; i < p->count; i++) {
1143 gain_val[i] = 0x1e00 - ((p->max - gain_val[i]) * interval_offset);
1144 gain_val[i] &= 0xffff;
1150 return 0;
1152 for (i = 0; i < p->count; i++) {
1169 if (err < 0)
1170 dev_err(&rt1320->sdw_slave->dev, "0x%08x can't be set\n", reg_base + i);
1184 unsigned int read_l, read_r, ctl_l = 0, ctl_r = 0;
1185 const unsigned int interval_offset = 0xc0;
1195 ctl_l = mc->max - (((0 - read_l) & 0xffff) / interval_offset);
1198 ctl_r = mc->max - (((0 - read_r) & 0xffff) / interval_offset);
1202 ucontrol->value.integer.value[0] = ctl_l;
1210 for (i = 0; i < p->count; i++) {
1227 ctl = p->max - (((0x1e00 - regvalue) & 0xffff) / interval_offset);
1231 return 0;
1239 for (i = 0; i < ARRAY_SIZE(rt1320->fu_mixer_mute); i++) {
1240 ch_mute = (rt1320->fu_dapm_mute || rt1320->fu_mixer_mute[i]) ? 0x01 : 0x00;
1262 if (err < 0)
1266 return 0;
1278 for (i = 0; i < p->count; i++)
1281 return 0;
1291 int err, changed = 0, i;
1293 for (i = 0; i < p->count; i++) {
1300 if (err < 0)
1317 uinfo->value.integer.min = 0;
1319 return 0;
1339 return 0;
1355 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_PPU21, RT1320_SDCA_CTL_POSTURE_NUMBER, 0), 0,
1358 static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -6525, 75, 0);
1359 static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -1725, 75, 0);
1365 0, 0x57, 0, rt1320_set_gain_get, rt1320_set_gain_put, out_vol_tlv),
1373 rt1320_set_gain_get, rt1320_set_gain_put, 4, 0x3f, in_vol_tlv, rt1320_dmic_fu_info),
1379 0, 1, 1);
1383 0, 1, 1);
1387 SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
1388 SND_SOC_DAPM_AIF_OUT("DP4TX", "DP4 Capture", 0, SND_SOC_NOPM, 0, 0),
1389 SND_SOC_DAPM_AIF_OUT("DP8-10TX", "DP8-10 Capture", 0, SND_SOC_NOPM, 0, 0),
1392 SND_SOC_DAPM_PGA("FU21", SND_SOC_NOPM, 0, 0, NULL, 0),
1393 SND_SOC_DAPM_SUPPLY("PDE 23", SND_SOC_NOPM, 0, 0,
1396 SND_SOC_DAPM_SUPPLY("PDE 11", SND_SOC_NOPM, 0, 0,
1398 SND_SOC_DAPM_ADC("FU 113", NULL, SND_SOC_NOPM, 0, 0),
1399 SND_SOC_DAPM_ADC("FU 14", NULL, SND_SOC_NOPM, 0, 0),
1400 SND_SOC_DAPM_PGA_E("FU", SND_SOC_NOPM, 0, 0, NULL, 0,
1404 SND_SOC_DAPM_SWITCH("OT23 L", SND_SOC_NOPM, 0, 0, &rt1320_spk_l_dac),
1405 SND_SOC_DAPM_SWITCH("OT23 R", SND_SOC_NOPM, 0, 0, &rt1320_spk_r_dac),
1410 SND_SOC_DAPM_PGA("AEC Data", SND_SOC_NOPM, 0, 0, NULL, 0),
1439 return 0;
1484 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
1485 dmic_port_config[0].num = 8;
1486 dmic_port_config[1].ch_mask = BIT(0) | BIT(1);
1490 dmic_port_config[0].ch_mask = BIT(0) | BIT(1);
1491 dmic_port_config[0].num = 8;
1553 SDW_SDCA_CTL(FUNC_NUM_AMP, RT1320_SDCA_ENT_CS21, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1557 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS113, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1562 SDW_SDCA_CTL(FUNC_NUM_MIC, RT1320_SDCA_ENT_CS14, RT1320_SDCA_CTL_SAMPLE_FREQ_INDEX, 0),
1566 return 0;
1582 return 0;
1602 return 0;
1606 if (ret < 0 && ret != -EACCES)
1609 return 0;
1696 rt1320->fu_mixer_mute[0] = rt1320->fu_mixer_mute[1] =
1703 if (ret < 0)
1747 return 0;
1751 * Version A/B will use the class id 0
1755 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x0, 0),
1756 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1320, 0x3, 0x1, 0),
1757 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1321, 0x3, 0x1, 0),
1767 return 0;
1771 return 0;
1783 return 0;
1796 slave->unattach_request = 0;
1801 return 0;