Lines Matching +full:- +full:4

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * rt1318.h -- Platform data for RT1318
100 /* Clock-1  (0xC001) */
101 #define RT1318_PLLIN_MASK			(0x7 << 4)
102 #define RT1318_PLLIN_BCLK0			(0x0 << 4)
103 #define RT1318_PLLIN_BCLK1			(0x1 << 4)
104 #define RT1318_PLLIN_RC				(0x2 << 4)
105 #define RT1318_PLLIN_MCLK			(0x3 << 4)
106 #define RT1318_PLLIN_SDW1			(0x4 << 4)
107 #define RT1318_PLLIN_SDW2			(0x5 << 4)
108 #define RT1318_PLLIN_SDW3			(0x6 << 4)
109 #define RT1318_PLLIN_SDW4			(0x7 << 4)
119 /* Clock-2  (0xC003) */
120 #define RT1318_DIV_AP_MASK			(0x3 << 4)
121 #define RT1318_DIV_AP_SFT			4
122 #define RT1318_DIV_AP_DIV1			(0x0 << 4)
123 #define RT1318_DIV_AP_DIV2			(0x1 << 4)
124 #define RT1318_DIV_AP_DIV4			(0x2 << 4)
125 #define RT1318_DIV_AP_DIV8			(0x3 << 4)
132 /* Clock-3  (0xC004) */
133 #define RT1318_AD_STO1_MASK			(0x7 << 4)
134 #define RT1318_AD_STO1_SFT			4
135 #define RT1318_AD_STO1_DIV1			(0x0 << 4)
136 #define RT1318_AD_STO1_DIV2			(0x1 << 4)
137 #define RT1318_AD_STO1_DIV4			(0x2 << 4)
138 #define RT1318_AD_STO1_DIV8			(0x3 << 4)
139 #define RT1318_AD_STO1_DIV16			(0x4 << 4)
148 /* Clock-4  (0xC005) */
149 #define RT1318_AD_ANA_STO1_MASK			(0x7 << 4)
150 #define RT1318_AD_ANA_STO1_SFT			4
151 #define RT1318_AD_ANA_STO1_DIV1			(0x0 << 4)
152 #define RT1318_AD_ANA_STO1_DIV2			(0x1 << 4)
153 #define RT1318_AD_ANA_STO1_DIV4			(0x2 << 4)
154 #define RT1318_AD_ANA_STO1_DIV8			(0x3 << 4)
155 #define RT1318_AD_ANA_STO1_DIV16		(0x4 << 4)
163 /* Clock-5  (0xC006) */
164 #define RT1318_DIV_FIFO_IN_MASK			(0x3 << 4)
165 #define RT1318_DIV_FIFO_IN_SFT			4
166 #define RT1318_DIV_FIFO_IN_DIV1			(0x0 << 4)
167 #define RT1318_DIV_FIFO_IN_DIV2			(0x1 << 4)
168 #define RT1318_DIV_FIFO_IN_DIV4			(0x2 << 4)
169 #define RT1318_DIV_FIFO_IN_DIV8			(0x3 << 4)
176 /* Clock-6  (0xC007) */
208 #define RT1318_SRCIN_F12288_MASK		(0x3 << 4)
209 #define RT1318_SRCIN_TCON1			(0x0 << 4)
210 #define RT1318_SRCIN_TCON2			(0x1 << 4)
211 #define RT1318_SRCIN_TCON4			(0x2 << 4)
212 #define RT1318_SRCIN_TCON8			(0x3 << 4)
248 #define RT1318_I2S_CH_RX_MASK			(0x3 << 4)
249 #define RT1318_I2S_CH_RX_2CH			(0x0 << 4)
250 #define RT1318_I2S_CH_RX_4CH			(0x1 << 4)
251 #define RT1318_I2S_CH_RX_6CH			(0x2 << 4)
252 #define RT1318_I2S_CH_RX_8CH			(0x3 << 4)
261 #define RT1318_I2S_TX_CHL_MASK			(0x7 << 4)
262 #define RT1318_I2S_TX_CHL_SFT			4
263 #define RT1318_I2S_TX_CHL_16			(0x0 << 4)
264 #define RT1318_I2S_TX_CHL_20			(0x1 << 4)
265 #define RT1318_I2S_TX_CHL_24			(0x2 << 4)
266 #define RT1318_I2S_TX_CHL_32			(0x3 << 4)
267 #define RT1318_I2S_TX_CHL_8			(0x4 << 4)
276 #define RT1318_TDM_I2S_TX_L_DAC1_1_MASK		(0x7 << 4)
278 #define RT1318_TDM_I2S_TX_L_DAC1_1_SFT		4
322 /* PLL pre-defined M/N/K */