791 static int rt1318_pll_calc(const unsigned int freq_in,  in rt1318_pll_calc()  argument
797 	int red_t = abs(freq_out - freq_in);  in rt1318_pll_calc()
800 	if (RT1318_PLL_INP_MAX < freq_in || RT1318_PLL_INP_MIN > freq_in)  in rt1318_pll_calc()
804 		if (freq_in == pll_preset_table[i].pll_in &&  in rt1318_pll_calc()
823 		in_t = freq_in / (k_bypass ? 1 : (k + 2));  in rt1318_pll_calc()
867 			unsigned int freq_in, unsigned int freq_out)  in rt1318_set_dai_pll()  argument
874 	if (!freq_in || !freq_out) {  in rt1318_set_dai_pll()
881 	if (source == rt1318->pll_src && freq_in == rt1318->pll_in &&  in rt1318_set_dai_pll()
923 	ret = rt1318_pll_calc(freq_in, freq_out, &pll_code);  in rt1318_set_dai_pll()
925 		dev_err(component->dev, "Unsupport input clock %d\n", freq_in);  in rt1318_set_dai_pll()
942 	rt1318->pll_in = freq_in;  in rt1318_set_dai_pll()