23 	{ 0x3004, 0x00 },
24 	{ 0x3005, 0x00 },
25 	{ 0x3206, 0x00 },
26 	{ 0xc001, 0x00 },
27 	{ 0xc002, 0x00 },
28 	{ 0xc003, 0x00 },
29 	{ 0xc004, 0x00 },
30 	{ 0xc005, 0x00 },
31 	{ 0xc006, 0x00 },
32 	{ 0xc007, 0x00 },
33 	{ 0xc008, 0x00 },
34 	{ 0xc009, 0x00 },
35 	{ 0xc00a, 0x00 },
36 	{ 0xc00b, 0x00 },
37 	{ 0xc00c, 0x00 },
38 	{ 0xc00d, 0x00 },
39 	{ 0xc00e, 0x00 },
40 	{ 0xc00f, 0x00 },
41 	{ 0xc010, 0xa5 },
42 	{ 0xc011, 0x00 },
43 	{ 0xc012, 0xff },
44 	{ 0xc013, 0xff },
45 	{ 0xc014, 0x40 },
46 	{ 0xc015, 0x00 },
47 	{ 0xc016, 0x00 },
48 	{ 0xc017, 0x00 },
49 	{ 0xc605, 0x30 },
50 	{ 0xc700, 0x0a },
51 	{ 0xc701, 0xaa },
52 	{ 0xc702, 0x1a },
53 	{ 0xc703, 0x0a },
54 	{ 0xc710, 0x80 },
55 	{ 0xc711, 0x00 },
56 	{ 0xc712, 0x3e },
57 	{ 0xc713, 0x80 },
58 	{ 0xc714, 0x80 },
59 	{ 0xc715, 0x06 },
60 	{ 0xd101, 0x00 },
61 	{ 0xd102, 0x30 },
62 	{ 0xd103, 0x00 },
63 …{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0x0…
64 	{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_L), 0x01 },
65 	{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_FU21, RT1316_SDCA_CTL_FU_MUTE, CH_R), 0x01 },
66 	{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x01 },
67 …{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x0…
68 …{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x0…
69 …{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0), 0x0…
73 	{ 0xc710, 0x17 },
74 	{ 0xc711, 0x80 },
75 	{ 0xc712, 0x26 },
76 	{ 0xc713, 0x06 },
77 	{ 0xc714, 0x80 },
78 	{ 0xc715, 0x06 },
79 	{ 0xc702, 0x0a },
80 	{ 0xc703, 0x0a },
81 	{ 0xc001, 0x45 },
82 	{ 0xc003, 0x00 },
83 	{ 0xc004, 0x11 },
84 	{ 0xc005, 0x00 },
85 	{ 0xc006, 0x00 },
86 	{ 0xc106, 0x00 },
87 	{ 0xc007, 0x11 },
88 	{ 0xc008, 0x11 },
89 	{ 0xc009, 0x00 },
91 	{ 0x2f0a, 0x00 },
92 	{ 0xd101, 0xf0 },
93 	{ 0xd103, 0x9b },
94 	{ 0x2f36, 0x8e },
95 	{ 0x3206, 0x80 },
96 	{ 0x3211, 0x0b },
97 	{ 0x3216, 0x06 },
98 	{ 0xc614, 0x20 },
99 	{ 0xc615, 0x0a },
100 	{ 0xc616, 0x02 },
101 	{ 0xc617, 0x00 },
102 	{ 0xc60b, 0x10 },
103 	{ 0xc60e, 0x05 },
104 	{ 0xc102, 0x00 },
105 	{ 0xc090, 0xb0 },
106 	{ 0xc00f, 0x01 },
107 	{ 0xc09c, 0x7b },
109 	{ 0xc602, 0x07 },
110 	{ 0xc603, 0x07 },
111 	{ 0xc0a3, 0x71 },
112 	{ 0xc00b, 0x30 },
113 	{ 0xc093, 0x80 },
114 	{ 0xc09d, 0x80 },
115 	{ 0xc0b0, 0x77 },
116 	{ 0xc010, 0xa5 },
117 	{ 0xc050, 0x83 },
118 	{ 0x2f55, 0x03 },
119 	{ 0x3217, 0xb5 },
120 	{ 0x3202, 0x02 },
122 	{ SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0x00 },
125 	{ 0x2232, 0x80 },
126 	{ 0xc0b0, 0x77 },
127 	{ 0xc011, 0x00 },
128 	{ 0xc020, 0x00 },
129 	{ 0xc023, 0x00 },
130 	{ 0x3101, 0x00 },
131 	{ 0x3004, 0xa0 },
132 	{ 0x3005, 0xb1 },
133 	{ 0xc007, 0x11 },
134 	{ 0xc008, 0x11 },
135 	{ 0xc009, 0x00 },
136 	{ 0xc022, 0xd6 },
137 	{ 0xc025, 0xd6 },
139 	{ 0xd001, 0x03 },
140 	{ 0xd002, 0xbf },
141 	{ 0xd003, 0x03 },
142 	{ 0xd004, 0xbf },
148 	case 0x2f0a:  in rt1316_readable_register()
149 	case 0x2f36:  in rt1316_readable_register()
150 	case 0x3203 ... 0x320e:  in rt1316_readable_register()
151 	case 0xc000 ... 0xc7b4:  in rt1316_readable_register()
152 	case 0xcf00 ... 0xcf03:  in rt1316_readable_register()
153 	case 0xd101 ... 0xd103:  in rt1316_readable_register()
154 	case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0):  in rt1316_readable_register()
157 	case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE23, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):  in rt1316_readable_register()
158 	case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE27, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):  in rt1316_readable_register()
159 	case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE22, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):  in rt1316_readable_register()
160 	case SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_PDE24, RT1316_SDCA_CTL_REQ_POWER_STATE, 0):  in rt1316_readable_register()
170 	case 0xc000:  in rt1316_volatile_register()
171 	case 0xc093:  in rt1316_volatile_register()
172 	case 0xc09d:  in rt1316_volatile_register()
173 	case 0xc0a3:  in rt1316_volatile_register()
174 	case 0xc201:  in rt1316_volatile_register()
175 	case 0xc427 ... 0xc428:  in rt1316_volatile_register()
176 	case 0xd102:  in rt1316_volatile_register()
188 	.max_register = 0x4108ffff,
211 	prop->source_ports = 0x04; /* BITMAP: 00000100 */  in rt1316_read_prop()
212 	prop->sink_ports = 0x2; /* BITMAP:  00000010 */  in rt1316_read_prop()
220 	i = 0;  in rt1316_read_prop()
238 	j = 0;  in rt1316_read_prop()
254 	return 0;  in rt1316_read_prop()
261 	for (i = 0; i < rt1316->bq_params_cnt; i += 3) {  in rt1316_apply_bq_params()
273 		return 0;  in rt1316_io_init()
290 	regmap_write(rt1316->regmap, 0xc000, 0x02);  in rt1316_io_init()
309 	return 0;  in rt1316_io_init()
325 		return 0;  in rt1316_update_status()
337 	unsigned char ps0 = 0x0, ps3 = 0x3;  in rt1316_classd_event()
343 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_classd_event()
347 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_classd_event()
351 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_classd_event()
357 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_classd_event()
361 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_classd_event()
365 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_classd_event()
373 	return 0;  in rt1316_classd_event()
382 	unsigned char ps0 = 0x0, ps3 = 0x3;  in rt1316_pde24_event()
388 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_pde24_event()
394 				RT1316_SDCA_CTL_REQ_POWER_STATE, 0),  in rt1316_pde24_event()
398 	return 0;  in rt1316_pde24_event()
415 	SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_UDMPU21, RT1316_SDCA_CTL_UDMPU_CLUSTER, 0), 0,
425 	0xc010, 6, rt1316_dac_output_vol_select);
434 		SDW_SDCA_CTL(FUNC_NUM_SMART_AMP, RT1316_SDCA_ENT_XU24, RT1316_SDCA_CTL_BYPASS, 0), 0, 1, 0),
437 	SOC_SINGLE("Left V Tag Select", 0x3004, 0, 7, 0),
438 	SOC_SINGLE("Left I Tag Select", 0x3004, 4, 7, 0),
439 	SOC_SINGLE("Right V Tag Select", 0x3005, 0, 7, 0),
440 	SOC_SINGLE("Right I Tag Select", 0x3005, 4, 7, 0),
443 	SOC_DOUBLE("Isense Mixer Switch", 0xc605, 2, 0, 1, 1),
444 	SOC_DOUBLE("Vsense Mixer Switch", 0xc605, 3, 1, 1, 1),
454 		0, 1, 1);
458 	SND_SOC_DAPM_AIF_IN("DP1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
459 	SND_SOC_DAPM_AIF_OUT("DP2TX", "DP2 Capture", 0, SND_SOC_NOPM, 0, 0),
462 	SND_SOC_DAPM_SWITCH("DAC", SND_SOC_NOPM, 0, 0, &rt1316_sto_dac),
465 	SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
471 	SND_SOC_DAPM_SUPPLY("PDE 24", SND_SOC_NOPM, 0, 0,
474 	SND_SOC_DAPM_PGA("I Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
475 	SND_SOC_DAPM_PGA("V Sense", SND_SOC_NOPM, 0, 0, NULL, 0),
499 	return 0;  in rt1316_set_sdw_stream()
514 	struct sdw_stream_config stream_config = {0};  in rt1316_sdw_hw_params()
515 	struct sdw_port_config port_config = {0};  in rt1316_sdw_hw_params()
544 	return 0;  in rt1316_sdw_hw_params()
560 	return 0;  in rt1316_sdw_pcm_hw_free()
574 	int ret = 0;  in rt1316_sdw_parse_dt()
584 			if (ret < 0)  in rt1316_sdw_parse_dt()
602 		return 0;  in rt1316_sdw_component_probe()
605 	if (ret < 0 && ret != -EACCES)  in rt1316_sdw_component_probe()
611 	return 0;  in rt1316_sdw_component_probe()
684 	if (ret < 0)  in rt1316_sdw_init()
704 	return 0;  in rt1316_sdw_init()
724 	return 0;  in rt1316_sdw_remove()
728 	SDW_SLAVE_ENTRY_EXT(0x025d, 0x1316, 0x3, 0x1, 0),
738 		return 0;  in rt1316_dev_suspend()
742 	return 0;  in rt1316_dev_suspend()
754 		return 0;  in rt1316_dev_resume()
769 	slave->unattach_request = 0;  in rt1316_dev_resume()
773 	return 0;  in rt1316_dev_resume()