Lines Matching +full:0 +full:xcfff
31 case 0x00e0: in rt1308_readable_register()
32 case 0x00f0: in rt1308_readable_register()
33 case 0x2f01 ... 0x2f07: in rt1308_readable_register()
34 case 0x3000 ... 0x3001: in rt1308_readable_register()
35 case 0x3004 ... 0x3005: in rt1308_readable_register()
36 case 0x3008: in rt1308_readable_register()
37 case 0x300a: in rt1308_readable_register()
38 case 0xc000 ... 0xcff3: in rt1308_readable_register()
48 case 0x2f01 ... 0x2f07: in rt1308_volatile_register()
49 case 0x3000 ... 0x3001: in rt1308_volatile_register()
50 case 0x3004 ... 0x3005: in rt1308_volatile_register()
51 case 0x3008: in rt1308_volatile_register()
52 case 0x300a: in rt1308_volatile_register()
53 case 0xc000: in rt1308_volatile_register()
54 case 0xc710: in rt1308_volatile_register()
55 case 0xcf01: in rt1308_volatile_register()
56 case 0xc860 ... 0xc863: in rt1308_volatile_register()
57 case 0xc870 ... 0xc873: in rt1308_volatile_register()
69 .max_register = 0xcfff,
94 value = 0x0; in rt1308_clock_config()
97 value = 0x1; in rt1308_clock_config()
100 value = 0x2; in rt1308_clock_config()
103 value = 0x3; in rt1308_clock_config()
106 value = 0x4; in rt1308_clock_config()
109 value = 0x5; in rt1308_clock_config()
115 regmap_write(rt1308->regmap, 0xe0, value); in rt1308_clock_config()
116 regmap_write(rt1308->regmap, 0xf0, value); in rt1308_clock_config()
120 return 0; in rt1308_clock_config()
137 prop->source_ports = 0x00; /* BITMAP: 00010100 (not enable yet) */ in rt1308_read_prop()
138 prop->sink_ports = 0x2; /* BITMAP: 00000010 */ in rt1308_read_prop()
148 i = 0; in rt1308_read_prop()
164 return 0; in rt1308_read_prop()
173 regmap_write(rt1308->regmap, 0xc7f0, 0x04); in rt1308_apply_calib_params()
174 regmap_write(rt1308->regmap, 0xc7f1, 0xfe); in rt1308_apply_calib_params()
176 regmap_write(rt1308->regmap, 0xc7f0, 0x44); in rt1308_apply_calib_params()
178 regmap_write(rt1308->regmap, 0xc240, 0x10); in rt1308_apply_calib_params()
180 regmap_read(rt1308->regmap, 0xc861, &tmp); in rt1308_apply_calib_params()
182 regmap_read(rt1308->regmap, 0xc860, &tmp); in rt1308_apply_calib_params()
184 regmap_read(rt1308->regmap, 0xc863, &tmp); in rt1308_apply_calib_params()
186 regmap_read(rt1308->regmap, 0xc862, &tmp); in rt1308_apply_calib_params()
188 regmap_read(rt1308->regmap, 0xc871, &tmp); in rt1308_apply_calib_params()
190 regmap_read(rt1308->regmap, 0xc870, &tmp); in rt1308_apply_calib_params()
192 regmap_read(rt1308->regmap, 0xc873, &tmp); in rt1308_apply_calib_params()
194 regmap_read(rt1308->regmap, 0xc872, &tmp); in rt1308_apply_calib_params()
196 dev_dbg(&rt1308->sdw_slave->dev, "%s m_btl_l=0x%x, m_btl_r=0x%x\n", __func__, in rt1308_apply_calib_params()
198 dev_dbg(&rt1308->sdw_slave->dev, "%s c_btl_l=0x%x, c_btl_r=0x%x\n", __func__, in rt1308_apply_calib_params()
206 for (i = 0; i < rt1308->bq_params_cnt; i += 3) { in rt1308_apply_bq_params()
216 int ret = 0; in rt1308_io_init()
220 return 0; in rt1308_io_init()
235 regmap_read(rt1308->regmap, 0xcf01, &hibernation_flag); in rt1308_io_init()
236 if ((hibernation_flag != 0x00) && rt1308->first_hw_init) in rt1308_io_init()
240 regmap_write(rt1308->regmap, RT1308_SDW_RESET, 0); in rt1308_io_init()
242 regmap_read(rt1308->regmap, 0xc710, &tmp); in rt1308_io_init()
244 dev_dbg(dev, "%s, hw_ver=0x%x\n", __func__, rt1308->hw_ver); in rt1308_io_init()
247 regmap_write(rt1308->regmap, 0xc103, 0xc0); in rt1308_io_init()
248 regmap_write(rt1308->regmap, 0xc030, 0x17); in rt1308_io_init()
249 regmap_write(rt1308->regmap, 0xc031, 0x81); in rt1308_io_init()
250 regmap_write(rt1308->regmap, 0xc032, 0x26); in rt1308_io_init()
251 regmap_write(rt1308->regmap, 0xc040, 0x80); in rt1308_io_init()
252 regmap_write(rt1308->regmap, 0xc041, 0x80); in rt1308_io_init()
253 regmap_write(rt1308->regmap, 0xc042, 0x06); in rt1308_io_init()
254 regmap_write(rt1308->regmap, 0xc052, 0x0a); in rt1308_io_init()
255 regmap_write(rt1308->regmap, 0xc080, 0x0a); in rt1308_io_init()
256 regmap_write(rt1308->regmap, 0xc060, 0x02); in rt1308_io_init()
257 regmap_write(rt1308->regmap, 0xc061, 0x75); in rt1308_io_init()
258 regmap_write(rt1308->regmap, 0xc062, 0x05); in rt1308_io_init()
259 regmap_write(rt1308->regmap, 0xc171, 0x07); in rt1308_io_init()
260 regmap_write(rt1308->regmap, 0xc173, 0x0d); in rt1308_io_init()
262 regmap_write(rt1308->regmap, 0xc311, 0x7f); in rt1308_io_init()
263 regmap_write(rt1308->regmap, 0xc300, 0x09); in rt1308_io_init()
265 regmap_write(rt1308->regmap, 0xc311, 0x4f); in rt1308_io_init()
266 regmap_write(rt1308->regmap, 0xc300, 0x0b); in rt1308_io_init()
268 regmap_write(rt1308->regmap, 0xc900, 0x5a); in rt1308_io_init()
269 regmap_write(rt1308->regmap, 0xc1a0, 0x84); in rt1308_io_init()
270 regmap_write(rt1308->regmap, 0xc1a1, 0x01); in rt1308_io_init()
271 regmap_write(rt1308->regmap, 0xc360, 0x78); in rt1308_io_init()
272 regmap_write(rt1308->regmap, 0xc361, 0x87); in rt1308_io_init()
273 regmap_write(rt1308->regmap, 0xc0a1, 0x71); in rt1308_io_init()
274 regmap_write(rt1308->regmap, 0xc210, 0x00); in rt1308_io_init()
275 regmap_write(rt1308->regmap, 0xc070, 0x00); in rt1308_io_init()
276 regmap_write(rt1308->regmap, 0xc100, 0xd7); in rt1308_io_init()
277 regmap_write(rt1308->regmap, 0xc101, 0xd7); in rt1308_io_init()
282 regmap_write(rt1308->regmap, 0xcf01, 0x01); in rt1308_io_init()
314 return 0; in rt1308_update_status()
329 if (ret < 0) in rt1308_bus_config()
341 return 0; in rt1308_interrupt_callback()
357 0x3, 0x3); in rt1308_classd_event()
364 0x3, 0); in rt1308_classd_event()
372 return 0; in rt1308_classd_event()
383 RT1308_SDW_OFFSET | (RT1308_DATA_PATH << 4), 0,
404 SND_SOC_DAPM_AIF_IN("AIF1RX", "DP1 Playback", 0, SND_SOC_NOPM, 0, 0),
408 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 7, 0, NULL, 0),
410 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 6, 0, NULL, 0),
412 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 5, 0, NULL, 0),
414 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 4, 0, NULL, 0),
416 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 2, 0, NULL, 0),
418 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 1, 0, NULL, 0),
420 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 0, 0, NULL, 0),
422 RT1308_SDW_OFFSET | (RT1308_POWER << 4), 3, 0, NULL, 0),
425 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 5, 0, NULL, 0),
427 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 4, 0, NULL, 0),
429 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 2, 0, NULL, 0),
431 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 1, 0, NULL, 0),
433 RT1308_SDW_OFFSET_BYTE1 | (RT1308_POWER << 4), 0, 0, NULL, 0),
436 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 4, 0, NULL, 0),
438 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 3, 0, NULL, 0),
440 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 2, 0, NULL, 0),
442 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 1, 0, NULL, 0),
444 RT1308_SDW_OFFSET_BYTE2 | (RT1308_POWER << 4), 0, 0, NULL, 0),
447 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
448 SND_SOC_DAPM_SWITCH("DAC L", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_l),
449 SND_SOC_DAPM_SWITCH("DAC R", SND_SOC_NOPM, 0, 0, &rt1308_sto_dac_r),
452 SND_SOC_DAPM_PGA_E("CLASS D", SND_SOC_NOPM, 0, 0, NULL, 0,
497 return 0; in rt1308_set_sdw_stream()
525 return 0; in rt1308_sdw_set_tdm_slot()
534 struct sdw_stream_config stream_config = {0}; in rt1308_sdw_hw_params()
535 struct sdw_port_config port_config = {0}; in rt1308_sdw_hw_params()
585 return 0; in rt1308_sdw_pcm_hw_free()
601 int ret = 0; in rt1308_sdw_parse_dt()
611 if (ret < 0) in rt1308_sdw_parse_dt()
629 return 0; in rt1308_sdw_component_probe()
632 if (ret < 0 && ret != -EACCES) in rt1308_sdw_component_probe()
638 return 0; in rt1308_sdw_component_probe()
706 if (ret < 0) in rt1308_sdw_init()
726 return 0; in rt1308_sdw_init()
746 return 0; in rt1308_sdw_remove()
750 SDW_SLAVE_ENTRY_EXT(0x025d, 0x1308, 0x2, 0, 0),
760 return 0; in rt1308_dev_suspend()
764 return 0; in rt1308_dev_suspend()
776 return 0; in rt1308_dev_resume()
791 slave->unattach_request = 0; in rt1308_dev_resume()
793 regcache_sync_region(rt1308->regmap, 0xc000, 0xcfff); in rt1308_dev_resume()
795 return 0; in rt1308_dev_resume()