Lines Matching +full:digital +full:- +full:input +full:- +full:short +full:- +full:circuit +full:- +full:detection
1 // SPDX-License-Identifier: GPL-2.0-only
8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
35 #define NUVOTON_CODEC_DAI "nau8825-hifi"
41 /* cross talk suppression detection */
83 /* ratio for input clk freq */
198 /* register backup table when cross talk detection */
223 * nau8825_sema_acquire - acquire the semaphore of nau88l25
233 * this function returns -ETIME. If the sleep is interrupted by a signal,
234 * this function will return -EINTR. It returns 0 if the semaphore was
246 ret = down_timeout(&nau8825->xtalk_sem, timeout);
248 dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
250 ret = down_trylock(&nau8825->xtalk_sem);
252 dev_warn(nau8825->dev, "Acquire semaphore fail\n");
259 * nau8825_sema_release - release the semaphore of nau88l25
267 up(&nau8825->xtalk_sem);
271 * nau8825_sema_reset - reset the semaphore for nau88l25
279 nau8825->xtalk_sem.count = 1;
283 * nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level.
290 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
311 /* only handle volume from 0dB to minimum -54dB */
319 value = to - volume + from;
320 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
329 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
335 * nau8825_intlog10_dec3 - Computes log10 of a value, rounding the result to 3 decimal places.
336 * @value: input for log10
346 * nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain.
368 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
370 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
371 sidetone = SIDETONE_BASE - gain * 2;
384 return -EINVAL;
391 if (nau8825->xtalk_baktab_initialized)
396 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
399 nau8825->xtalk_baktab_initialized = true;
406 if (!nau8825->xtalk_baktab_initialized)
423 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
427 nau8825->xtalk_baktab_initialized = false;
433 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
442 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
446 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
451 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
456 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
460 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
463 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
466 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
474 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
482 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
483 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
484 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
485 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
486 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
487 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
488 /* Enable internal VCO clock for detection signal generated */
489 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
491 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
496 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
498 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
506 /* Backup those registers changed by cross talk detection */
509 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
517 if (index != -EINVAL) {
525 /* Config channel path and digital gain */
526 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
529 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
535 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
541 regmap_update_bits(nau8825->regmap,
544 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
545 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
548 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
556 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
559 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
563 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
564 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
568 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
572 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
576 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
578 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
582 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
585 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
588 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
591 if (!nau8825->irq)
592 regmap_update_bits(nau8825->regmap,
599 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
610 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
612 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
615 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
625 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
630 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
633 switch (nau8825->xtalk_state) {
636 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
642 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
651 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
658 regmap_update_bits(nau8825->regmap,
665 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
672 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
686 switch (nau8825->xtalk_state) {
689 * path and cross talk detection parameters for preparation.
693 /* Trigger right headphone impedance detection */
694 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
701 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
702 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
703 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
704 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
705 /* Disable then re-enable IMM mode to update */
707 /* Trigger left headphone impedance detection */
708 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
714 * detection sine wave output finish. Then, we can calculate
718 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
719 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
720 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
721 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
724 nau8825->xtalk_state = NAU8825_XTALK_IMM;
728 * signal level vlues are ready. The side tone gain is deter-
733 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
734 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
735 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
736 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
739 nau8825->xtalk_state = NAU8825_XTALK_DONE;
755 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
758 /* Delay jack report until cross talk detection process
760 * preparation before cross talk detection is still working.
761 * Meanwhile, the protection of the cross talk detection
764 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
765 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
766 nau8825->xtalk_event_mask);
768 nau8825->xtalk_protect = false;
778 if (nau8825->xtalk_enable && nau8825->xtalk_state !=
780 cancel_work_sync(&nau8825->xtalk_work);
785 nau8825->xtalk_state = NAU8825_XTALK_DONE;
786 nau8825->xtalk_protect = false;
861 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
866 regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA,
869 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
872 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
874 regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA,
887 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
892 msleep(nau8825->adc_delay);
893 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
897 if (!nau8825->irq)
898 regmap_update_bits(nau8825->regmap,
902 return -EINVAL;
911 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
918 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
922 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
926 return -EINVAL;
935 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
941 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
943 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
944 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
947 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
952 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
954 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
955 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
959 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
964 return -EINVAL;
973 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
975 struct regmap *regmap = nau8825->regmap;
978 dev_dbg(nau8825->dev, "system clock control : POWER OFF\n");
981 * detection and button press if jack inserted; otherwise,
999 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
1001 if (!component->regmap)
1002 return -EINVAL;
1004 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
1005 ucontrol->value.bytes.data, params->max);
1013 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
1016 if (!component->regmap)
1017 return -EINVAL;
1019 data = kmemdup(ucontrol->value.bytes.data,
1020 params->max, GFP_KERNEL | GFP_DMA);
1022 return -ENOMEM;
1024 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1026 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1027 data, params->max);
1028 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1059 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1060 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1061 static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1062 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1063 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1125 /* ADC for button press detection. A dapm supply widget is used to
1176 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1242 regmap_read(nau8825->regmap,
1249 regmap_read(nau8825->regmap,
1261 struct snd_soc_component *component = dai->component;
1265 osr = nau8825_get_osr(nau8825, substream->stream);
1266 if (!osr || !osr->osr)
1267 return -EINVAL;
1269 return snd_pcm_hw_constraint_minmax(substream->runtime,
1271 0, CLK_DA_AD_MAX / osr->osr);
1278 struct snd_soc_component *component = dai->component;
1282 int err = -EINVAL;
1292 osr = nau8825_get_osr(nau8825, substream->stream);
1293 if (!osr || !osr->osr)
1295 if (params_rate(params) * osr->osr > CLK_DA_AD_MAX)
1297 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1298 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1300 osr->clk_src << NAU8825_CLK_DAC_SRC_SFT);
1302 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1304 osr->clk_src << NAU8825_CLK_ADC_SRC_SFT);
1307 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
1319 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1341 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1354 struct snd_soc_component *component = codec_dai->component;
1365 return -EINVAL;
1375 return -EINVAL;
1396 return -EINVAL;
1401 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1405 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1415 * nau8825_set_tdm_slot - configure DAI TDM.
1428 struct snd_soc_component *component = dai->component;
1433 dev_err(nau8825->dev, "Only support 4 or 8 slots!\n");
1434 return -EINVAL;
1437 /* The driver is limited to 1-channel for ADC, and 2-channel for DAC on TDM mode */
1440 dev_err(nau8825->dev,
1441 "The limitation is 1-channel for ADC, and 2-channel for DAC on TDM mode.\n");
1442 return -EINVAL;
1449 dev_err(nau8825->dev,
1451 return -EINVAL;
1456 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1458 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, &value);
1495 return -EINVAL;
1498 ctrl_val |= adc_s - 1;
1500 regmap_update_bits(nau8825->regmap, NAU8825_REG_TDM_CTRL,
1504 regmap_update_bits(nau8825->regmap, NAU8825_REG_LEFT_TIME_SLOT,
1522 .name = "nau8825-hifi",
1541 * nau8825_enable_jack_detect - Specify a jack for event reporting
1554 struct regmap *regmap = nau8825->regmap;
1556 nau8825->jack = jack;
1558 if (!nau8825->jack) {
1564 /* Ground HP Outputs[1:0], needed for headset auto detection
1593 /* this will restart the entire jack detection process including MIC/GND
1607 /* Reset the intrruption status from rightmost bit if the corres-
1621 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1622 struct regmap *regmap = nau8825->regmap;
1624 /* Force to cancel the cross talk detection process */
1640 /* Enable the insertion interruption, disable the ejection inter-
1641 * ruption, and then bypass de-bounce circuit.
1658 /* Close clock for jack type detection at manual mode */
1665 struct regmap *regmap = nau8825->regmap;
1671 /* Enable headset jack type detection complete interruption and
1679 /* Raise up the internal clock for jack detection */
1697 /* Not bypass de-bounce circuit */
1704 /* Restart the jack detection process at auto mode */
1731 struct regmap *regmap = nau8825->regmap;
1732 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1788 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1798 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1801 (nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT) |
1802 (nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT));
1803 dev_dbg(nau8825->dev, "adc_mg1:%x, adc_mg2:%x\n", adc_mg1, adc_mg2);
1807 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1822 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1837 dev_err(nau8825->dev, "Jack broken.\n");
1838 return -EINVAL;
1846 struct regmap *regmap = nau8825->regmap;
1847 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1855 nau8825->high_imped = true;
1857 nau8825->high_imped = false;
1865 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1885 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1905 /* Detection failure case */
1906 dev_warn(nau8825->dev,
1907 "Detection failure. Try the manually mechanism for jack type checking.\n");
1938 struct regmap *regmap = nau8825->regmap;
1942 dev_err(nau8825->dev, "failed to read irq status\n");
1958 /* upper 8 bits of the register are for short pressed keys,
1959 * lower 8 bits - for long pressed buttons
1961 nau8825->button_pressed = nau8825_button_decode(
1964 event |= nau8825->button_pressed;
1973 if (nau8825->xtalk_enable && !nau8825->high_imped) {
1977 if (!nau8825->xtalk_protect) {
1978 /* Raise protection for cross talk de-
1980 * The driver has to cancel the pro-
1985 nau8825->xtalk_protect = true;
1988 nau8825->xtalk_protect = false;
1990 /* Startup cross talk detection process */
1991 if (nau8825->xtalk_protect) {
1992 nau8825->xtalk_state =
1994 schedule_work(&nau8825->xtalk_work);
2001 if (nau8825->xtalk_protect) {
2003 nau8825->xtalk_protect = false;
2007 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
2015 * talk detection process is done.
2017 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
2018 nau8825->xtalk_event = event;
2019 nau8825->xtalk_event_mask = event_mask;
2022 /* crosstalk detection enable and process on going */
2023 if (nau8825->xtalk_enable && nau8825->xtalk_protect)
2024 schedule_work(&nau8825->xtalk_work);
2031 * circuit which can get rid of unstable status.
2041 /* Enable interruption for jack type detection at audo
2053 /* Delay jack report until cross talk detection is done. It can avoid
2054 * application to do playback preparation when cross talk detection
2058 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
2059 snd_soc_jack_report(nau8825->jack, event, event_mask);
2066 struct regmap *regmap = nau8825->regmap;
2070 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
2073 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
2076 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
2080 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
2083 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
2086 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
2089 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
2091 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
2093 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
2095 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
2097 /* Enable short press and release interruptions */
2105 struct regmap *regmap = nau8825->regmap;
2110 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
2112 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
2118 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
2119 /* Disable Boost Driver, Automatic Short circuit protection enable */
2128 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
2131 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
2134 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
2137 /* jkdet_polarity - 1 is for active-low */
2138 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
2142 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
2145 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
2151 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
2155 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
2157 if (nau8825->sar_threshold_num)
2169 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
2173 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
2175 * the analog and digital DAC circuit.
2177 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
2199 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
2201 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
2203 /* Disable short Frame Sync detection logic */
2209 nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT);
2231 nau8825->dapm = dapm;
2240 /* Cancel and reset cross tak suppresstion detection funciton */
2245 * nau8825_calc_fll_param - Calculate FLL parameters.
2261 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
2270 return -EINVAL;
2271 fll_param->clk_ref_div = fll_pre_scalar[i].val;
2279 return -EINVAL;
2280 fll_param->ratio = fll_ratio[i].val;
2283 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
2298 return -EINVAL;
2299 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
2301 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2302 * input based on FDCO, FREF and FLL ratio.
2304 fvco = div_u64(fvco_max << fll_param->fll_frac_num, fref * fll_param->ratio);
2305 fll_param->fll_int = (fvco >> fll_param->fll_frac_num) & 0x3FF;
2306 if (fll_param->fll_frac_num == 16)
2307 fll_param->fll_frac = fvco & 0xFFFF;
2309 fll_param->fll_frac = fvco & 0xFFFFFF;
2316 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2318 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
2320 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2322 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2323 /* FLL 16/24 bit fractional input */
2324 if (fll_param->fll_frac_num == 16)
2325 regmap_write(nau8825->regmap, NAU8825_REG_FLL2,
2326 fll_param->fll_frac);
2328 regmap_write(nau8825->regmap, NAU8825_REG_FLL2_LOWER,
2329 fll_param->fll_frac & 0xffff);
2330 regmap_write(nau8825->regmap, NAU8825_REG_FLL2_UPPER,
2331 (fll_param->fll_frac >> 16) & 0xff);
2333 /* FLL 10-bit integer input */
2334 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2335 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2336 /* FLL pre-scaler */
2337 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
2339 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
2340 /* select divided VCO input */
2341 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2343 /* Disable free-running mode */
2344 regmap_update_bits(nau8825->regmap,
2346 if (fll_param->fll_frac) {
2348 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2353 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2358 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2361 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2374 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
2382 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2385 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
2391 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2400 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2401 if (IS_ERR(nau8825->mclk)) {
2402 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2406 if (!nau8825->mclk_freq) {
2407 ret = clk_prepare_enable(nau8825->mclk);
2409 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2414 if (nau8825->mclk_freq != freq) {
2415 freq = clk_round_rate(nau8825->mclk, freq);
2416 ret = clk_set_rate(nau8825->mclk, freq);
2418 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2421 nau8825->mclk_freq = freq;
2441 struct regmap *regmap = nau8825->regmap;
2448 if (nau8825->mclk_freq) {
2449 clk_disable_unprepare(nau8825->mclk);
2450 nau8825->mclk_freq = 0;
2456 * interrupt handler. In order to avoid the playback inter-
2474 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2494 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2496 if (nau8825->mclk_freq) {
2497 clk_disable_unprepare(nau8825->mclk);
2498 nau8825->mclk_freq = 0;
2504 * interrupt handler. In order to avoid the playback inter-
2509 /* Higher FLL reference input frequency can only set lower
2510 * gain error, such as 0000 for input reference from MCLK
2526 * interrupt handler. In order to avoid the playback inter-
2531 /* If FLL reference input is from low frequency source,
2544 if (nau8825->mclk_freq) {
2545 clk_disable_unprepare(nau8825->mclk);
2546 nau8825->mclk_freq = 0;
2552 * interrupt handler. In order to avoid the playback inter-
2557 /* If FLL reference input is from low frequency source,
2570 if (nau8825->mclk_freq) {
2571 clk_disable_unprepare(nau8825->mclk);
2572 nau8825->mclk_freq = 0;
2577 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2578 return -EINVAL;
2581 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2596 struct regmap *regmap = nau8825->regmap;
2598 /* Close clock when jack type detection at manual mode */
2605 * bypass de-bounce circuit.
2634 if (nau8825->mclk_freq) {
2635 ret = clk_prepare_enable(nau8825->mclk);
2637 dev_err(nau8825->dev, "Unable to prepare component mclk\n");
2647 /* Reset the configuration of jack type for detection */
2649 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
2652 regmap_update_bits(nau8825->regmap,
2654 /* Cancel and reset cross talk detection funciton */
2659 regmap_write(nau8825->regmap,
2662 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2664 if (nau8825->mclk_freq)
2665 clk_disable_unprepare(nau8825->mclk);
2675 disable_irq(nau8825->irq);
2678 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
2679 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
2680 snd_soc_dapm_sync(nau8825->dapm);
2681 regcache_cache_only(nau8825->regmap, true);
2682 regcache_mark_dirty(nau8825->regmap);
2692 regcache_cache_only(nau8825->regmap, false);
2693 regcache_sync(nau8825->regmap);
2694 nau8825->xtalk_protect = true;
2697 nau8825->xtalk_protect = false;
2698 enable_irq(nau8825->irq);
2739 struct device *dev = nau8825->dev;
2741 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2742 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2743 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2744 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2745 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2746 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2748 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2749 for (i = 0; i < nau8825->sar_threshold_num; i++)
2750 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2751 nau8825->sar_threshold[i]);
2753 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2754 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2755 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2756 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2757 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2758 dev_dbg(dev, "jack-insert-debounce: %d\n",
2759 nau8825->jack_insert_debounce);
2760 dev_dbg(dev, "jack-eject-debounce: %d\n",
2761 nau8825->jack_eject_debounce);
2762 dev_dbg(dev, "crosstalk-enable: %d\n",
2763 nau8825->xtalk_enable);
2764 dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds);
2765 dev_dbg(dev, "adc-delay-ms: %d\n", nau8825->adc_delay);
2772 nau8825->jkdet_enable = device_property_read_bool(dev,
2773 "nuvoton,jkdet-enable");
2774 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2775 "nuvoton,jkdet-pull-enable");
2776 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2777 "nuvoton,jkdet-pull-up");
2778 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2779 &nau8825->jkdet_polarity);
2781 nau8825->jkdet_polarity = 1;
2782 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
2783 &nau8825->micbias_voltage);
2785 nau8825->micbias_voltage = 6;
2786 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
2787 &nau8825->vref_impedance);
2789 nau8825->vref_impedance = 2;
2790 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2791 &nau8825->sar_threshold_num);
2793 nau8825->sar_threshold_num = 4;
2794 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2795 nau8825->sar_threshold, nau8825->sar_threshold_num);
2797 nau8825->sar_threshold[0] = 0x08;
2798 nau8825->sar_threshold[1] = 0x12;
2799 nau8825->sar_threshold[2] = 0x26;
2800 nau8825->sar_threshold[3] = 0x73;
2802 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2803 &nau8825->sar_hysteresis);
2805 nau8825->sar_hysteresis = 0;
2806 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
2807 &nau8825->sar_voltage);
2809 nau8825->sar_voltage = 6;
2810 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
2811 &nau8825->sar_compare_time);
2813 nau8825->sar_compare_time = 1;
2814 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2815 &nau8825->sar_sampling_time);
2817 nau8825->sar_sampling_time = 1;
2818 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
2819 &nau8825->key_debounce);
2821 nau8825->key_debounce = 3;
2822 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2823 &nau8825->jack_insert_debounce);
2825 nau8825->jack_insert_debounce = 7;
2826 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2827 &nau8825->jack_eject_debounce);
2829 nau8825->jack_eject_debounce = 0;
2830 nau8825->xtalk_enable = device_property_read_bool(dev,
2831 "nuvoton,crosstalk-enable");
2832 nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong");
2833 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", &nau8825->adc_delay);
2835 nau8825->adc_delay = 125;
2836 if (nau8825->adc_delay < 125 || nau8825->adc_delay > 500)
2839 nau8825->mclk = devm_clk_get_optional(dev, "mclk");
2840 if (IS_ERR(nau8825->mclk))
2841 return PTR_ERR(nau8825->mclk);
2842 if (!nau8825->mclk)
2853 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2858 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2859 nau8825->irq, ret);
2868 struct device *dev = &i2c->dev;
2869 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2875 return -ENOMEM;
2883 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2884 if (IS_ERR(nau8825->regmap))
2885 return PTR_ERR(nau8825->regmap);
2886 nau8825->dev = dev;
2887 nau8825->irq = i2c->irq;
2891 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2892 nau8825->xtalk_protect = false;
2893 nau8825->xtalk_baktab_initialized = false;
2894 sema_init(&nau8825->xtalk_sem, 1);
2895 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2899 nau8825_reset_chip(nau8825->regmap);
2900 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2906 nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK;
2907 switch (nau8825->sw_id) {
2911 ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch,
2920 return -ENODEV;
2925 if (i2c->irq)
2928 return devm_snd_soc_register_component(&i2c->dev,