Lines Matching +full:mic1 +full:- +full:src
1 // SPDX-License-Identifier: GPL-2.0-only
35 static int quirk_override = -1;
37 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
91 { 64, 2 }, /* OSR 64, SRC 1/4 */
92 { 256, 0 }, /* OSR 256, SRC 1 */
93 { 128, 1 }, /* OSR 128, SRC 1/2 */
95 { 32, 3 }, /* OSR 32, SRC 1/8 */
99 { 32, 3 }, /* OSR 32, SRC 1/8 */
100 { 64, 2 }, /* OSR 64, SRC 1/4 */
101 { 128, 1 }, /* OSR 128, SRC 1/2 */
102 { 256, 0 }, /* OSR 256, SRC 1 */
211 ret = down_timeout(&nau8824->jd_sem, timeout);
213 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
215 ret = down_interruptible(&nau8824->jd_sem);
217 dev_warn(nau8824->dev, "Acquire semaphore fail\n");
225 up(&nau8824->jd_sem);
304 "Off", "NC", "u-law", "A-law" };
359 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
361 static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
388 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
431 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
437 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
441 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
445 return -EINVAL;
454 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
459 regmap_update_bits(nau8824->regmap,
464 regmap_update_bits(nau8824->regmap,
469 return -EINVAL;
478 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
485 regmap_update_bits(nau8824->regmap,
490 regmap_update_bits(nau8824->regmap,
495 return -EINVAL;
504 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
506 struct regmap *regmap = nau8824->regmap;
512 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
525 clk_disable_unprepare(nau8824->mclk);
527 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
529 ret = clk_prepare_enable(nau8824->mclk);
571 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
573 int src;
576 freq = clk_get_rate(nau8824->mclk);
578 freq = nau8824->fs * 256;
584 for (src = 0; src < 5; src++) {
585 if (freq / (0x1 << src) <= DMIC_CLK)
588 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, freq);
589 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
590 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
663 SND_SOC_DAPM_INPUT("MIC1"),
769 {"Left ADC", "MIC Switch", "MIC1"},
827 struct snd_soc_jack *jack = nau8824->jack;
830 if (nau8824->irq && jack)
831 insert = jack->status & SND_JACK_HEADPHONE;
840 /* Reset the intrruption status from rightmost bit if the corres-
854 struct snd_soc_dapm_context *dapm = nau8824->dapm;
855 struct regmap *regmap = nau8824->regmap;
865 * interruption, and then bypass de-bounce circuit.
879 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
887 struct snd_soc_dapm_context *dapm = nau8824->dapm;
888 struct regmap *regmap = nau8824->regmap;
899 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
910 snd_soc_jack_report(nau8824->jack, event, event_mask);
917 if (nau8824->resume_lock) {
919 nau8824->resume_lock = false;
925 struct regmap *regmap = nau8824->regmap;
934 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
969 struct regmap *regmap = nau8824->regmap;
973 dev_err(nau8824->dev, "failed to read irq status\n");
976 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
985 if (nau8824->resume_lock) {
987 nau8824->resume_lock = false;
989 cancel_work_sync(&nau8824->jdet_work);
1000 dev_dbg(nau8824->dev, "button %x pressed\n", event);
1016 cancel_work_sync(&nau8824->jdet_work);
1017 schedule_work(&nau8824->jdet_work);
1031 snd_soc_jack_report(nau8824->jack, event, event_mask);
1042 regmap_read(nau8824->regmap,
1049 regmap_read(nau8824->regmap,
1061 struct snd_soc_component *component = dai->component;
1065 osr = nau8824_get_osr(nau8824, substream->stream);
1066 if (!osr || !osr->osr)
1067 return -EINVAL;
1069 return snd_pcm_hw_constraint_minmax(substream->runtime,
1071 0, CLK_DA_AD_MAX / osr->osr);
1077 struct snd_soc_component *component = dai->component;
1081 int err = -EINVAL;
1091 nau8824->fs = params_rate(params);
1092 osr = nau8824_get_osr(nau8824, substream->stream);
1093 if (!osr || !osr->osr)
1095 if (nau8824->fs * osr->osr > CLK_DA_AD_MAX)
1097 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1098 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1100 osr->clk_src << NAU8824_CLK_DAC_SRC_SFT);
1102 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1104 osr->clk_src << NAU8824_CLK_ADC_SRC_SFT);
1107 regmap_read(nau8824->regmap,
1111 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
1122 regmap_update_bits(nau8824->regmap,
1145 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1157 struct snd_soc_component *component = dai->component;
1168 return -EINVAL;
1178 return -EINVAL;
1199 return -EINVAL;
1204 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1207 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1216 * nau8824_set_tdm_slot - configure DAI TDM.
1234 struct snd_soc_component *component = dai->component;
1242 return -EINVAL;
1256 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
1260 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
1267 * nau8824_calc_fll_param - Calculate FLL parameters.
1283 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1292 return -EINVAL;
1293 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1301 return -EINVAL;
1302 fll_param->ratio = fll_ratio[i].val;
1305 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1320 return -EINVAL;
1321 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1323 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1326 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1327 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1328 fll_param->fll_frac = fvco & 0xFFFF;
1337 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
1339 NAU8824_FLL_RATIO_MASK, fll_param->ratio);
1340 /* FLL 16-bit fractional input */
1341 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
1342 /* FLL 10-bit integer input */
1344 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
1345 /* FLL pre-scaler */
1348 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
1352 /* Disable free-running mode */
1355 if (fll_param->fll_frac) {
1383 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
1386 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1390 nau8824_fll_apply(nau8824->regmap, &fll_param);
1392 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1401 struct regmap *regmap = nau8824->regmap;
1449 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
1450 return -EINVAL;
1453 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1470 if (nau8824->irq) {
1472 nau8824_int_status_clear_all(nau8824->regmap);
1476 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1478 regmap_update_bits(nau8824->regmap,
1482 regmap_update_bits(nau8824->regmap,
1508 regmap_update_bits(nau8824->regmap,
1510 regmap_update_bits(nau8824->regmap,
1524 nau8824->dapm = dapm;
1533 if (nau8824->irq) {
1534 disable_irq(nau8824->irq);
1537 regcache_cache_only(nau8824->regmap, true);
1538 regcache_mark_dirty(nau8824->regmap);
1548 regcache_cache_only(nau8824->regmap, false);
1549 regcache_sync(nau8824->regmap);
1550 if (nau8824->irq) {
1554 nau8824->resume_lock = true;
1557 nau8824->resume_lock = false;
1558 enable_irq(nau8824->irq);
1628 * nau8824_enable_jack_detect - Specify a jack for event reporting
1643 nau8824->jack = jack;
1645 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
1646 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
1650 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
1651 nau8824->irq, ret);
1666 struct regmap *regmap = nau8824->regmap;
1670 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
1673 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
1676 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
1680 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
1683 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
1686 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
1689 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
1691 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
1693 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
1695 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
1700 struct regmap *regmap = nau8824->regmap;
1705 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
1710 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
1789 /* jkdet_polarity - 1 is for active-low */
1790 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
1793 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
1794 if (nau8824->sar_threshold_num)
1801 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1803 regmap_update_bits(nau8824->regmap,
1805 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
1813 struct device *dev = nau8824->dev;
1816 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
1817 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
1818 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
1820 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
1821 for (i = 0; i < nau8824->sar_threshold_num; i++)
1822 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
1823 nau8824->sar_threshold[i]);
1825 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
1826 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
1827 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
1828 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
1829 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
1830 dev_dbg(dev, "jack-eject-debounce: %d\n",
1831 nau8824->jack_eject_debounce);
1838 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1839 &nau8824->jkdet_polarity);
1841 nau8824->jkdet_polarity = 1;
1842 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1843 &nau8824->micbias_voltage);
1845 nau8824->micbias_voltage = 6;
1846 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1847 &nau8824->vref_impedance);
1849 nau8824->vref_impedance = 2;
1850 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1851 &nau8824->sar_threshold_num);
1853 nau8824->sar_threshold_num = 4;
1854 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1855 nau8824->sar_threshold, nau8824->sar_threshold_num);
1857 nau8824->sar_threshold[0] = 0x0a;
1858 nau8824->sar_threshold[1] = 0x14;
1859 nau8824->sar_threshold[2] = 0x26;
1860 nau8824->sar_threshold[3] = 0x73;
1862 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1863 &nau8824->sar_hysteresis);
1865 nau8824->sar_hysteresis = 0;
1866 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
1867 &nau8824->sar_voltage);
1869 nau8824->sar_voltage = 6;
1870 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
1871 &nau8824->sar_compare_time);
1873 nau8824->sar_compare_time = 1;
1874 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1875 &nau8824->sar_sampling_time);
1877 nau8824->sar_sampling_time = 1;
1878 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
1879 &nau8824->key_debounce);
1881 nau8824->key_debounce = 0;
1882 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1883 &nau8824->jack_eject_debounce);
1885 nau8824->jack_eject_debounce = 1;
1887 nau8824->mclk = devm_clk_get_optional(dev, "mclk");
1888 if (IS_ERR(nau8824->mclk))
1889 return PTR_ERR(nau8824->mclk);
1910 DMI_MATCH(DMI_PRODUCT_NAME, "i1-TF"),
1954 if (quirk_override != -1) {
1961 nau8824_quirk = (unsigned long)dmi_id->driver_data;
1969 return "cfg-spk:1";
1971 return "cfg-spk:2";
1977 struct device *dev = &i2c->dev;
1984 return -ENOMEM;
1991 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
1992 if (IS_ERR(nau8824->regmap))
1993 return PTR_ERR(nau8824->regmap);
1994 nau8824->resume_lock = false;
1995 nau8824->dev = dev;
1996 nau8824->irq = i2c->irq;
1997 sema_init(&nau8824->jd_sem, 1);
2002 nau8824->jkdet_polarity = 0;
2006 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
2012 nau8824_reset_chip(nau8824->regmap);
2015 if (i2c->irq)