1 // SPDX-License-Identifier: GPL-2.0
3 // nau8822.c  --  NAU8822 ALSA Soc Audio driver
8 // Co-author: John Hsu <kchsu0@nuvoton.com>
9 // Co-author: Seven Li <wtli@nuvoton.com>
185 	struct soc_bytes_ext *params = (void *)kcontrol->private_value;  in nau8822_eq_get()
190 	val = (u16 *)ucontrol->value.bytes.data;  in nau8822_eq_get()
192 	for (i = 0; i < params->max / sizeof(u16); i++) {  in nau8822_eq_get()
194 		/* conversion of 16-bit integers between native CPU format  in nau8822_eq_get()
206  * cut-off frequency, bandwidth control, and equalizer path.
217 	struct soc_bytes_ext *params = (void *)kcontrol->private_value;  in nau8822_eq_put()
223 	data = kmemdup(ucontrol->value.bytes.data,  in nau8822_eq_put()
224 		params->max, GFP_KERNEL | GFP_DMA);  in nau8822_eq_put()
226 		return -ENOMEM;  in nau8822_eq_put()
230 	for (i = 0; i < params->max / sizeof(u16); i++) {  in nau8822_eq_put()
231 		/* conversion of 16-bit integers between native CPU format  in nau8822_eq_put()
238 			dev_err(component->dev,  in nau8822_eq_put()
251 	"Off", "NC", "u-law", "A-law"};
278 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
279 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
280 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
282 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
449 		snd_soc_dapm_to_component(source->dapm);  in check_mclk_select_pll()
510 	SND_SOC_DAPM_SUPPLY("PLL",
533 	{"Right DAC", NULL, "PLL", check_mclk_select_pll},
534 	{"Left DAC", NULL, "PLL", check_mclk_select_pll},
578 	{"Right ADC", NULL, "PLL", check_mclk_select_pll},
579 	{"Left ADC", NULL, "PLL", check_mclk_select_pll},
623 		return -EINVAL;  in nau8822_calc_pll()
637 		return -EINVAL;  in nau8822_calc_pll()
638 	pll_param->mclk_scaler = scal_sel;  in nau8822_calc_pll()
641 	/* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional  in nau8822_calc_pll()
645 	pll_param->pre_factor = 0;  in nau8822_calc_pll()
648 		pll_param->pre_factor = 1;  in nau8822_calc_pll()
650 	pll_param->pll_int = (pll_ratio >> 28) & 0xF;  in nau8822_calc_pll()
651 	pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);  in nau8822_calc_pll()
658 	struct snd_soc_component *component = dai->component;  in nau8822_config_clkdiv()
660 	struct nau8822_pll *pll = &nau8822->pll;  in nau8822_config_clkdiv()  local
663 	switch (nau8822->div_id) {  in nau8822_config_clkdiv()
665 		/* Configure the master clock prescaler div to make system  in nau8822_config_clkdiv()
666 		 * clock to approximate the internal master clock (IMCLK);  in nau8822_config_clkdiv()
672 			sclk = (nau8822->sysclk * 10) /	nau8822_mclk_scaler[i];  in nau8822_config_clkdiv()
677 		dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",  in nau8822_config_clkdiv()
680 		/* master clock from MCLK and disable PLL */  in nau8822_config_clkdiv()
690 		/* master clock from PLL and enable PLL */  in nau8822_config_clkdiv()
691 		if (pll->mclk_scaler != div) {  in nau8822_config_clkdiv()
692 			dev_err(component->dev,  in nau8822_config_clkdiv()
693 			"master clock prescaler not meet PLL parameters\n");  in nau8822_config_clkdiv()
694 			return -EINVAL;  in nau8822_config_clkdiv()
705 		return -EINVAL;  in nau8822_config_clkdiv()
714 	struct snd_soc_component *component = dai->component;  in nau8822_set_pll()
716 	struct nau8822_pll *pll_param = &nau8822->pll;  in nau8822_set_pll()
719 	if (freq_in == pll_param->freq_in &&  in nau8822_set_pll()
720 	    freq_out == pll_param->freq_out)  in nau8822_set_pll()
724 		dev_dbg(component->dev, "PLL disabled\n");  in nau8822_set_pll()
734 		dev_err(component->dev, "Unsupported input clock %d\n",  in nau8822_set_pll()
739 	dev_dbg(component->dev,  in nau8822_set_pll()
741 		pll_param->pll_int, pll_param->pll_frac,  in nau8822_set_pll()
742 		pll_param->mclk_scaler, pll_param->pre_factor);  in nau8822_set_pll()
748 		(pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |  in nau8822_set_pll()
749 		pll_param->pll_int);  in nau8822_set_pll()
751 		NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &  in nau8822_set_pll()
754 		NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &  in nau8822_set_pll()
757 		NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);  in nau8822_set_pll()
760 		pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);  in nau8822_set_pll()
766 	pll_param->freq_in = freq_in;  in nau8822_set_pll()
767 	pll_param->freq_out = freq_out;  in nau8822_set_pll()
775 	struct snd_soc_component *component = dai->component;  in nau8822_set_dai_sysclk()
779 	nau8822->div_id = clk_id;  in nau8822_set_dai_sysclk()
780 	nau8822->sysclk = freq;  in nau8822_set_dai_sysclk()
782 	if (nau8822->mclk) {  in nau8822_set_dai_sysclk()
783 		mclk_freq = clk_get_rate(nau8822->mclk);  in nau8822_set_dai_sysclk()
788 				dev_err(component->dev, "Failed to set PLL\n");  in nau8822_set_dai_sysclk()
791 			nau8822->div_id = NAU8822_CLK_PLL;  in nau8822_set_dai_sysclk()
795 	dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,  in nau8822_set_dai_sysclk()
796 		nau8822->div_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");  in nau8822_set_dai_sysclk()
803 	struct snd_soc_component *component = dai->component;  in nau8822_set_dai_fmt()
806 	dev_dbg(component->dev, "%s\n", __func__);  in nau8822_set_dai_fmt()
816 		return -EINVAL;  in nau8822_set_dai_fmt()
832 		return -EINVAL;  in nau8822_set_dai_fmt()
848 		return -EINVAL;  in nau8822_set_dai_fmt()
865 	struct snd_soc_component *component = dai->component;  in nau8822_hw_params()
870 	/* make BCLK and LRC divide configuration if the codec as master. */  in nau8822_hw_params()
882 			return -EINVAL;  in nau8822_hw_params()
900 		return -EINVAL;  in nau8822_hw_params()
923 		return -EINVAL;  in nau8822_hw_params()
931 	/* If the master clock is from MCLK, provide the runtime FS for driver  in nau8822_hw_params()
932 	 * to get the master clock prescaler configuration.  in nau8822_hw_params()
934 	if (nau8822->div_id != NAU8822_CLK_MCLK)  in nau8822_hw_params()
935 		div = nau8822->pll.mclk_scaler;  in nau8822_hw_params()
944 	struct snd_soc_component *component = dai->component;  in nau8822_mute()
946 	dev_dbg(component->dev, "%s: %d\n", __func__, mute);  in nau8822_mute()
968 		if (nau8822->mclk &&  in nau8822_set_bias_level()
970 			int ret = clk_prepare_enable(nau8822->mclk);  in nau8822_set_bias_level()
973 				dev_err(component->dev,  in nau8822_set_bias_level()
985 		if (nau8822->mclk &&  in nau8822_set_bias_level()
987 			clk_disable_unprepare(nau8822->mclk);  in nau8822_set_bias_level()
1016 	dev_dbg(component->dev, "%s: %d\n", __func__, level);  in nau8822_set_bias_level()
1036 	.name = "nau8822-hifi",
1061 	regcache_mark_dirty(nau8822->regmap);  in nau8822_suspend()
1070 	regcache_sync(nau8822->regmap);  in nau8822_resume()
1078  * These registers contain an "update" bit - bit 8. This means, for example,
1080  * the update bit is set, will also the volume be updated - simultaneously for
1099 	struct device_node *of_node = component->dev->of_node;  in nau8822_probe()
1113 	if (of_property_read_bool(of_node, "nuvoton,spk-btl"))  in nau8822_probe()
1154 	struct device *dev = &i2c->dev;  in nau8822_i2c_probe()
1161 			return -ENOMEM;  in nau8822_i2c_probe()
1165 	nau8822->mclk = devm_clk_get_optional(&i2c->dev, "mclk");  in nau8822_i2c_probe()
1166 	if (IS_ERR(nau8822->mclk))  in nau8822_i2c_probe()
1167 		return dev_err_probe(&i2c->dev, PTR_ERR(nau8822->mclk),  in nau8822_i2c_probe()
1170 	nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);  in nau8822_i2c_probe()
1171 	if (IS_ERR(nau8822->regmap)) {  in nau8822_i2c_probe()
1172 		ret = PTR_ERR(nau8822->regmap);  in nau8822_i2c_probe()
1173 		dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);  in nau8822_i2c_probe()
1176 	nau8822->dev = dev;  in nau8822_i2c_probe()
1179 	ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);  in nau8822_i2c_probe()
1181 		dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);  in nau8822_i2c_probe()
1188 		dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);  in nau8822_i2c_probe()