Lines Matching +full:pga +full:- +full:gain
1 // SPDX-License-Identifier: GPL-2.0
3 // nau8822.c -- NAU8822 ALSA Soc Audio driver
8 // Co-author: John Hsu <kchsu0@nuvoton.com>
9 // Co-author: Seven Li <wtli@nuvoton.com>
185 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
190 val = (u16 *)ucontrol->value.bytes.data;
192 for (i = 0; i < params->max / sizeof(u16); i++) {
194 /* conversion of 16-bit integers between native CPU format
205 * control. These configuration includes central frequency, equalizer gain,
206 * cut-off frequency, bandwidth control, and equalizer path.
217 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
223 data = kmemdup(ucontrol->value.bytes.data,
224 params->max, GFP_KERNEL | GFP_DMA);
226 return -ENOMEM;
230 for (i = 0; i < params->max / sizeof(u16); i++) {
231 /* conversion of 16-bit integers between native CPU format
238 dev_err(component->dev,
251 "Off", "NC", "u-law", "A-law"};
278 static const DECLARE_TLV_DB_SCALE(digital_tlv, -12750, 50, 1);
279 static const DECLARE_TLV_DB_SCALE(inpga_tlv, -1200, 75, 0);
280 static const DECLARE_TLV_DB_SCALE(spk_tlv, -5700, 100, 0);
282 static const DECLARE_TLV_DB_SCALE(boost_tlv, -1500, 300, 1);
323 SOC_SINGLE("ALC Min Gain",
325 SOC_SINGLE("ALC Max Gain",
340 SOC_DOUBLE_R("PGA ZC Switch",
344 SOC_DOUBLE_R_TLV("PGA Volume",
372 SOC_DOUBLE_R_TLV("PGA Boost Volume",
428 /* Input PGA */
449 snd_soc_dapm_to_component(source->dapm);
488 SND_SOC_DAPM_PGA("Left Capture PGA",
490 SND_SOC_DAPM_PGA("Right Capture PGA",
584 {"Right Boost Mixer", NULL, "Right Capture PGA"},
590 {"Left Boost Mixer", NULL, "Left Capture PGA"},
593 /* Input PGA */
594 {"Right Capture PGA", NULL, "Right Input Mixer"},
595 {"Left Capture PGA", NULL, "Left Input Mixer"},
598 {"Right Capture PGA", NULL, "Mic Bias"},
599 {"Left Capture PGA", NULL, "Mic Bias"},
623 return -EINVAL;
637 return -EINVAL;
638 pll_param->mclk_scaler = scal_sel;
641 /* Calculate the PLL 4-bit integer input and the PLL 24-bit fractional
645 pll_param->pre_factor = 0;
648 pll_param->pre_factor = 1;
650 pll_param->pll_int = (pll_ratio >> 28) & 0xF;
651 pll_param->pll_frac = ((pll_ratio & 0xFFFFFFF) >> 4);
658 struct snd_soc_component *component = dai->component;
660 struct nau8822_pll *pll = &nau8822->pll;
663 switch (nau8822->div_id) {
672 sclk = (nau8822->sysclk * 10) / nau8822_mclk_scaler[i];
677 dev_dbg(component->dev, "master clock prescaler %x for fs %d\n",
691 if (pll->mclk_scaler != div) {
692 dev_err(component->dev,
694 return -EINVAL;
705 return -EINVAL;
714 struct snd_soc_component *component = dai->component;
716 struct nau8822_pll *pll_param = &nau8822->pll;
719 if (freq_in == pll_param->freq_in &&
720 freq_out == pll_param->freq_out)
724 dev_dbg(component->dev, "PLL disabled\n");
734 dev_err(component->dev, "Unsupported input clock %d\n",
739 dev_dbg(component->dev,
741 pll_param->pll_int, pll_param->pll_frac,
742 pll_param->mclk_scaler, pll_param->pre_factor);
748 (pll_param->pre_factor ? NAU8822_PLLMCLK_DIV2 : 0) |
749 pll_param->pll_int);
751 NAU8822_REG_PLL_K1, (pll_param->pll_frac >> NAU8822_PLLK1_SFT) &
754 NAU8822_REG_PLL_K2, (pll_param->pll_frac >> NAU8822_PLLK2_SFT) &
757 NAU8822_REG_PLL_K3, pll_param->pll_frac & NAU8822_PLLK3_MASK);
760 pll_param->mclk_scaler << NAU8822_MCLKSEL_SFT);
766 pll_param->freq_in = freq_in;
767 pll_param->freq_out = freq_out;
775 struct snd_soc_component *component = dai->component;
779 nau8822->div_id = clk_id;
780 nau8822->sysclk = freq;
782 if (nau8822->mclk) {
783 mclk_freq = clk_get_rate(nau8822->mclk);
788 dev_err(component->dev, "Failed to set PLL\n");
791 nau8822->div_id = NAU8822_CLK_PLL;
795 dev_dbg(component->dev, "master sysclk %dHz, source %s\n", freq,
796 nau8822->div_id == NAU8822_CLK_PLL ? "PLL" : "MCLK");
803 struct snd_soc_component *component = dai->component;
806 dev_dbg(component->dev, "%s\n", __func__);
816 return -EINVAL;
832 return -EINVAL;
848 return -EINVAL;
865 struct snd_soc_component *component = dai->component;
882 return -EINVAL;
900 return -EINVAL;
923 return -EINVAL;
934 if (nau8822->div_id != NAU8822_CLK_MCLK)
935 div = nau8822->pll.mclk_scaler;
944 struct snd_soc_component *component = dai->component;
946 dev_dbg(component->dev, "%s: %d\n", __func__, mute);
968 if (nau8822->mclk &&
970 int ret = clk_prepare_enable(nau8822->mclk);
973 dev_err(component->dev,
985 if (nau8822->mclk &&
987 clk_disable_unprepare(nau8822->mclk);
1016 dev_dbg(component->dev, "%s: %d\n", __func__, level);
1036 .name = "nau8822-hifi",
1061 regcache_mark_dirty(nau8822->regmap);
1070 regcache_sync(nau8822->regmap);
1078 * These registers contain an "update" bit - bit 8. This means, for example,
1080 * the update bit is set, will also the volume be updated - simultaneously for
1099 struct device_node *of_node = component->dev->of_node;
1113 if (of_property_read_bool(of_node, "nuvoton,spk-btl"))
1154 struct device *dev = &i2c->dev;
1161 return -ENOMEM;
1165 nau8822->mclk = devm_clk_get_optional(&i2c->dev, "mclk");
1166 if (IS_ERR(nau8822->mclk))
1167 return dev_err_probe(&i2c->dev, PTR_ERR(nau8822->mclk),
1170 nau8822->regmap = devm_regmap_init_i2c(i2c, &nau8822_regmap_config);
1171 if (IS_ERR(nau8822->regmap)) {
1172 ret = PTR_ERR(nau8822->regmap);
1173 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
1176 nau8822->dev = dev;
1179 ret = regmap_write(nau8822->regmap, NAU8822_REG_RESET, 0x00);
1181 dev_err(&i2c->dev, "Failed to issue reset: %d\n", ret);
1188 dev_err(&i2c->dev, "Failed to register CODEC: %d\n", ret);