Lines Matching +full:dmic +full:- +full:sample +full:- +full:rate
1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8821.c -- Nuvoton NAU88L21 audio codec driver
7 // Co-author: Seven Lee <wtli@nuvoton.com>
33 static int quirk_override = -1;
35 MODULE_PARM_DESC(quirk, "Board-specific quirk override");
98 /* over sampling rate */
286 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
288 if (!component->regmap)
289 return -EINVAL;
291 return regmap_raw_read(component->regmap, NAU8821_R21_BIQ0_COF1,
292 ucontrol->value.bytes.data, params->max);
299 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
303 if (!component->regmap)
304 return -EINVAL;
306 data = kmemdup(ucontrol->value.bytes.data,
307 params->max, GFP_KERNEL | GFP_DMA);
309 return -ENOMEM;
311 ret = regmap_raw_write(component->regmap, NAU8821_R21_BIQ0_COF1,
312 data, params->max);
411 static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -6600, 2400);
412 static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
413 static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -900, 0);
414 static const DECLARE_TLV_DB_SCALE(playback_vol_tlv, -6600, 50, 1);
415 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
416 static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -7000, 2400);
417 static const DECLARE_TLV_DB_MINMAX(drc_knee4_tlv, -9800, -3500);
418 static const DECLARE_TLV_DB_MINMAX(drc_knee3_tlv, -8100, -1800);
454 SOC_ENUM("ADC Decimation Rate", nau8821_adc_decimation_enum),
455 SOC_ENUM("DAC Oversampling Rate", nau8821_dac_oversampl_enum),
470 snd_soc_dapm_to_component(w->dapm);
472 int i, speed_selection = -1, clk_adc_src, clk_adc;
475 /* The DMIC clock is gotten from adc clock divided by
477 * less than nau8821->dmic_clk_threshold.
479 regmap_read(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
483 clk_adc = (nau8821->fs * 256) >> clk_adc_src;
487 nau8821->dmic_clk_threshold) {
492 return -EINVAL;
494 dev_dbg(nau8821->dev,
496 clk_adc, nau8821->dmic_clk_threshold,
498 regmap_update_bits(nau8821->regmap, NAU8821_R13_DMIC_CTRL,
509 snd_soc_dapm_to_component(w->dapm);
514 msleep(nau8821->adc_delay);
519 return -EINVAL;
529 snd_soc_dapm_to_component(w->dapm);
534 msleep(nau8821->adc_delay);
539 return -EINVAL;
549 snd_soc_dapm_to_component(w->dapm);
557 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
561 regmap_update_bits(nau8821->regmap, NAU8821_R80_CHARGE_PUMP,
565 return -EINVAL;
575 snd_soc_dapm_to_component(w->dapm);
581 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
585 regmap_update_bits(nau8821->regmap, NAU8821_R66_BIAS_ADJ,
589 return -EINVAL;
599 snd_soc_dapm_to_component(w->dapm);
603 dev_dbg(nau8821->dev, "system clock control : POWER OFF\n");
609 if (nau8821_is_jack_inserted(nau8821->regmap)) {
622 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
625 if (!nau8821->left_input_single_end)
630 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA,
633 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST,
637 regmap_update_bits(nau8821->regmap, NAU8821_R77_FEPGA,
639 regmap_update_bits(nau8821->regmap, NAU8821_R76_BOOST,
654 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
660 /* single-ended design only on the left */
672 SND_SOC_DAPM_SWITCH("DMIC Enable", SND_SOC_NOPM,
724 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
740 SND_SOC_DAPM_INPUT("DMIC"),
746 {"DMIC Enable", "Switch", "DMIC"},
747 {"DMIC Enable", NULL, "DMIC Clock"},
759 {"ADCL Digital path", NULL, "DMIC Enable"},
760 {"ADCR Digital path", NULL, "DMIC Enable"},
807 regmap_read(nau8821->regmap, NAU8821_R2C_DAC_CTRL1, &osr);
813 regmap_read(nau8821->regmap, NAU8821_R2B_ADC_RATE, &osr);
824 struct snd_soc_component *component = dai->component;
828 osr = nau8821_get_osr(nau8821, substream->stream);
829 if (!osr || !osr->osr)
830 return -EINVAL;
832 return snd_pcm_hw_constraint_minmax(substream->runtime,
834 0, CLK_DA_AD_MAX / osr->osr);
840 struct snd_soc_component *component = dai->component;
845 nau8821->fs = params_rate(params);
847 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
848 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
852 osr = nau8821_get_osr(nau8821, substream->stream);
853 if (!osr || !osr->osr)
854 return -EINVAL;
855 if (nau8821->fs * osr->osr > CLK_DA_AD_MAX)
856 return -EINVAL;
857 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
858 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
860 osr->clk_src << NAU8821_CLK_DAC_SRC_SFT);
862 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
864 osr->clk_src << NAU8821_CLK_ADC_SRC_SFT);
867 regmap_read(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2, &ctrl_val);
870 bclk_fs = snd_soc_params_to_bclk(params) / nau8821->fs;
878 return -EINVAL;
880 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
899 return -EINVAL;
902 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
910 struct snd_soc_component *component = codec_dai->component;
921 return -EINVAL;
931 return -EINVAL;
952 return -EINVAL;
955 regmap_update_bits(nau8821->regmap, NAU8821_R1C_I2S_PCM_CTRL1,
958 regmap_update_bits(nau8821->regmap, NAU8821_R1D_I2S_PCM_CTRL2,
967 struct snd_soc_component *component = dai->component;
974 return regmap_update_bits(nau8821->regmap,
1048 struct snd_soc_dapm_context *dapm = nau8821->dapm;
1049 struct regmap *regmap = nau8821->regmap;
1077 /* Bypass de-bounce circuit */
1088 if (nau8821->key_enable) {
1107 struct snd_soc_dapm_context *dapm = nau8821->dapm;
1108 struct regmap *regmap = nau8821->regmap;
1114 dev_dbg(nau8821->dev, "Headset connected\n");
1125 if (nau8821->key_enable) {
1138 dev_dbg(nau8821->dev, "Headphone connected\n");
1145 snd_soc_jack_report(nau8821->jack, event, event_mask);
1151 struct regmap *regmap = nau8821->regmap;
1163 if (snd_soc_dapm_get_bias_level(nau8821->dapm) < SND_SOC_BIAS_PREPARE)
1176 /* Do not bypass de-bounce circuit */
1191 struct regmap *regmap = nau8821->regmap;
1195 dev_err(nau8821->dev, "failed to read irq status\n");
1199 dev_dbg(nau8821->dev, "IRQ %d\n", active_irq);
1203 cancel_delayed_work_sync(&nau8821->jdet_work);
1217 cancel_delayed_work_sync(&nau8821->jdet_work);
1222 snd_soc_dapm_force_enable_pin(nau8821->dapm, "MICBIAS");
1223 snd_soc_dapm_sync(nau8821->dapm);
1224 schedule_delayed_work(&nau8821->jdet_work, msecs_to_jiffies(20));
1228 dev_warn(nau8821->dev,
1238 snd_soc_jack_report(nau8821->jack, event, event_mask);
1262 nau8821->dapm = dapm;
1268 * nau8821_calc_fll_param - Calculate FLL parameters.
1270 * @fs: sampling rate.
1284 * dividing freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1293 return -EINVAL;
1294 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1302 return -EINVAL;
1303 fll_param->ratio = fll_ratio[i].val;
1306 * FDCO must be within the 90MHz - 100MHz or the FFL cannot be
1321 return -EINVAL;
1322 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1324 /* Calculate the FLL 10-bit integer input and the FLL 24-bit fractional
1327 fvco = div_u64(fvco_max << 24, fref * fll_param->ratio);
1328 fll_param->fll_int = (fvco >> 24) & 0x3ff;
1329 fll_param->fll_frac = fvco & 0xffffff;
1337 struct regmap *regmap = nau8821->regmap;
1341 NAU8821_CLK_SRC_MCLK | fll_param->mclk_src);
1345 fll_param->ratio | (0x6 << NAU8821_ICTRL_LATCH_SFT));
1346 /* FLL 24-bit fractional input */
1348 (fll_param->fll_frac >> 16) & 0xff);
1349 regmap_write(regmap, NAU8821_R0B_FLL8, fll_param->fll_frac & 0xffff);
1350 /* FLL 10-bit integer input */
1352 NAU8821_FLL_INTEGER_MASK, fll_param->fll_int);
1353 /* FLL pre-scaler */
1357 (fll_param->clk_ref_div << NAU8821_FLL_REF_DIV_SFT));
1361 /* Disable free-running mode */
1364 if (fll_param->fll_frac) {
1385 * nau8821_set_fll - FLL configuration of nau8821
1407 dev_err(nau8821->dev,
1412 dev_dbg(nau8821->dev,
1414 fll_param->mclk_src, fll_param->ratio, fll_param->fll_frac,
1415 fll_param->fll_int, fll_param->clk_ref_div);
1419 regmap_update_bits(nau8821->regmap, NAU8821_R03_CLK_DIVIDER,
1439 struct regmap *regmap = nau8821->regmap;
1504 dev_err(nau8821->dev, "Invalid clock id (%d)\n", clk_id);
1505 return -EINVAL;
1507 nau8821->clk_id = clk_id;
1508 dev_dbg(nau8821->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1509 nau8821->clk_id);
1524 struct regmap *regmap = nau8821->regmap;
1528 if (nau8821->irq) {
1533 * bypass de-bounce circuit.
1551 struct regmap *regmap = nau8821->regmap;
1562 if (snd_soc_dapm_get_bias_level(nau8821->dapm) == SND_SOC_BIAS_OFF)
1570 if (nau8821->irq) {
1598 if (nau8821->irq)
1599 disable_irq(nau8821->irq);
1600 snd_soc_dapm_force_bias_level(nau8821->dapm, SND_SOC_BIAS_OFF);
1602 snd_soc_dapm_disable_pin(nau8821->dapm, "MICBIAS");
1603 snd_soc_dapm_sync(nau8821->dapm);
1604 regcache_cache_only(nau8821->regmap, true);
1605 regcache_mark_dirty(nau8821->regmap);
1614 regcache_cache_only(nau8821->regmap, false);
1615 regcache_sync(nau8821->regmap);
1616 if (nau8821->irq)
1617 enable_irq(nau8821->irq);
1642 * nau8821_enable_jack_detect - Specify a jack for event reporting
1657 nau8821->jack = jack;
1659 INIT_DELAYED_WORK(&nau8821->jdet_work, nau8821_jdet_work);
1661 ret = devm_request_threaded_irq(nau8821->dev, nau8821->irq, NULL,
1665 dev_err(nau8821->dev, "Cannot request irq %d (%d)\n",
1666 nau8821->irq, ret);
1682 struct device *dev = nau8821->dev;
1684 dev_dbg(dev, "jkdet-enable: %d\n", nau8821->jkdet_enable);
1685 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8821->jkdet_pull_enable);
1686 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8821->jkdet_pull_up);
1687 dev_dbg(dev, "jkdet-polarity: %d\n", nau8821->jkdet_polarity);
1688 dev_dbg(dev, "micbias-voltage: %d\n", nau8821->micbias_voltage);
1689 dev_dbg(dev, "vref-impedance: %d\n", nau8821->vref_impedance);
1690 dev_dbg(dev, "jack-insert-debounce: %d\n",
1691 nau8821->jack_insert_debounce);
1692 dev_dbg(dev, "jack-eject-debounce: %d\n",
1693 nau8821->jack_eject_debounce);
1694 dev_dbg(dev, "dmic-clk-threshold: %d\n",
1695 nau8821->dmic_clk_threshold);
1696 dev_dbg(dev, "key_enable: %d\n", nau8821->key_enable);
1697 dev_dbg(dev, "adc-delay-ms: %d\n", nau8821->adc_delay);
1705 nau8821->jkdet_enable = device_property_read_bool(dev,
1706 "nuvoton,jkdet-enable");
1707 nau8821->jkdet_pull_enable = device_property_read_bool(dev,
1708 "nuvoton,jkdet-pull-enable");
1709 nau8821->jkdet_pull_up = device_property_read_bool(dev,
1710 "nuvoton,jkdet-pull-up");
1711 nau8821->key_enable = device_property_read_bool(dev,
1712 "nuvoton,key-enable");
1713 nau8821->left_input_single_end = device_property_read_bool(dev,
1714 "nuvoton,left-input-single-end");
1715 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1716 &nau8821->jkdet_polarity);
1718 nau8821->jkdet_polarity = 1;
1719 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1720 &nau8821->micbias_voltage);
1722 nau8821->micbias_voltage = 6;
1723 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1724 &nau8821->vref_impedance);
1726 nau8821->vref_impedance = 2;
1727 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
1728 &nau8821->jack_insert_debounce);
1730 nau8821->jack_insert_debounce = 7;
1731 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1732 &nau8821->jack_eject_debounce);
1734 nau8821->jack_eject_debounce = 0;
1735 ret = device_property_read_u32(dev, "nuvoton,dmic-clk-threshold",
1736 &nau8821->dmic_clk_threshold);
1738 nau8821->dmic_clk_threshold = 3072000;
1739 ret = device_property_read_u32(dev, "nuvoton,dmic-slew-rate",
1740 &nau8821->dmic_slew_rate);
1742 nau8821->dmic_slew_rate = 0;
1743 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms",
1744 &nau8821->adc_delay);
1746 nau8821->adc_delay = 125;
1747 if (nau8821->adc_delay < 125 || nau8821->adc_delay > 500)
1755 struct regmap *regmap = nau8821->regmap;
1769 (nau8821->vref_impedance << NAU8821_BIAS_VMID_SEL_SFT) |
1800 NAU8821_MICBIAS_VOLTAGE_MASK, nau8821->micbias_voltage);
1809 NAU8821_DMIC_SLEW_MASK, nau8821->dmic_slew_rate <<
1811 if (nau8821->left_input_single_end) {
1821 struct regmap *regmap = nau8821->regmap;
1826 nau8821->jkdet_enable ? 0 : NAU8821_JKDET_OUTPUT_EN);
1829 nau8821->jkdet_pull_enable ? 0 : NAU8821_JKDET_PULL_EN);
1832 nau8821->jkdet_pull_up ? NAU8821_JKDET_PULL_UP : 0);
1835 /* jkdet_polarity - 1 is for active-low */
1836 nau8821->jkdet_polarity ? 0 : NAU8821_JACK_POLARITY);
1839 nau8821->jack_insert_debounce <<
1843 nau8821->jack_eject_debounce <<
1851 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1860 /* Positivo CW14Q01P-V2 */
1863 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P-V2"),
1890 if (quirk_override != -1) {
1897 nau8821_quirk = (unsigned long)dmi_id->driver_data;
1902 struct device *dev = &i2c->dev;
1903 struct nau8821 *nau8821 = dev_get_platdata(&i2c->dev);
1909 return -ENOMEM;
1914 nau8821->regmap = devm_regmap_init_i2c(i2c, &nau8821_regmap_config);
1915 if (IS_ERR(nau8821->regmap))
1916 return PTR_ERR(nau8821->regmap);
1918 nau8821->dev = dev;
1919 nau8821->irq = i2c->irq;
1924 nau8821->jkdet_polarity = 0;
1931 nau8821_reset_chip(nau8821->regmap);
1932 ret = regmap_read(nau8821->regmap, NAU8821_R58_I2C_DEVICE_ID, &value);
1939 if (i2c->irq)
1942 ret = devm_snd_soc_register_component(&i2c->dev,