1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
182 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
183 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
206 	"ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
235 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in nau8540_fepga_event()
240 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,  in nau8540_fepga_event()
256 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in nau8540_precharge_event()
261 		regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,  in nau8540_precharge_event()
264 		regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,  in nau8540_precharge_event()
266 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,  in nau8540_precharge_event()
278 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in adc_power_control()
284 		regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,  in adc_power_control()
286 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in adc_power_control()
288 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in adc_power_control()
291 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in adc_power_control()
293 		regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in adc_power_control()
295 		regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,  in adc_power_control()
304 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);  in aiftx_power_control()
308 		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);  in aiftx_power_control()
309 		regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);  in aiftx_power_control()
335 	SND_SOC_DAPM_PGA_S("ADC CH1", 2, NAU8540_REG_ANALOG_PWR, 0, 0,
337 	SND_SOC_DAPM_PGA_S("ADC CH2", 2, NAU8540_REG_ANALOG_PWR, 1, 0,
339 	SND_SOC_DAPM_PGA_S("ADC CH3", 2, NAU8540_REG_ANALOG_PWR, 2, 0,
341 	SND_SOC_DAPM_PGA_S("ADC CH4", 2, NAU8540_REG_ANALOG_PWR, 3, 0,
368 	{"ADC CH1", NULL, "Precharge"},
369 	{"ADC CH2", NULL, "Precharge"},
370 	{"ADC CH3", NULL, "Precharge"},
371 	{"ADC CH4", NULL, "Precharge"},
373 	{"ADC CH1", NULL, "MICBIAS1"},
374 	{"ADC CH2", NULL, "MICBIAS1"},
375 	{"ADC CH3", NULL, "MICBIAS2"},
376 	{"ADC CH4", NULL, "MICBIAS2"},
378 	{"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
379 	{"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
380 	{"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
381 	{"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
383 	{"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
384 	{"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
385 	{"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
386 	{"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
388 	{"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
389 	{"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
390 	{"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
391 	{"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
393 	{"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
394 	{"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
395 	{"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
396 	{"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
409 	regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);  in nau8540_get_osr()
419 	struct snd_soc_component *component = dai->component;  in nau8540_dai_startup()
424 	if (!osr || !osr->osr)  in nau8540_dai_startup()
425 		return -EINVAL;  in nau8540_dai_startup()
427 	return snd_pcm_hw_constraint_minmax(substream->runtime,  in nau8540_dai_startup()
429 					    0, CLK_ADC_MAX / osr->osr);  in nau8540_dai_startup()
435 	struct snd_soc_component *component = dai->component;  in nau8540_hw_params()
441 	 * ADC clock frequency is defined as Over Sampling Rate (OSR)  in nau8540_hw_params()
447 	if (!osr || !osr->osr)  in nau8540_hw_params()
448 		return -EINVAL;  in nau8540_hw_params()
449 	if (params_rate(params) * osr->osr > CLK_ADC_MAX)  in nau8540_hw_params()
450 		return -EINVAL;  in nau8540_hw_params()
451 	regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_hw_params()
453 		osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);  in nau8540_hw_params()
469 		return -EINVAL;  in nau8540_hw_params()
472 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,  in nau8540_hw_params()
480 	struct snd_soc_component *component = dai->component;  in nau8540_set_fmt()
491 		return -EINVAL;  in nau8540_set_fmt()
501 		return -EINVAL;  in nau8540_set_fmt()
522 		return -EINVAL;  in nau8540_set_fmt()
525 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,  in nau8540_set_fmt()
528 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in nau8540_set_fmt()
530 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in nau8540_set_fmt()
537  * nau8540_set_tdm_slot - configure DAI TX TDM.
551 	struct snd_soc_component *component = dai->component;  in nau8540_set_tdm_slot()
556 		return -EINVAL;  in nau8540_set_tdm_slot()
565 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,  in nau8540_set_tdm_slot()
568 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,  in nau8540_set_tdm_slot()
570 	regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,  in nau8540_set_tdm_slot()
580 	struct snd_soc_component *component = dai->component;  in nau8540_dai_trigger()
582 	struct regmap *regmap = nau8540->regmap;  in nau8540_dai_trigger()
586 	/* Reading the peak data to detect abnormal data in the ADC channel.  in nau8540_dai_trigger()
588 	 * refresh the ADC channel.  in nau8540_dai_trigger()
598 		dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val);  in nau8540_dai_trigger()
607 			dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val);  in nau8540_dai_trigger()
609 				dev_err(nau8540->dev, "Channel recovery failed!!");  in nau8540_dai_trigger()
610 				ret = -EIO;  in nau8540_dai_trigger()
627 	.startup = nau8540_dai_startup,
639 	.name = "nau8540-hifi",
651  * nau8540_calc_fll_param - Calculate FLL parameters.
667 	 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.  in nau8540_calc_fll_param()
676 		return -EINVAL;  in nau8540_calc_fll_param()
677 	fll_param->clk_ref_div = fll_pre_scalar[i].val;  in nau8540_calc_fll_param()
685 		return -EINVAL;  in nau8540_calc_fll_param()
686 	fll_param->ratio = fll_ratio[i].val;  in nau8540_calc_fll_param()
689 	 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be  in nau8540_calc_fll_param()
704 		return -EINVAL;  in nau8540_calc_fll_param()
705 	fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;  in nau8540_calc_fll_param()
707 	/* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional  in nau8540_calc_fll_param()
710 	fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);  in nau8540_calc_fll_param()
711 	fll_param->fll_int = (fvco >> 16) & 0x3FF;  in nau8540_calc_fll_param()
712 	fll_param->fll_frac = fvco & 0xFFFF;  in nau8540_calc_fll_param()
721 		NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);  in nau8540_fll_apply()
724 		fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));  in nau8540_fll_apply()
725 	/* FLL 16-bit fractional input */  in nau8540_fll_apply()
726 	regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);  in nau8540_fll_apply()
727 	/* FLL 10-bit integer input */  in nau8540_fll_apply()
729 		NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);  in nau8540_fll_apply()
730 	/* FLL pre-scaler */  in nau8540_fll_apply()
733 		fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);  in nau8540_fll_apply()
738 	if (fll_param->fll_frac) {  in nau8540_fll_apply()
766 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
772 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
779 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,  in nau8540_set_pll()
786 		dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);  in nau8540_set_pll()
787 		return -EINVAL;  in nau8540_set_pll()
789 	dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",  in nau8540_set_pll()
795 		dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);  in nau8540_set_pll()
798 	dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",  in nau8540_set_pll()
802 	nau8540_fll_apply(nau8540->regmap, &fll_param);  in nau8540_set_pll()
804 	regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_pll()
818 		regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_sysclk()
820 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,  in nau8540_set_sysclk()
825 		regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,  in nau8540_set_sysclk()
827 		regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,  in nau8540_set_sysclk()
832 		dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);  in nau8540_set_sysclk()
833 		return -EINVAL;  in nau8540_set_sysclk()
836 	dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",  in nau8540_set_sysclk()
850 	struct regmap *regmap = nau8540->regmap;  in nau8540_init_regs()
865 	/* ADC OSR selection, CLK_ADC = Fs * OSR;  in nau8540_init_regs()
866 	 * Channel time alignment enable.  in nau8540_init_regs()
889 	regcache_cache_only(nau8540->regmap, true);  in nau8540_suspend()
890 	regcache_mark_dirty(nau8540->regmap);  in nau8540_suspend()
899 	regcache_cache_only(nau8540->regmap, false);  in nau8540_resume()
900 	regcache_sync(nau8540->regmap);  in nau8540_resume()
938 	struct device *dev = &i2c->dev;  in nau8540_i2c_probe()
945 			return -ENOMEM;  in nau8540_i2c_probe()
949 	nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);  in nau8540_i2c_probe()
950 	if (IS_ERR(nau8540->regmap))  in nau8540_i2c_probe()
951 		return PTR_ERR(nau8540->regmap);  in nau8540_i2c_probe()
952 	ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);  in nau8540_i2c_probe()
959 	nau8540->dev = dev;  in nau8540_i2c_probe()
960 	nau8540_reset_chip(nau8540->regmap);  in nau8540_i2c_probe()