Lines Matching +full:adc +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <sound/soc-dapm.h>
182 static const DECLARE_TLV_DB_MINMAX(adc_vol_tlv, -12800, 3600);
183 static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
206 "ADC channel 1", "ADC channel 2", "ADC channel 3", "ADC channel 4"
235 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
240 regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,
256 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
261 regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,
264 regmap_update_bits(nau8540->regmap, NAU8540_REG_REFERENCE,
266 regmap_update_bits(nau8540->regmap, NAU8540_REG_FEPGA2,
278 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
284 regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
286 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
288 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
291 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
293 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
295 regmap_update_bits(nau8540->regmap, NAU8540_REG_POWER_MANAGEMENT,
304 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
308 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0001);
309 regmap_write(nau8540->regmap, NAU8540_REG_RST, 0x0000);
335 SND_SOC_DAPM_PGA_S("ADC CH1", 2, NAU8540_REG_ANALOG_PWR, 0, 0,
337 SND_SOC_DAPM_PGA_S("ADC CH2", 2, NAU8540_REG_ANALOG_PWR, 1, 0,
339 SND_SOC_DAPM_PGA_S("ADC CH3", 2, NAU8540_REG_ANALOG_PWR, 2, 0,
341 SND_SOC_DAPM_PGA_S("ADC CH4", 2, NAU8540_REG_ANALOG_PWR, 3, 0,
344 SND_SOC_DAPM_MUX("Digital CH4 Mux",
346 SND_SOC_DAPM_MUX("Digital CH3 Mux",
348 SND_SOC_DAPM_MUX("Digital CH2 Mux",
350 SND_SOC_DAPM_MUX("Digital CH1 Mux",
368 {"ADC CH1", NULL, "Precharge"},
369 {"ADC CH2", NULL, "Precharge"},
370 {"ADC CH3", NULL, "Precharge"},
371 {"ADC CH4", NULL, "Precharge"},
373 {"ADC CH1", NULL, "MICBIAS1"},
374 {"ADC CH2", NULL, "MICBIAS1"},
375 {"ADC CH3", NULL, "MICBIAS2"},
376 {"ADC CH4", NULL, "MICBIAS2"},
378 {"Digital CH1 Mux", "ADC channel 1", "ADC CH1"},
379 {"Digital CH1 Mux", "ADC channel 2", "ADC CH2"},
380 {"Digital CH1 Mux", "ADC channel 3", "ADC CH3"},
381 {"Digital CH1 Mux", "ADC channel 4", "ADC CH4"},
383 {"Digital CH2 Mux", "ADC channel 1", "ADC CH1"},
384 {"Digital CH2 Mux", "ADC channel 2", "ADC CH2"},
385 {"Digital CH2 Mux", "ADC channel 3", "ADC CH3"},
386 {"Digital CH2 Mux", "ADC channel 4", "ADC CH4"},
388 {"Digital CH3 Mux", "ADC channel 1", "ADC CH1"},
389 {"Digital CH3 Mux", "ADC channel 2", "ADC CH2"},
390 {"Digital CH3 Mux", "ADC channel 3", "ADC CH3"},
391 {"Digital CH3 Mux", "ADC channel 4", "ADC CH4"},
393 {"Digital CH4 Mux", "ADC channel 1", "ADC CH1"},
394 {"Digital CH4 Mux", "ADC channel 2", "ADC CH2"},
395 {"Digital CH4 Mux", "ADC channel 3", "ADC CH3"},
396 {"Digital CH4 Mux", "ADC channel 4", "ADC CH4"},
398 {"AIFTX", NULL, "Digital CH1 Mux"},
399 {"AIFTX", NULL, "Digital CH2 Mux"},
400 {"AIFTX", NULL, "Digital CH3 Mux"},
401 {"AIFTX", NULL, "Digital CH4 Mux"},
409 regmap_read(nau8540->regmap, NAU8540_REG_ADC_SAMPLE_RATE, &osr);
419 struct snd_soc_component *component = dai->component;
424 if (!osr || !osr->osr)
425 return -EINVAL;
427 return snd_pcm_hw_constraint_minmax(substream->runtime,
429 0, CLK_ADC_MAX / osr->osr);
435 struct snd_soc_component *component = dai->component;
441 * ADC clock frequency is defined as Over Sampling Rate (OSR)
447 if (!osr || !osr->osr)
448 return -EINVAL;
449 if (params_rate(params) * osr->osr > CLK_ADC_MAX)
450 return -EINVAL;
451 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
453 osr->clk_src << NAU8540_CLK_ADC_SRC_SFT);
469 return -EINVAL;
472 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
480 struct snd_soc_component *component = dai->component;
491 return -EINVAL;
501 return -EINVAL;
522 return -EINVAL;
525 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL0,
528 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
530 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
537 * nau8540_set_tdm_slot - configure DAI TX TDM.
551 struct snd_soc_component *component = dai->component;
556 return -EINVAL;
565 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL4,
568 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL1,
570 regmap_update_bits(nau8540->regmap, NAU8540_REG_PCM_CTRL2,
580 struct snd_soc_component *component = dai->component;
582 struct regmap *regmap = nau8540->regmap;
586 /* Reading the peak data to detect abnormal data in the ADC channel.
588 * refresh the ADC channel.
598 dev_dbg(nau8540->dev, "1.ADC CH1 peak data %x", val);
607 dev_dbg(nau8540->dev, "2.ADC CH1 peak data %x", val);
609 dev_err(nau8540->dev, "Channel recovery failed!!");
610 ret = -EIO;
639 .name = "nau8540-hifi",
651 * nau8540_calc_fll_param - Calculate FLL parameters.
667 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
676 return -EINVAL;
677 fll_param->clk_ref_div = fll_pre_scalar[i].val;
685 return -EINVAL;
686 fll_param->ratio = fll_ratio[i].val;
689 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
704 return -EINVAL;
705 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
707 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
710 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
711 fll_param->fll_int = (fvco >> 16) & 0x3FF;
712 fll_param->fll_frac = fvco & 0xFFFF;
721 NAU8540_CLK_SRC_MCLK | fll_param->mclk_src);
724 fll_param->ratio | (0x6 << NAU8540_ICTRL_LATCH_SFT));
725 /* FLL 16-bit fractional input */
726 regmap_write(regmap, NAU8540_REG_FLL2, fll_param->fll_frac);
727 /* FLL 10-bit integer input */
729 NAU8540_FLL_INTEGER_MASK, fll_param->fll_int);
730 /* FLL pre-scaler */
733 fll_param->clk_ref_div << NAU8540_FLL_REF_DIV_SFT);
738 if (fll_param->fll_frac) {
766 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
772 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
779 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL3,
786 dev_err(nau8540->dev, "Invalid clock id (%d)\n", pll_id);
787 return -EINVAL;
789 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
795 dev_err(nau8540->dev, "Unsupported input clock %d\n", freq_in);
798 dev_dbg(nau8540->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
802 nau8540_fll_apply(nau8540->regmap, &fll_param);
804 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
818 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
820 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
825 regmap_update_bits(nau8540->regmap, NAU8540_REG_FLL6,
827 regmap_update_bits(nau8540->regmap, NAU8540_REG_CLOCK_SRC,
832 dev_err(nau8540->dev, "Invalid clock id (%d)\n", clk_id);
833 return -EINVAL;
836 dev_dbg(nau8540->dev, "Sysclk is %dHz and clock id is %d\n",
850 struct regmap *regmap = nau8540->regmap;
865 /* ADC OSR selection, CLK_ADC = Fs * OSR;
889 regcache_cache_only(nau8540->regmap, true);
890 regcache_mark_dirty(nau8540->regmap);
899 regcache_cache_only(nau8540->regmap, false);
900 regcache_sync(nau8540->regmap);
938 struct device *dev = &i2c->dev;
945 return -ENOMEM;
949 nau8540->regmap = devm_regmap_init_i2c(i2c, &nau8540_regmap_config);
950 if (IS_ERR(nau8540->regmap))
951 return PTR_ERR(nau8540->regmap);
952 ret = regmap_read(nau8540->regmap, NAU8540_REG_I2C_DEVICE_ID, &value);
959 nau8540->dev = dev;
960 nau8540_reset_chip(nau8540->regmap);