Lines Matching +full:mclk +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0-only
3 // nau8325.c -- Nuvoton NAU8325 audio codec driver
25 /* Range of Master Clock MCLK (Hz) */
29 /* scaling for MCLK source */
30 #define CLK_PROC_BYPASS (-1)
35 /* from MCLK input */
70 /* { FS, range, max, { MCLK source }} */
192 static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -8000, 600);
219 snd_soc_dapm_to_component(w->dapm);
224 regmap_update_bits(nau8325->regmap, NAU8325_R12_MUTE_CTRL,
230 regmap_update_bits(nau8325->regmap, NAU8325_R12_MUTE_CTRL,
235 return -EINVAL;
245 snd_soc_dapm_to_component(w->dapm);
248 if (nau8325->clock_detection)
253 regmap_update_bits(nau8325->regmap, NAU8325_R40_CLK_DET_CTRL,
257 regmap_update_bits(nau8325->regmap, NAU8325_R40_CLK_DET_CTRL,
261 return -EINVAL;
299 dev_dbg(nau8325->dev, "The CLK isn't supported.");
300 return -EINVAL;
303 regmap_update_bits(nau8325->regmap, NAU8325_R40_CLK_DET_CTRL,
305 (srate_table->range << NAU8325_REG_SRATE_SFT) |
306 (srate_table->max ? NAU8325_REG_DIV_MAX : 0));
307 regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
309 regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
314 regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
319 regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
325 regmap_update_bits(nau8325->regmap, NAU8325_R65_ANALOG_CONTROL_5,
329 regmap_update_bits(nau8325->regmap, NAU8325_R65_ANALOG_CONTROL_5,
334 regmap_update_bits(nau8325->regmap, NAU8325_R65_ANALOG_CONTROL_5,
344 int mclk, int *n2_sel)
350 mclk_src = mclk >> mclk_n2_div[i].param;
351 if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_256] == mclk_src) {
354 } else if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_400] == mclk_src) {
357 } else if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_500] == mclk_src) {
389 int i, j, mclk, mclk_max, ratio, ratio_sel, n2_max;
391 if (!nau8325->mclk || !nau8325->fs)
395 *srate_table = target_srate_attribute(nau8325->fs);
399 /* First check clock from MCLK directly, decide N2 for MCLK_SRC.
402 ratio = nau8325_clksrc_n2(nau8325, *srate_table, nau8325->mclk, n2_sel);
414 mclk = nau8325->mclk << mclk_n3_mult[j].param;
415 mclk = mclk / mclk_n1_div[i].param;
417 *srate_table, mclk, n2_sel);
419 (mclk_max < mclk || i > *n1_sel)) {
420 mclk_max = mclk;
436 dev_dbg(nau8325->dev, "The MCLK %d is invalid. It can't get MCLK_SRC of 256/400/500 FS (%d)",
437 nau8325->mclk, nau8325->fs);
438 return -EINVAL;
440 dev_dbg(nau8325->dev, "nau8325->fs=%d,range=0x%x, %s, (n1,mu,n2,dmu):(%d,%d,%d), MCLK_SRC=%uHz (%d)",
441 nau8325->fs, (*srate_table)->range,
442 (*srate_table)->max ? "MAX" : "MIN",
448 (*srate_table)->mclk_src[ratio],
449 (*srate_table)->mclk_src[ratio] / nau8325->fs);
478 regmap_read(nau8325->regmap, NAU8325_R29_DAC_CTRL1, &osr);
489 struct snd_soc_component *component = dai->component;
494 if (!osr || !osr->osr)
495 return -EINVAL;
497 return snd_pcm_hw_constraint_minmax(substream->runtime,
499 0, CLK_DA_AD_MAX / osr->osr);
506 struct snd_soc_component *component = dai->component;
512 nau8325->fs = params_rate(params);
514 if (!osr || !osr->osr || nau8325->fs * osr->osr > CLK_DA_AD_MAX) {
515 ret = -EINVAL;
518 regmap_update_bits(nau8325->regmap, NAU8325_R03_CLK_CTRL,
520 osr->clk_src << NAU8325_CLK_DAC_SRC_SFT);
540 ret = -EINVAL;
544 regmap_update_bits(nau8325->regmap, NAU8325_R0D_I2S_PCM_CTRL1,
555 struct snd_soc_component *component = dai->component;
563 return -EINVAL;
573 return -EINVAL;
594 return -EINVAL;
597 regmap_update_bits(nau8325->regmap, NAU8325_R0D_I2S_PCM_CTRL1,
610 dev_dbg(nau8325->dev, "MCLK exceeds the range, MCLK:%d", freq);
611 return -EINVAL;
614 nau8325->mclk = freq;
615 dev_dbg(nau8325->dev, "MCLK %dHz", nau8325->mclk);
675 struct regmap *regmap = nau8325->regmap;
676 struct device *dev = nau8325->dev;
688 if (nau8325->alc_enable)
691 if (nau8325->clock_detection)
699 if (nau8325->clock_det_data)
707 switch (nau8325->dac_vref_microvolt) {
725 dev_dbg(dev, "Invalid dac-vref-microvolt %d", nau8325->dac_vref_microvolt);
732 /* Auto-Att Min Gain 0dB, Class-D N Driver Slew Rate -25%. */
737 switch (nau8325->vref_impedance_ohms) {
755 dev_dbg(dev, "Invalid vref-impedance-ohms %d", nau8325->vref_impedance_ohms);
775 if (nau8325->alc_enable)
778 if (nau8325->clock_det_data)
784 if (nau8325->clock_detection)
799 struct device *dev = nau8325->dev;
801 dev_dbg(dev, "vref-impedance-ohms: %d", nau8325->vref_impedance_ohms);
802 dev_dbg(dev, "dac-vref-microvolt: %d", nau8325->dac_vref_microvolt);
803 dev_dbg(dev, "alc-enable: %d", nau8325->alc_enable);
804 dev_dbg(dev, "clock-det-data: %d", nau8325->clock_det_data);
805 dev_dbg(dev, "clock-detection-disable: %d", nau8325->clock_detection);
813 nau8325->alc_enable =
814 device_property_read_bool(dev, "nuvoton,alc-enable");
815 nau8325->clock_det_data =
816 device_property_read_bool(dev, "nuvoton,clock-det-data");
817 nau8325->clock_detection =
818 !device_property_read_bool(dev, "nuvoton,clock-detection-disable");
820 ret = device_property_read_u32(dev, "nuvoton,vref-impedance-ohms",
821 &nau8325->vref_impedance_ohms);
823 nau8325->vref_impedance_ohms = 125000;
824 ret = device_property_read_u32(dev, "nuvoton,dac-vref-microvolt",
825 &nau8325->dac_vref_microvolt);
827 nau8325->dac_vref_microvolt = 2880000;
834 struct device *dev = &i2c->dev;
841 ret = -ENOMEM;
850 nau8325->regmap = devm_regmap_init_i2c(i2c, &nau8325_regmap_config);
851 if (IS_ERR(nau8325->regmap)) {
852 ret = PTR_ERR(nau8325->regmap);
855 nau8325->dev = dev;
858 nau8325_reset_chip(nau8325->regmap);
859 ret = regmap_read(nau8325->regmap, NAU8325_R02_DEVICE_ID, &value);
861 dev_dbg(dev, "Failed to read device id (%d)", ret);