Lines Matching full:mclk_src
36 #define MCLK_SRC 4 macro
68 /* Sample Rate and MCLK_SRC selections */
346 int i, mclk_src, ratio; in nau8325_clksrc_n2() local
350 mclk_src = mclk >> mclk_n2_div[i].param; in nau8325_clksrc_n2()
351 if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_256] == mclk_src) { in nau8325_clksrc_n2()
354 } else if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_400] == mclk_src) { in nau8325_clksrc_n2()
357 } else if (srate_table->mclk_src[NAU8325_MCLK_FS_RATIO_500] == mclk_src) { in nau8325_clksrc_n2()
394 /* select sampling rate and MCLK_SRC */ in nau8325_clksrc_choose()
399 /* First check clock from MCLK directly, decide N2 for MCLK_SRC. in nau8325_clksrc_choose()
406 *n2_sel = MCLK_SRC; in nau8325_clksrc_choose()
410 /* Get MCLK_SRC through 1/N, Multiplier, and then 1/N2. */ in nau8325_clksrc_choose()
436 dev_dbg(nau8325->dev, "The MCLK %d is invalid. It can't get MCLK_SRC of 256/400/500 FS (%d)", in nau8325_clksrc_choose()
440 …dev_dbg(nau8325->dev, "nau8325->fs=%d,range=0x%x, %s, (n1,mu,n2,dmu):(%d,%d,%d), MCLK_SRC=%uHz (%d… in nau8325_clksrc_choose()
448 (*srate_table)->mclk_src[ratio], in nau8325_clksrc_choose()
449 (*srate_table)->mclk_src[ratio] / nau8325->fs); in nau8325_clksrc_choose()