Lines Matching +full:aux +full:- +full:output +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0
3 // mt6359.c -- mt6359 ALSA SoC audio codec driver
24 regmap_update_bits(priv->regmap, MT6359_SMT_CON1, 0x3ff0, 0x3ff0);
30 regmap_update_bits(priv->regmap, MT6359_DRV_CON2, 0xffff, 0x8888);
31 regmap_update_bits(priv->regmap, MT6359_DRV_CON3, 0xffff, 0x8888);
32 regmap_update_bits(priv->regmap, MT6359_DRV_CON4, 0x00ff, 0x88);
38 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ffe);
39 regmap_write(priv->regmap, MT6359_GPIO_MODE2_SET, 0x0249);
42 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x6);
43 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x1);
53 regmap_write(priv->regmap, MT6359_GPIO_MODE2_CLR, 0x0ff8);
54 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0, 0x7 << 9, 0x0);
60 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
61 regmap_write(priv->regmap, MT6359_GPIO_MODE3_SET, 0x0200);
63 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
64 regmap_write(priv->regmap, MT6359_GPIO_MODE4_SET, 0x0009);
75 regmap_write(priv->regmap, MT6359_GPIO_MODE3_CLR, 0x0e00);
77 regmap_write(priv->regmap, MT6359_GPIO_MODE4_CLR, 0x003f);
79 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR0,
81 regmap_update_bits(priv->regmap, MT6359_GPIO_DIR1,
86 static void mt6359_set_dcxo(struct mt6359_priv *priv, bool enable)
88 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
90 (enable ? 1 : 0) << RG_XO_AUDIO_EN_M_SFT);
94 static void mt6359_set_clksq(struct mt6359_priv *priv, bool enable)
96 /* Enable/disable CLKSQ 26MHz */
97 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
99 (enable ? 1 : 0) << RG_CLKSQ_EN_SFT);
103 static void mt6359_set_aud_global_bias(struct mt6359_priv *priv, bool enable)
105 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
107 (enable ? 0 : 1) << RG_AUDGLB_PWRDN_VA32_SFT);
111 static void mt6359_set_topck(struct mt6359_priv *priv, bool enable)
113 regmap_update_bits(priv->regmap, MT6359_AUD_TOP_CKPDN_CON0,
114 0x0066, enable ? 0x0 : 0x66);
117 static void mt6359_set_decoder_clk(struct mt6359_priv *priv, bool enable)
119 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON13,
121 (enable ? 1 : 0) << RG_RSTB_DECODER_VA32_SFT);
126 switch (priv->mtkaif_protocol) {
129 regmap_update_bits(priv->regmap,
132 /* enable aud_pad TX fifos */
133 regmap_update_bits(priv->regmap,
136 regmap_update_bits(priv->regmap,
142 regmap_update_bits(priv->regmap,
145 /* enable aud_pad TX fifos */
146 regmap_update_bits(priv->regmap,
153 regmap_update_bits(priv->regmap,
156 /* enable aud_pad TX fifos */
157 regmap_update_bits(priv->regmap,
167 regmap_update_bits(priv->regmap, MT6359_AFE_AUD_PAD_TOP,
176 priv->mtkaif_protocol = mtkaif_protocol;
194 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
197 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
200 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
211 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
214 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
217 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
237 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
240 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG,
243 regmap_update_bits(priv->regmap, MT6359_AUDIO_DIG_CFG1,
251 regmap_write(priv->regmap, MT6359_ZCD_CON0, 0x0000);
259 /* Enable/Reduce HPL/R main output stage step by step */
261 stage = up ? i : target - i;
262 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
265 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
277 /* Enable/Reduce HP aux feedback loop gain step by step */
279 stage = up ? i : target - i;
280 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
291 /* Set input diff pair bias select (Hi-Fi mode) */
292 if (priv->hp_hifi_mode) {
293 /* Reduce HP aux feedback loop gain step by step */
295 stage = increase ? i : target - i;
296 regmap_update_bits(priv->regmap,
304 static void hp_pull_down(struct mt6359_priv *priv, bool enable)
308 if (enable) {
310 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
316 for (i = 0x7; i >= 0x0; i--) {
317 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
337 dev_warn(priv->dev, "%s(), volume index is not valid, from %d, to %d\n",
342 dev_dbg(priv->dev, "%s(), from %d, to %d\n", __func__, from, to);
345 offset = to - from;
347 offset = from - to;
353 reg_idx = from - count;
356 regmap_update_bits(priv->regmap,
362 offset--;
374 (struct soc_mixer_control *)kcontrol->private_value;
376 int index = ucontrol->value.integer.value[0];
380 switch (mc->reg) {
382 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
383 orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
386 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
387 orig_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
390 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
393 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
396 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
399 orig_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
402 return -EINVAL;
409 switch (mc->reg) {
411 regmap_read(priv->regmap, MT6359_ZCD_CON2, ®);
412 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL] =
414 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR] =
416 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
417 new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
420 regmap_read(priv->regmap, MT6359_ZCD_CON1, ®);
421 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL] =
423 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR] =
425 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
426 new_gain[1] = priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
429 regmap_read(priv->regmap, MT6359_ZCD_CON3, ®);
430 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL] =
432 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
435 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON0, ®);
436 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1] =
438 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
441 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON1, ®);
442 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2] =
444 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
447 regmap_read(priv->regmap, MT6359_AUDENC_ANA_CON2, ®);
448 priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3] =
450 new_gain[0] = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
462 dev_dbg(priv->dev, "%s(), name %s, reg(0x%x) = 0x%x, set index = %x\n",
463 __func__, kcontrol->id.name, mc->reg, reg, index);
475 (struct soc_mixer_control *)kcontrol->private_value;
477 switch (mc->reg) {
479 ucontrol->value.integer.value[0] =
480 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL];
481 ucontrol->value.integer.value[1] =
482 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTR];
485 ucontrol->value.integer.value[0] =
486 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL];
487 ucontrol->value.integer.value[1] =
488 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTR];
491 ucontrol->value.integer.value[0] =
492 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL];
495 return -EINVAL;
820 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
823 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
828 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0006);
829 /* scrambler clock on enable */
830 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
832 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0003);
833 /* sdm fifo enable */
834 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x000b);
836 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG0,
839 regmap_update_bits(priv->regmap, MT6359_AFE_SGEN_CFG1,
845 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON2, 0x0000);
846 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
857 if (priv->hp_hifi_mode) {
859 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
864 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
867 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
872 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
877 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
880 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
885 /* HP damp circuit enable */
886 /* Enable HPRN/HPLN output 4K to VCM */
887 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0087);
891 if (priv->dl_rate[MT6359_AIF_1] >= 96000)
892 regmap_update_bits(priv->regmap,
897 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON4, 0x0000);
900 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON2, 0xf133);
902 /* Enable HP aux output stage */
903 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x000c);
904 /* Enable HP aux feedback loop */
905 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x003c);
906 /* Enable HP aux CMFB loop */
907 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c00);
908 /* Enable HP driver bias circuits */
909 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30c0);
910 /* Enable HP driver core circuits */
911 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30f0);
912 /* Short HP main output to HP aux output stage */
913 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00fc);
918 /* Enable HP main CMFB loop */
919 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e00);
920 /* Disable HP aux CMFB loop */
921 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0200);
923 /* Enable HP main output stage */
924 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x00ff);
925 /* Enable HPR/L main output stage step by step */
928 /* Reduce HP aux feedback loop gain */
930 /* Disable HP aux feedback loop */
931 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
936 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL]);
938 /* Disable HP aux output stage */
939 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
940 /* Unshort HP main output to HP aux output stage */
941 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x7703);
944 /* Enable AUD_CLK */
947 /* Enable Audio DAC */
948 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x30ff);
949 if (priv->hp_hifi_mode) {
950 /* Enable low-noise mode of DAC */
951 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf201);
953 /* Disable low-noise mode of DAC */
954 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
959 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x32ff);
961 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3aff);
963 /* Disable Pull-down HPL/R to AVSS28_AUD */
969 /* Pull-down HPL/R to AVSS28_AUD */
973 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
976 /* Disable low-noise mode of DAC */
977 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON9,
981 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
987 /* Short HP main output to HP aux output stage */
988 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77c3);
989 /* Enable HP aux output stage */
990 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77cf);
994 priv->ana_gain[AUDIO_ANALOG_VOLUME_HPOUTL],
997 /* Enable HP aux feedback loop */
998 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x77ff);
1000 /* Reduce HP aux feedback loop gain */
1003 /* decrease HPR/L main output stage step by step */
1006 /* Disable HP main output stage */
1007 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1, 0x3, 0x0);
1009 /* Enable HP aux CMFB loop */
1010 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0e01);
1013 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0c01);
1018 /* Unshort HP main output to HP aux output stage */
1019 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1023 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1027 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1030 /* Disable HP aux CMFB loop */
1031 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x201);
1033 /* Disable HP aux feedback loop */
1034 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1037 /* Disable HP aux output stage */
1038 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON1,
1046 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1048 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1051 dev_dbg(priv->dev, "%s(), event 0x%x, dev_counter[DEV_HP] %d, mux %u\n",
1052 __func__, event, priv->dev_counter[device], mux);
1056 priv->dev_counter[device]++;
1061 priv->dev_counter[device]--;
1076 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1079 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1080 __func__, event, dapm_kcontrol_get_value(w->kcontrols[0]));
1084 /* Disable handset short-circuit protection */
1085 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0010);
1088 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1093 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1096 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1101 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0090);
1103 /* Set HS output stage (3'b111 = 8x) */
1104 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x7000);
1106 /* Enable HS driver bias circuits */
1107 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0092);
1108 /* Enable HS driver core circuits */
1109 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x0093);
1112 regmap_write(priv->regmap, MT6359_ZCD_CON3,
1113 priv->ana_gain[AUDIO_ANALOG_VOLUME_HSOUTL]);
1115 /* Enable AUD_CLK */
1118 /* Enable Audio DAC */
1119 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x0009);
1120 /* Enable low-noise mode of DAC */
1121 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
1123 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON6, 0x009b);
1127 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1132 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1139 regmap_write(priv->regmap, MT6359_ZCD_CON3, DL_GAIN_N_40DB);
1142 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1146 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
1160 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1162 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1164 dev_dbg(priv->dev, "%s(), event 0x%x, mux %u\n",
1169 /* Disable handset short-circuit protection */
1170 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0010);
1173 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON11,
1178 if (priv->dev_counter[DEVICE_HP] == 0)
1179 regmap_update_bits(priv->regmap,
1184 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON12,
1189 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0110);
1191 /* Enable LO driver bias circuits */
1192 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0112);
1193 /* Enable LO driver core circuits */
1194 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0113);
1197 regmap_write(priv->regmap, MT6359_ZCD_CON1,
1198 priv->ana_gain[AUDIO_ANALOG_VOLUME_LINEOUTL]);
1200 /* Enable AUD_CLK */
1205 if (priv->dev_counter[DEVICE_HP] > 0) {
1206 dev_info(priv->dev, "%s(), can not enable DAC, hp count %d\n",
1207 __func__, priv->dev_counter[DEVICE_HP]);
1210 /* Enable DACL and switch HP MUX to open*/
1211 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON0, 0x3009);
1212 /* Disable low-noise mode of DAC */
1213 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0xf200);
1216 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x0117);
1218 /* Enable Audio DAC (3rd DAC) */
1219 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x3113);
1220 /* Enable low-noise mode of DAC */
1221 if (priv->dev_counter[DEVICE_HP] == 0)
1222 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON9, 0x0001);
1224 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON7, 0x311b);
1229 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1234 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1239 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1242 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
1250 regmap_write(priv->regmap, MT6359_ZCD_CON1, DL_GAIN_N_40DB);
1253 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1257 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
1271 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1274 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
1279 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1282 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1284 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1286 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1291 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1293 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1295 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1297 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON5,
1311 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1314 dev_dbg(priv->dev, "%s(), event 0x%x\n", __func__, event);
1320 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1322 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1324 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1327 regmap_write(priv->regmap, MT6359_AFE_DCCLK_CFG1, 0x0100);
1330 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1332 regmap_update_bits(priv->regmap, MT6359_AFE_DCCLK_CFG0,
1346 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1348 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1350 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1357 regmap_update_bits(priv->regmap,
1362 regmap_update_bits(priv->regmap,
1367 regmap_update_bits(priv->regmap,
1373 /* DMIC enable */
1374 regmap_write(priv->regmap,
1377 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1381 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON15,
1387 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON15, 0x0000);
1400 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1402 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1404 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1411 regmap_write(priv->regmap,
1414 regmap_write(priv->regmap,
1418 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON16,
1433 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1435 unsigned int mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1437 dev_dbg(priv->dev, "%s(), event 0x%x, mic_type %d\n",
1444 regmap_update_bits(priv->regmap,
1449 regmap_update_bits(priv->regmap,
1454 regmap_update_bits(priv->regmap,
1461 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
1465 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON17,
1471 regmap_write(priv->regmap, MT6359_AUDENC_ANA_CON17, 0x0000);
1484 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1487 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1507 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1510 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1515 if (priv->dmic_one_wire_mode)
1516 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
1519 regmap_write(priv->regmap, MT6359_AFE_UL_SRC_CON0_H,
1522 regmap_update_bits(priv->regmap, MT6359_AFE_UL_SRC_CON0_L,
1526 regmap_write(priv->regmap,
1540 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1543 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1548 regmap_write(priv->regmap,
1550 regmap_update_bits(priv->regmap, MT6359_AFE_ADDA6_UL_SRC_CON0_L,
1554 regmap_write(priv->regmap,
1568 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1571 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1577 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1592 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1595 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1601 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1616 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1619 dev_dbg(priv->dev, "%s(), event = 0x%x\n", __func__, event);
1625 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1640 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1642 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1644 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1645 priv->mux_select[MUX_PGA_L] = mux >> RG_AUDPREAMPLINPUTSEL_SFT;
1653 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1655 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1657 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1658 priv->mux_select[MUX_PGA_R] = mux >> RG_AUDPREAMPRINPUTSEL_SFT;
1666 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1668 unsigned int mux = dapm_kcontrol_get_value(w->kcontrols[0]);
1670 dev_dbg(priv->dev, "%s(), mux %d\n", __func__, mux);
1671 priv->mux_select[MUX_PGA_3] = mux >> RG_AUDPREAMP3INPUTSEL_SFT;
1679 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1681 int mic_gain_l = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP1];
1682 unsigned int mux_pga = priv->mux_select[MUX_PGA_L];
1687 mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1690 mic_type = priv->mux_select[MUX_MIC_TYPE_1];
1693 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1695 return -EINVAL;
1702 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1709 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1715 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1722 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON0,
1737 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1739 int mic_gain_r = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP2];
1740 unsigned int mux_pga = priv->mux_select[MUX_PGA_R];
1745 mic_type = priv->mux_select[MUX_MIC_TYPE_0];
1749 mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1752 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1754 return -EINVAL;
1761 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1768 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1774 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1781 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON1,
1796 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1798 int mic_gain_3 = priv->ana_gain[AUDIO_ANALOG_VOLUME_MICAMP3];
1799 unsigned int mux_pga = priv->mux_select[MUX_PGA_3];
1805 mic_type = priv->mux_select[MUX_MIC_TYPE_2];
1808 dev_err(priv->dev, "%s(), invalid pga mux %d\n",
1810 return -EINVAL;
1817 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1824 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1830 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1837 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON2,
1885 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1906 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1911 /* Set HPR/HPL gain to -22dB */
1912 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_22DB_REG);
1916 regmap_write(priv->regmap, MT6359_ZCD_CON2, DL_GAIN_N_40DB_REG);
1929 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1936 regmap_write(priv->regmap, MT6359_AUDDEC_ANA_CON10, 0x0000);
1949 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1955 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
1962 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON2,
1976 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
1982 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1984 /* scrambler clock on enable */
1985 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba1);
1987 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1989 /* sdm fifo enable */
1990 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1995 regmap_update_bits(priv->regmap, MT6359_AFUNC_AUD_CON2,
1997 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON0, 0xcba0);
2010 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2016 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0006);
2017 /* scrambler clock on enable */
2018 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba1);
2020 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0003);
2021 /* sdm fifo enable */
2022 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x000b);
2026 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON11, 0x0000);
2027 regmap_write(priv->regmap, MT6359_AFUNC_AUD_CON9, 0xcba0);
2040 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2045 regmap_write(priv->regmap, MT6359_AFE_NCP_CFG0, 0xc800);
2234 SND_SOC_DAPM_SUPPLY("SGEN DL Enable", MT6359_AFE_SGEN_CFG0,
2416 struct snd_soc_component *cmpnt = snd_soc_dapm_to_component(w->dapm);
2419 if (IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_0]) ||
2420 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_1]) ||
2421 IS_DCC_BASE(priv->mux_select[MUX_MIC_TYPE_2]))
2440 * *_ADC_CTL should enable only if UL_SRC in use,
2522 * enable ADC_L even use ADC_R only
2600 {"SGEN DL", NULL, "SGEN DL Enable"},
2648 struct snd_soc_component *cmpnt = dai->component;
2651 int id = dai->id;
2653 dev_dbg(priv->dev, "%s(), id %d, substream->stream %d, rate %d, number %d\n",
2654 __func__, id, substream->stream, rate, substream->number);
2656 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2657 priv->dl_rate[id] = rate;
2658 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2659 priv->ul_rate[id] = rate;
2667 struct snd_soc_component *cmpnt = dai->component;
2670 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
2671 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2673 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2682 struct snd_soc_component *cmpnt = dai->component;
2685 dev_dbg(priv->dev, "%s stream %d\n", __func__, substream->stream);
2686 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2688 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2705 .name = "mt6359-snd-codec-aif1",
2731 .name = "mt6359-snd-codec-aif2",
2759 /* enable clk buf */
2760 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
2767 regmap_update_bits(priv->regmap, MT6359_AUDENC_ANA_CON23,
2772 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
2775 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON0,
2779 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON6,
2783 regmap_update_bits(priv->regmap, MT6359_AUDDEC_ANA_CON7,
2794 priv->hp_hifi_mode = 0;
2800 regmap_update_bits(priv->regmap, MT6359_DCXO_CW12,
2811 snd_soc_component_init_regmap(cmpnt, priv->regmap);
2818 cmpnt->regmap = NULL;
2821 static const DECLARE_TLV_DB_SCALE(playback_tlv, -1000, 100, 0);
2867 struct device *dev = priv->dev;
2870 np = of_get_child_by_name(dev->parent->of_node, "audio-codec");
2872 np = of_get_child_by_name(dev->parent->of_node, "mt6359codec");
2874 return -EINVAL;
2877 ret = of_property_read_u32(np, "mediatek,dmic-mode",
2878 &priv->dmic_one_wire_mode);
2880 dev_info(priv->dev,
2881 "%s() failed to read dmic-mode, use default (0)\n",
2883 priv->dmic_one_wire_mode = 0;
2886 ret = of_property_read_u32(np, "mediatek,mic-type-0",
2887 &priv->mux_select[MUX_MIC_TYPE_0]);
2889 dev_info(priv->dev,
2890 "%s() failed to read mic-type-0, use default (%d)\n",
2892 priv->mux_select[MUX_MIC_TYPE_0] = MIC_TYPE_MUX_IDLE;
2895 ret = of_property_read_u32(np, "mediatek,mic-type-1",
2896 &priv->mux_select[MUX_MIC_TYPE_1]);
2898 dev_info(priv->dev,
2899 "%s() failed to read mic-type-1, use default (%d)\n",
2901 priv->mux_select[MUX_MIC_TYPE_1] = MIC_TYPE_MUX_IDLE;
2904 ret = of_property_read_u32(np, "mediatek,mic-type-2",
2905 &priv->mux_select[MUX_MIC_TYPE_2]);
2908 dev_info(priv->dev,
2909 "%s() failed to read mic-type-2, use default (%d)\n",
2911 priv->mux_select[MUX_MIC_TYPE_2] = MIC_TYPE_MUX_IDLE;
2921 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
2923 dev_dbg(&pdev->dev, "%s(), dev name %s\n",
2924 __func__, dev_name(&pdev->dev));
2926 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2928 return -ENOMEM;
2930 priv->regmap = mt6397->regmap;
2931 if (IS_ERR(priv->regmap))
2932 return PTR_ERR(priv->regmap);
2934 dev_set_drvdata(&pdev->dev, priv);
2935 priv->dev = &pdev->dev;
2939 dev_warn(&pdev->dev, "%s() failed to parse dts\n", __func__);
2943 return devm_snd_soc_register_component(&pdev->dev,
2951 .name = "mt6359-sound",