Lines Matching +full:imon +full:- +full:slot +full:- +full:no
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * max98927.c -- MAX98927 ALSA Soc Audio driver
5 * Copyright (C) 2016-2017 Maxim Integrated Products
140 struct snd_soc_component *component = codec_dai->component;
147 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
151 max98927->provider = false;
155 max98927->provider = true;
159 dev_err(component->dev, "DAI clock mode unsupported\n");
160 return -EINVAL;
163 regmap_update_bits(max98927->regmap, MAX98927_R0021_PCM_MASTER_MODE,
173 dev_err(component->dev, "DAI invert mode unsupported\n");
174 return -EINVAL;
177 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
198 return -EINVAL;
200 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
204 regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
208 regmap_update_bits(max98927->regmap,
213 regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
216 regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
220 regmap_update_bits(max98927->regmap, MAX98927_R0035_PDM_RX_CTRL,
223 regmap_update_bits(max98927->regmap, MAX98927_R003B_SPK_SRC_SEL,
226 regmap_update_bits(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
258 struct snd_soc_component *component = max98927->component;
260 int blr_clk_ratio = params_channels(params) * max98927->ch_size;
263 if (max98927->provider) {
267 if (rate_table[i] >= max98927->sysclk)
271 dev_err(component->dev, "failed to find proper clock rate.\n");
272 return -EINVAL;
274 regmap_update_bits(max98927->regmap,
280 if (!max98927->tdm_mode) {
284 dev_err(component->dev, "format unsupported %d\n",
286 return -EINVAL;
289 regmap_update_bits(max98927->regmap,
300 struct snd_soc_component *component = dai->component;
317 dev_err(component->dev, "format unsupported %d\n",
322 max98927->ch_size = snd_pcm_format_width(params_format(params));
324 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
327 dev_dbg(component->dev, "format supported %d",
360 dev_err(component->dev, "rate %d not supported\n",
365 regmap_update_bits(max98927->regmap, MAX98927_R0023_PCM_SR_SETUP1,
367 regmap_update_bits(max98927->regmap, MAX98927_R0024_PCM_SR_SETUP2,
372 if (max98927->interleave_mode &&
374 regmap_update_bits(max98927->regmap,
377 sampling_rate - 3);
379 regmap_update_bits(max98927->regmap,
385 return -EINVAL;
392 struct snd_soc_component *component = dai->component;
397 max98927->tdm_mode = true;
402 dev_err(component->dev, "BCLK %d not supported\n",
404 return -EINVAL;
407 regmap_update_bits(max98927->regmap, MAX98927_R0022_PCM_CLK_SETUP,
422 dev_err(component->dev, "format unsupported %d\n",
424 return -EINVAL;
427 regmap_update_bits(max98927->regmap, MAX98927_R0020_PCM_MODE_CFG,
430 /* Rx slot configuration */
431 regmap_write(max98927->regmap, MAX98927_R0018_PCM_RX_EN_A,
433 regmap_write(max98927->regmap, MAX98927_R0019_PCM_RX_EN_B,
436 /* Tx slot configuration */
437 regmap_write(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
439 regmap_write(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
442 /* Tx slot Hi-Z configuration */
443 regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
445 regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
459 struct snd_soc_component *component = dai->component;
462 max98927->sysclk = freq;
476 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
481 max98927->tdm_mode = false;
484 regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
486 regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
490 regmap_update_bits(max98927->regmap, MAX98927_R00FF_GLOBAL_SHDN,
492 regmap_update_bits(max98927->regmap, MAX98927_R003A_AMP_EN,
529 SND_SOC_DAPM_SIGGEN("IMON"),
533 static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
600 0, (1 << MAX98927_AMP_VOL_WIDTH) - 1, 0,
622 { "VI Sense", "Switch", "IMON" },
629 .name = "max98927-aif1",
652 max98927->component = component;
655 regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
658 /* IV default slot configuration */
659 regmap_write(max98927->regmap, MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0xFF);
660 regmap_write(max98927->regmap, MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0xFF);
661 regmap_write(max98927->regmap, MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
663 regmap_write(max98927->regmap, MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
666 regmap_write(max98927->regmap, MAX98927_R0036_AMP_VOL_CTRL, 0x38);
667 regmap_write(max98927->regmap, MAX98927_R003C_SPK_GAIN, 0x05);
669 regmap_write(max98927->regmap, MAX98927_R0037_AMP_DSP_CFG, 0x03);
670 /* Enable IMON VMON DC blocker */
671 regmap_write(max98927->regmap, MAX98927_R003F_MEAS_DSP_CFG, 0xF7);
673 regmap_write(max98927->regmap, MAX98927_R0040_BOOST_CTRL0, 0x1C);
674 regmap_write(max98927->regmap, MAX98927_R0042_BOOST_CTRL1, 0x3E);
676 regmap_write(max98927->regmap, MAX98927_R0043_MEAS_ADC_CFG, 0x04);
677 regmap_write(max98927->regmap, MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x00);
678 regmap_write(max98927->regmap, MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x24);
680 regmap_write(max98927->regmap, MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
683 regmap_write(max98927->regmap, MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
685 regmap_write(max98927->regmap, MAX98927_R0086_ENV_TRACK_CTRL, 0x01);
686 regmap_write(max98927->regmap, MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
689 /* voltage, current slot configuration */
690 regmap_write(max98927->regmap, MAX98927_R001E_PCM_TX_CH_SRC_A,
691 (max98927->i_l_slot << MAX98927_PCM_TX_CH_SRC_A_I_SHIFT | max98927->v_l_slot) & 0xFF);
693 if (max98927->v_l_slot < 8) {
694 regmap_update_bits(max98927->regmap,
696 1 << max98927->v_l_slot, 0);
697 regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
698 1 << max98927->v_l_slot,
699 1 << max98927->v_l_slot);
701 regmap_update_bits(max98927->regmap,
703 1 << (max98927->v_l_slot - 8), 0);
704 regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
705 1 << (max98927->v_l_slot - 8),
706 1 << (max98927->v_l_slot - 8));
709 if (max98927->i_l_slot < 8) {
710 regmap_update_bits(max98927->regmap,
712 1 << max98927->i_l_slot, 0);
713 regmap_update_bits(max98927->regmap, MAX98927_R001A_PCM_TX_EN_A,
714 1 << max98927->i_l_slot,
715 1 << max98927->i_l_slot);
717 regmap_update_bits(max98927->regmap,
719 1 << (max98927->i_l_slot - 8), 0);
720 regmap_update_bits(max98927->regmap, MAX98927_R001B_PCM_TX_EN_B,
721 1 << (max98927->i_l_slot - 8),
722 1 << (max98927->i_l_slot - 8));
726 if (max98927->interleave_mode)
727 regmap_update_bits(max98927->regmap,
738 regcache_cache_only(max98927->regmap, true);
739 regcache_mark_dirty(max98927->regmap);
746 regmap_write(max98927->regmap, MAX98927_R0100_SOFT_RESET,
748 regcache_cache_only(max98927->regmap, false);
749 regcache_sync(max98927->regmap);
785 struct device *dev = &i2c->dev;
787 if (!device_property_read_u32(dev, "vmon-slot-no", &value))
788 max98927->v_l_slot = value & 0xF;
790 max98927->v_l_slot = 0;
792 if (!device_property_read_u32(dev, "imon-slot-no", &value))
793 max98927->i_l_slot = value & 0xF;
795 max98927->i_l_slot = 1;
805 max98927 = devm_kzalloc(&i2c->dev, sizeof(*max98927), GFP_KERNEL);
807 ret = -ENOMEM;
813 if (of_property_read_bool(i2c->dev.of_node, "maxim,interleave-mode")) {
814 max98927->interleave_mode = true;
816 if (!of_property_read_u32(i2c->dev.of_node, "interleave_mode",
819 max98927->interleave_mode = true;
823 max98927->regmap
825 if (IS_ERR(max98927->regmap)) {
826 ret = PTR_ERR(max98927->regmap);
827 dev_err(&i2c->dev,
832 max98927->reset_gpio = devm_gpiod_get_optional(&i2c->dev, "reset",
834 if (IS_ERR(max98927->reset_gpio)) {
835 ret = PTR_ERR(max98927->reset_gpio);
836 return dev_err_probe(&i2c->dev, ret, "failed to request GPIO reset pin");
839 if (max98927->reset_gpio) {
840 gpiod_set_value_cansleep(max98927->reset_gpio, 0);
846 ret = regmap_read(max98927->regmap, MAX98927_R01FF_REV_ID, ®);
848 dev_err(&i2c->dev,
852 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
854 /* voltage/current slot configuration */
858 ret = devm_snd_soc_register_component(&i2c->dev,
862 dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
871 if (max98927->reset_gpio)
872 gpiod_set_value_cansleep(max98927->reset_gpio, 1);