Lines Matching +full:current +full:- +full:limiter
1 // SPDX-License-Identifier: GPL-2.0
23 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
28 regmap_update_bits(max98373->regmap,
34 regmap_update_bits(max98373->regmap,
38 max98373->tdm_mode = false;
72 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
85 static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, -6350, 50, 1);
101 0, 1, TLV_DB_SCALE_ITEM(-3000, 500, 0),
102 2, 4, TLV_DB_SCALE_ITEM(-2200, 200, 0),
103 5, 6, TLV_DB_SCALE_ITEM(-1500, 300, 0),
104 7, 9, TLV_DB_SCALE_ITEM(-1000, 200, 0),
105 10, 13, TLV_DB_SCALE_ITEM(-500, 100, 0),
106 14, 15, TLV_DB_SCALE_ITEM(-100, 50, 0),
109 0, 15, TLV_DB_SCALE_ITEM(-1500, 100, 0),
113 0, 60, TLV_DB_SCALE_ITEM(-1500, 25, 0),
179 (struct soc_mixer_control *)kcontrol->private_value;
188 for (i = 0; i < max98373->cache_num; i++) {
189 if (mc->reg == max98373->cache[i].reg) {
190 ucontrol->value.integer.value[0] = max98373->cache[i].val;
291 SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
293 SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
295 SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
297 SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
299 /* Limiter */
300 SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
302 SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
304 SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
306 SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
307 SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
321 { "Current Sense", NULL, "VI Sense" },
330 ret = regmap_update_bits(max98373->regmap,
341 ret = regmap_read(max98373->regmap,
358 max98373_reset(max98373, component->dev);
361 regmap_write(max98373->regmap,
364 regmap_write(max98373->regmap,
368 regmap_write(max98373->regmap,
371 regmap_write(max98373->regmap,
375 regmap_write(max98373->regmap,
379 regmap_write(max98373->regmap,
382 /* voltage, current slot configuration */
383 regmap_write(max98373->regmap,
385 (max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
386 max98373->v_slot) & 0xFF);
387 if (max98373->v_slot < 8)
388 regmap_update_bits(max98373->regmap,
390 1 << max98373->v_slot, 0);
392 regmap_update_bits(max98373->regmap,
394 1 << (max98373->v_slot - 8), 0);
396 if (max98373->i_slot < 8)
397 regmap_update_bits(max98373->regmap,
399 1 << max98373->i_slot, 0);
401 regmap_update_bits(max98373->regmap,
403 1 << (max98373->i_slot - 8), 0);
406 regmap_write(max98373->regmap,
411 regmap_write(max98373->regmap,
413 max98373->spkfb_slot & 0xFF);
416 if (max98373->interleave_mode)
417 regmap_update_bits(max98373->regmap,
423 regmap_update_bits(max98373->regmap,
447 ret = pm_runtime_resume(component->dev);
448 if (ret < 0 && ret != -EACCES)
472 if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
473 max98373->v_slot = value & 0xF;
475 max98373->v_slot = 0;
477 if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
478 max98373->i_slot = value & 0xF;
480 max98373->i_slot = 1;
483 max98373->reset = devm_gpiod_get_optional(dev,
486 if (IS_ERR(max98373->reset)) {
488 PTR_ERR(max98373->reset));
493 if (max98373->reset) {
494 gpiod_set_consumer_name(max98373->reset ,"MAX98373_RESET");
495 gpiod_direction_output(max98373->reset, 1);
497 gpiod_direction_output(max98373->reset, 0);
501 if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
502 max98373->spkfb_slot = value & 0xF;
504 max98373->spkfb_slot = 2;