Lines Matching +full:switch +full:- +full:freq +full:- +full:select
1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
252 switch (reg) { in max98090_volatile_register()
265 switch (reg) { in max98090_readable_register()
279 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
283 dev_err(max98090->component->dev, in max98090_reset()
300 -600, 600, 0);
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
308 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
311 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
319 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
320 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
324 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
325 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
326 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
327 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
332 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
333 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
334 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
335 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
340 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
341 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
342 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
353 (struct soc_mixer_control *)kcontrol->private_value; in max98090_get_enab_tlv()
354 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_get_enab_tlv()
355 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_get_enab_tlv()
356 unsigned int *select; in max98090_get_enab_tlv() local
358 switch (mc->reg) { in max98090_get_enab_tlv()
360 select = &(max98090->pa1en); in max98090_get_enab_tlv()
363 select = &(max98090->pa2en); in max98090_get_enab_tlv()
366 select = &(max98090->sidetone); in max98090_get_enab_tlv()
369 return -EINVAL; in max98090_get_enab_tlv()
372 val = (val >> mc->shift) & mask; in max98090_get_enab_tlv()
376 val = val - 1; in max98090_get_enab_tlv()
377 *select = val; in max98090_get_enab_tlv()
380 val = *select; in max98090_get_enab_tlv()
383 ucontrol->value.integer.value[0] = val; in max98090_get_enab_tlv()
393 (struct soc_mixer_control *)kcontrol->private_value; in max98090_put_enab_tlv()
394 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_put_enab_tlv()
395 int sel_unchecked = ucontrol->value.integer.value[0]; in max98090_put_enab_tlv()
397 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_put_enab_tlv()
398 unsigned int *select; in max98090_put_enab_tlv() local
401 switch (mc->reg) { in max98090_put_enab_tlv()
403 select = &(max98090->pa1en); in max98090_put_enab_tlv()
406 select = &(max98090->pa2en); in max98090_put_enab_tlv()
409 select = &(max98090->sidetone); in max98090_put_enab_tlv()
412 return -EINVAL; in max98090_put_enab_tlv()
415 val = (val >> mc->shift) & mask; in max98090_put_enab_tlv()
417 if (sel_unchecked < 0 || sel_unchecked > mc->max) in max98090_put_enab_tlv()
418 return -EINVAL; in max98090_put_enab_tlv()
421 change = *select != sel; in max98090_put_enab_tlv()
422 *select = sel; in max98090_put_enab_tlv()
432 snd_soc_component_update_bits(component, mc->reg, in max98090_put_enab_tlv()
433 mask << mc->shift, in max98090_put_enab_tlv()
434 sel << mc->shift); in max98090_put_enab_tlv()
518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
604 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
606 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
608 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
671 SOC_SINGLE("Headphone Left Switch", M98090_REG_LEFT_HP_VOLUME,
673 SOC_SINGLE("Headphone Right Switch", M98090_REG_RIGHT_HP_VOLUME,
676 SOC_SINGLE("Speaker Left Switch", M98090_REG_LEFT_SPK_VOLUME,
678 SOC_SINGLE("Speaker Right Switch", M98090_REG_RIGHT_SPK_VOLUME,
681 SOC_SINGLE("Receiver Left Switch", M98090_REG_RCV_LOUTL_VOLUME,
683 SOC_SINGLE("Receiver Right Switch", M98090_REG_LOUTR_VOLUME,
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
694 SOC_SINGLE("Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
702 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
707 M98090_FLT_DMIC34HPF_NUM - 1, 0),
710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
725 SOC_SINGLE("DMIC34 Biquad Switch", M98090_REG_DSP_FILTER_ENABLE,
726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_micinput_event()
739 unsigned int val = snd_soc_component_read(component, w->reg); in max98090_micinput_event()
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { in max98090_micinput_event()
748 max98090->pa1en = val - 1; /* Update for volatile */ in max98090_micinput_event()
750 max98090->pa2en = val - 1; /* Update for volatile */ in max98090_micinput_event()
754 switch (event) { in max98090_micinput_event()
757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
758 val = max98090->pa1en + 1; in max98090_micinput_event()
760 val = max98090->pa2en + 1; in max98090_micinput_event()
767 return -EINVAL; in max98090_micinput_event()
770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, in max98090_micinput_event()
774 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, in max98090_micinput_event()
783 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_shdn_event()
787 max98090->shdn_pending = true; in max98090_shdn_event()
820 /* LINEA mixer switch */
822 SOC_DAPM_SINGLE("IN1 Switch", M98090_REG_LINE_INPUT_CONFIG,
824 SOC_DAPM_SINGLE("IN3 Switch", M98090_REG_LINE_INPUT_CONFIG,
826 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
828 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LINE_INPUT_CONFIG,
832 /* LINEB mixer switch */
834 SOC_DAPM_SINGLE("IN2 Switch", M98090_REG_LINE_INPUT_CONFIG,
836 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
838 SOC_DAPM_SINGLE("IN6 Switch", M98090_REG_LINE_INPUT_CONFIG,
840 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LINE_INPUT_CONFIG,
844 /* Left ADC mixer switch */
846 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_LEFT_ADC_MIXER,
848 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_LEFT_ADC_MIXER,
850 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_LEFT_ADC_MIXER,
852 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_ADC_MIXER,
854 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_ADC_MIXER,
856 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_ADC_MIXER,
858 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_ADC_MIXER,
862 /* Right ADC mixer switch */
864 SOC_DAPM_SINGLE("IN12 Switch", M98090_REG_RIGHT_ADC_MIXER,
866 SOC_DAPM_SINGLE("IN34 Switch", M98090_REG_RIGHT_ADC_MIXER,
868 SOC_DAPM_SINGLE("IN56 Switch", M98090_REG_RIGHT_ADC_MIXER,
870 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_ADC_MIXER,
872 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_ADC_MIXER,
874 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_ADC_MIXER,
876 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_ADC_MIXER,
936 /* Left speaker mixer switch */
939 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_SPK_MIXER,
941 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_SPK_MIXER,
943 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_SPK_MIXER,
945 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_SPK_MIXER,
947 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_SPK_MIXER,
949 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_SPK_MIXER,
953 /* Right speaker mixer switch */
956 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
958 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_SPK_MIXER,
960 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_SPK_MIXER,
962 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_SPK_MIXER,
964 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_SPK_MIXER,
966 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_SPK_MIXER,
970 /* Left headphone mixer switch */
972 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LEFT_HP_MIXER,
974 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LEFT_HP_MIXER,
976 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LEFT_HP_MIXER,
978 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LEFT_HP_MIXER,
980 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LEFT_HP_MIXER,
982 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LEFT_HP_MIXER,
986 /* Right headphone mixer switch */
988 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RIGHT_HP_MIXER,
990 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RIGHT_HP_MIXER,
992 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RIGHT_HP_MIXER,
994 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RIGHT_HP_MIXER,
996 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RIGHT_HP_MIXER,
998 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RIGHT_HP_MIXER,
1002 /* Left receiver mixer switch */
1004 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1006 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_RCV_LOUTL_MIXER,
1008 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_RCV_LOUTL_MIXER,
1010 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_RCV_LOUTL_MIXER,
1012 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_RCV_LOUTL_MIXER,
1014 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_RCV_LOUTL_MIXER,
1018 /* Right receiver mixer switch */
1020 SOC_DAPM_SINGLE("Left DAC Switch", M98090_REG_LOUTR_MIXER,
1022 SOC_DAPM_SINGLE("Right DAC Switch", M98090_REG_LOUTR_MIXER,
1024 SOC_DAPM_SINGLE("LINEA Switch", M98090_REG_LOUTR_MIXER,
1026 SOC_DAPM_SINGLE("LINEB Switch", M98090_REG_LOUTR_MIXER,
1028 SOC_DAPM_SINGLE("MIC1 Switch", M98090_REG_LOUTR_MIXER,
1030 SOC_DAPM_SINGLE("MIC2 Switch", M98090_REG_LOUTR_MIXER,
1269 {"Left ADC Mixer", "IN12 Switch", "IN12"},
1270 {"Left ADC Mixer", "IN34 Switch", "IN34"},
1271 {"Left ADC Mixer", "IN56 Switch", "IN56"},
1272 {"Left ADC Mixer", "LINEA Switch", "LINEA Input"},
1273 {"Left ADC Mixer", "LINEB Switch", "LINEB Input"},
1274 {"Left ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1275 {"Left ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1278 {"Right ADC Mixer", "IN12 Switch", "IN12"},
1279 {"Right ADC Mixer", "IN34 Switch", "IN34"},
1280 {"Right ADC Mixer", "IN56 Switch", "IN56"},
1281 {"Right ADC Mixer", "LINEA Switch", "LINEA Input"},
1282 {"Right ADC Mixer", "LINEB Switch", "LINEB Input"},
1283 {"Right ADC Mixer", "MIC1 Switch", "MIC1 Input"},
1284 {"Right ADC Mixer", "MIC2 Switch", "MIC2 Input"},
1287 {"LINEA Mixer", "IN1 Switch", "IN1"},
1288 {"LINEA Mixer", "IN3 Switch", "IN3"},
1289 {"LINEA Mixer", "IN5 Switch", "IN5"},
1290 {"LINEA Mixer", "IN34 Switch", "IN34"},
1293 {"LINEB Mixer", "IN2 Switch", "IN2"},
1294 {"LINEB Mixer", "IN4 Switch", "IN4"},
1295 {"LINEB Mixer", "IN6 Switch", "IN6"},
1296 {"LINEB Mixer", "IN56 Switch", "IN56"},
1347 {"Left Headphone Mixer", "Left DAC Switch", "DACL"},
1348 {"Left Headphone Mixer", "Right DAC Switch", "DACR"},
1349 {"Left Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1350 {"Left Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1351 {"Left Headphone Mixer", "LINEA Switch", "LINEA Input"},
1352 {"Left Headphone Mixer", "LINEB Switch", "LINEB Input"},
1355 {"Right Headphone Mixer", "Left DAC Switch", "DACL"},
1356 {"Right Headphone Mixer", "Right DAC Switch", "DACR"},
1357 {"Right Headphone Mixer", "MIC1 Switch", "MIC1 Input"},
1358 {"Right Headphone Mixer", "MIC2 Switch", "MIC2 Input"},
1359 {"Right Headphone Mixer", "LINEA Switch", "LINEA Input"},
1360 {"Right Headphone Mixer", "LINEB Switch", "LINEB Input"},
1363 {"Left Speaker Mixer", "Left DAC Switch", "DACL"},
1364 {"Left Speaker Mixer", "Right DAC Switch", "DACR"},
1365 {"Left Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1366 {"Left Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1367 {"Left Speaker Mixer", "LINEA Switch", "LINEA Input"},
1368 {"Left Speaker Mixer", "LINEB Switch", "LINEB Input"},
1371 {"Right Speaker Mixer", "Left DAC Switch", "DACL"},
1372 {"Right Speaker Mixer", "Right DAC Switch", "DACR"},
1373 {"Right Speaker Mixer", "MIC1 Switch", "MIC1 Input"},
1374 {"Right Speaker Mixer", "MIC2 Switch", "MIC2 Input"},
1375 {"Right Speaker Mixer", "LINEA Switch", "LINEA Input"},
1376 {"Right Speaker Mixer", "LINEB Switch", "LINEB Input"},
1379 {"Left Receiver Mixer", "Left DAC Switch", "DACL"},
1380 {"Left Receiver Mixer", "Right DAC Switch", "DACR"},
1381 {"Left Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1382 {"Left Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1383 {"Left Receiver Mixer", "LINEA Switch", "LINEA Input"},
1384 {"Left Receiver Mixer", "LINEB Switch", "LINEB Input"},
1387 {"Right Receiver Mixer", "Left DAC Switch", "DACL"},
1388 {"Right Receiver Mixer", "Right DAC Switch", "DACR"},
1389 {"Right Receiver Mixer", "MIC1 Switch", "MIC1 Input"},
1390 {"Right Receiver Mixer", "MIC2 Switch", "MIC2 Input"},
1391 {"Right Receiver Mixer", "LINEA Switch", "LINEA Input"},
1392 {"Right Receiver Mixer", "LINEB Switch", "LINEB Input"},
1444 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1455 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1498 if (!max98090->sysclk) { in max98090_configure_bclk()
1499 dev_err(component->dev, "No SYSCLK configured\n"); in max98090_configure_bclk()
1503 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1504 dev_err(component->dev, "No audio clocks configured\n"); in max98090_configure_bclk()
1516 if ((pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1517 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1518 dev_dbg(component->dev, in max98090_configure_bclk()
1533 if ((user_pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1534 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1535 dev_dbg(component->dev, in max98090_configure_bclk()
1537 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", in max98090_configure_bclk()
1572 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1573 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1574 do_div(ni, (unsigned long long int)max98090->sysclk); in max98090_configure_bclk()
1575 dev_info(component->dev, "No better method found\n"); in max98090_configure_bclk()
1576 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); in max98090_configure_bclk()
1585 struct snd_soc_component *component = codec_dai->component; in max98090_dai_set_fmt()
1590 max98090->dai_fmt = fmt; in max98090_dai_set_fmt()
1591 cdata = &max98090->dai[0]; in max98090_dai_set_fmt()
1593 if (fmt != cdata->fmt) { in max98090_dai_set_fmt()
1594 cdata->fmt = fmt; in max98090_dai_set_fmt()
1598 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { in max98090_dai_set_fmt()
1600 /* Set to consumer mode PLL - MAS mode off */ in max98090_dai_set_fmt()
1607 max98090->master = false; in max98090_dai_set_fmt()
1611 if (max98090->tdm_slots == 4) { in max98090_dai_set_fmt()
1615 } else if (max98090->tdm_slots == 3) { in max98090_dai_set_fmt()
1624 max98090->master = true; in max98090_dai_set_fmt()
1627 dev_err(component->dev, "DAI clock mode unsupported"); in max98090_dai_set_fmt()
1628 return -EINVAL; in max98090_dai_set_fmt()
1633 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { in max98090_dai_set_fmt()
1646 dev_err(component->dev, "DAI format unsupported"); in max98090_dai_set_fmt()
1647 return -EINVAL; in max98090_dai_set_fmt()
1650 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { in max98090_dai_set_fmt()
1663 dev_err(component->dev, "DAI invert mode unsupported"); in max98090_dai_set_fmt()
1664 return -EINVAL; in max98090_dai_set_fmt()
1681 regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT | in max98090_dai_set_fmt()
1682 max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT | in max98090_dai_set_fmt()
1695 struct snd_soc_component *component = codec_dai->component; in max98090_set_tdm_slot()
1699 return -EINVAL; in max98090_set_tdm_slot()
1702 return -EINVAL; in max98090_set_tdm_slot()
1705 return -EINVAL; in max98090_set_tdm_slot()
1708 return -EINVAL; in max98090_set_tdm_slot()
1710 max98090->tdm_slots = slots; in max98090_set_tdm_slot()
1711 max98090->tdm_lslot = ffs(rx_mask) - 1; in max98090_set_tdm_slot()
1712 max98090->tdm_rslot = fls(rx_mask) - 1; in max98090_set_tdm_slot()
1723 switch (level) { in max98090_set_bias_level()
1735 if (IS_ERR(max98090->mclk)) in max98090_set_bias_level()
1739 clk_disable_unprepare(max98090->mclk); in max98090_set_bias_level()
1741 ret = clk_prepare_enable(max98090->mclk); in max98090_set_bias_level()
1749 ret = regcache_sync(max98090->regmap); in max98090_set_bias_level()
1751 dev_err(component->dev, in max98090_set_bias_level()
1759 /* Set internal pull-up to lowest power mode */ in max98090_set_bias_level()
1762 regcache_mark_dirty(max98090->regmap); in max98090_set_bias_level()
1777 int freq; member
1782 static const struct dmic_table dmic_table[] = { /* One for each pclk freq. */
1786 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1787 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1788 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1789 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1790 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1791 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1797 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1798 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1799 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1800 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1801 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1802 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1808 { .freq = 2, .comp = { 7, 8, 3, 3, 3, 3 } },
1809 { .freq = 1, .comp = { 7, 8, 2, 2, 2, 2 } },
1810 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1811 { .freq = 0, .comp = { 7, 8, 6, 6, 6, 6 } },
1812 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1813 { .freq = 0, .comp = { 7, 8, 3, 3, 3, 3 } },
1819 { .freq = 2, .comp = { 7, 8, 1, 1, 1, 1 } },
1820 { .freq = 1, .comp = { 7, 8, 0, 0, 0, 0 } },
1821 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1822 { .freq = 0, .comp = { 7, 8, 4, 4, 5, 5 } },
1823 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1824 { .freq = 0, .comp = { 7, 8, 1, 1, 1, 1 } },
1830 { .freq = 2, .comp = { 0, 0, 0, 0, 0, 0 } },
1831 { .freq = 1, .comp = { 7, 8, 1, 1, 1, 1 } },
1832 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1833 { .freq = 0, .comp = { 7, 8, 2, 2, 3, 3 } },
1834 { .freq = 0, .comp = { 7, 8, 1, 1, 2, 2 } },
1835 { .freq = 0, .comp = { 7, 8, 5, 5, 6, 6 } },
1848 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); in max98090_find_divisor()
1870 m1 = pclk - dmic_table[i-1].pclk; in max98090_find_closest_pclk()
1871 m2 = dmic_table[i].pclk - pclk; in max98090_find_closest_pclk()
1873 return i - 1; in max98090_find_closest_pclk()
1879 return -EINVAL; in max98090_find_closest_pclk()
1897 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { in max98090_configure_dmic()
1902 dmic_freq = dmic_table[pclk_index].settings[micclk_index].freq; in max98090_configure_dmic()
1905 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, in max98090_configure_dmic()
1909 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, in max98090_configure_dmic()
1920 struct snd_soc_component *component = dai->component; in max98090_dai_startup()
1922 unsigned int fmt = max98090->dai_fmt; in max98090_dai_startup()
1924 /* Remove 24-bit format support if it is not in right justified mode. */ in max98090_dai_startup()
1926 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; in max98090_dai_startup()
1927 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); in max98090_dai_startup()
1936 struct snd_soc_component *component = dai->component; in max98090_dai_hw_params()
1940 cdata = &max98090->dai[0]; in max98090_dai_hw_params()
1941 max98090->bclk = snd_soc_params_to_bclk(params); in max98090_dai_hw_params()
1943 max98090->bclk *= 2; in max98090_dai_hw_params()
1945 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1947 switch (params_width(params)) { in max98090_dai_hw_params()
1953 return -EINVAL; in max98090_dai_hw_params()
1956 if (max98090->master) in max98090_dai_hw_params()
1959 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
1962 if (max98090->lrclk < 24000) in max98090_dai_hw_params()
1970 if (max98090->lrclk < 50000) in max98090_dai_hw_params()
1977 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, in max98090_dai_hw_params()
1978 max98090->lrclk); in max98090_dai_hw_params()
1987 int clk_id, unsigned int freq, int dir) in max98090_dai_set_sysclk() argument
1989 struct snd_soc_component *component = dai->component; in max98090_dai_set_sysclk()
1993 if (freq == max98090->sysclk) in max98090_dai_set_sysclk()
1996 if (!IS_ERR(max98090->mclk)) { in max98090_dai_set_sysclk()
1997 freq = clk_round_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
1998 clk_set_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2006 if ((freq >= 10000000) && (freq <= 20000000)) { in max98090_dai_set_sysclk()
2009 max98090->pclk = freq; in max98090_dai_set_sysclk()
2010 } else if ((freq > 20000000) && (freq <= 40000000)) { in max98090_dai_set_sysclk()
2013 max98090->pclk = freq >> 1; in max98090_dai_set_sysclk()
2014 } else if ((freq > 40000000) && (freq <= 60000000)) { in max98090_dai_set_sysclk()
2017 max98090->pclk = freq >> 2; in max98090_dai_set_sysclk()
2019 dev_err(component->dev, "Invalid master clock frequency\n"); in max98090_dai_set_sysclk()
2020 return -EINVAL; in max98090_dai_set_sysclk()
2023 max98090->sysclk = freq; in max98090_dai_set_sysclk()
2031 struct snd_soc_component *component = codec_dai->component; in max98090_dai_mute()
2044 struct snd_soc_component *component = dai->component; in max98090_dai_trigger()
2047 switch (cmd) { in max98090_dai_trigger()
2051 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2053 &max98090->pll_det_enable_work, in max98090_dai_trigger()
2059 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2060 schedule_work(&max98090->pll_det_disable_work); in max98090_dai_trigger()
2074 struct snd_soc_component *component = max98090->component; in max98090_pll_det_enable_work()
2083 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_pll_det_enable_work()
2089 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_pll_det_enable_work()
2093 &max98090->jack_work, in max98090_pll_det_enable_work()
2106 struct snd_soc_component *component = max98090->component; in max98090_pll_det_disable_work()
2108 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_pll_det_disable_work()
2117 struct snd_soc_component *component = max98090->component; in max98090_pll_work()
2124 dev_info_ratelimited(component->dev, "PLL unlocked\n"); in max98090_pll_work()
2156 struct snd_soc_component *component = max98090->component; in max98090_jack_work()
2161 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { in max98090_jack_work()
2178 switch (reg & (M98090_LSNS_MASK | M98090_JKSNS_MASK)) { in max98090_jack_work()
2180 dev_dbg(component->dev, "No Headset Detected\n"); in max98090_jack_work()
2182 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_jack_work()
2189 if (max98090->jack_state == in max98090_jack_work()
2192 dev_dbg(component->dev, in max98090_jack_work()
2209 dev_dbg(component->dev, "Headphone Detected\n"); in max98090_jack_work()
2211 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; in max98090_jack_work()
2218 dev_dbg(component->dev, "Headset Detected\n"); in max98090_jack_work()
2220 max98090->jack_state = M98090_JACK_STATE_HEADSET; in max98090_jack_work()
2227 dev_dbg(component->dev, "Unrecognized Jack Status\n"); in max98090_jack_work()
2231 snd_soc_jack_report(max98090->jack, status, in max98090_jack_work()
2238 struct snd_soc_component *component = max98090->component; in max98090_interrupt()
2247 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); in max98090_interrupt()
2249 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_interrupt()
2252 dev_err(component->dev, in max98090_interrupt()
2258 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); in max98090_interrupt()
2261 dev_err(component->dev, in max98090_interrupt()
2267 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", in max98090_interrupt()
2276 dev_err(component->dev, "M98090_CLD_MASK\n"); in max98090_interrupt()
2279 dev_dbg(component->dev, "M98090_SLD_MASK\n"); in max98090_interrupt()
2282 dev_dbg(component->dev, "M98090_ULK_MASK\n"); in max98090_interrupt()
2287 dev_dbg(component->dev, "M98090_JDET_MASK\n"); in max98090_interrupt()
2289 pm_wakeup_event(component->dev, 100); in max98090_interrupt()
2292 &max98090->jack_work, in max98090_interrupt()
2297 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); in max98090_interrupt()
2300 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); in max98090_interrupt()
2306 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2323 dev_dbg(component->dev, "max98090_mic_detect\n"); in max98090_mic_detect()
2325 max98090->jack = jack; in max98090_mic_detect()
2337 snd_soc_jack_report(max98090->jack, 0, in max98090_mic_detect()
2341 &max98090->jack_work, in max98090_mic_detect()
2390 dev_dbg(component->dev, "max98090_probe\n"); in max98090_probe()
2392 max98090->mclk = devm_clk_get(component->dev, "mclk"); in max98090_probe()
2393 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) in max98090_probe()
2394 return -EPROBE_DEFER; in max98090_probe()
2396 max98090->component = component; in max98090_probe()
2403 max98090->sysclk = (unsigned)-1; in max98090_probe()
2404 max98090->pclk = (unsigned)-1; in max98090_probe()
2405 max98090->master = false; in max98090_probe()
2407 cdata = &max98090->dai[0]; in max98090_probe()
2408 cdata->rate = (unsigned)-1; in max98090_probe()
2409 cdata->fmt = (unsigned)-1; in max98090_probe()
2411 max98090->lin_state = 0; in max98090_probe()
2412 max98090->pa1en = 0; in max98090_probe()
2413 max98090->pa2en = 0; in max98090_probe()
2415 max98090->tdm_lslot = 0; in max98090_probe()
2416 max98090->tdm_rslot = 1; in max98090_probe()
2420 dev_err(component->dev, "Failed to read device revision: %d\n", in max98090_probe()
2427 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); in max98090_probe()
2430 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); in max98090_probe()
2433 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); in max98090_probe()
2436 if (max98090->devtype != devtype) { in max98090_probe()
2437 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); in max98090_probe()
2438 max98090->devtype = devtype; in max98090_probe()
2441 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_probe()
2443 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); in max98090_probe()
2444 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, in max98090_probe()
2446 INIT_WORK(&max98090->pll_det_disable_work, in max98090_probe()
2475 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); in max98090_probe()
2478 dev_info(component->dev, "use default 2.8v micbias\n"); in max98090_probe()
2480 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); in max98090_probe()
2497 cancel_delayed_work_sync(&max98090->jack_work); in max98090_remove()
2498 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_remove()
2499 cancel_work_sync(&max98090->pll_det_disable_work); in max98090_remove()
2500 max98090->component = NULL; in max98090_remove()
2508 if (max98090->shdn_pending) { in max98090_seq_notifier()
2514 max98090->shdn_pending = false; in max98090_seq_notifier()
2554 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), in max98090_i2c_probe()
2557 return -ENOMEM; in max98090_i2c_probe()
2559 max98090->devtype = (uintptr_t)i2c_get_match_data(i2c); in max98090_i2c_probe()
2561 max98090->pdata = i2c->dev.platform_data; in max98090_i2c_probe()
2563 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", in max98090_i2c_probe()
2564 &max98090->dmic_freq); in max98090_i2c_probe()
2566 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; in max98090_i2c_probe()
2568 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); in max98090_i2c_probe()
2569 if (IS_ERR(max98090->regmap)) { in max98090_i2c_probe()
2570 ret = PTR_ERR(max98090->regmap); in max98090_i2c_probe()
2571 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in max98090_i2c_probe()
2575 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in max98090_i2c_probe()
2579 dev_err(&i2c->dev, "request_irq failed: %d\n", in max98090_i2c_probe()
2584 ret = devm_snd_soc_register_component(&i2c->dev, in max98090_i2c_probe()
2593 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); in max98090_i2c_shutdown()
2599 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2601 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2615 regcache_cache_only(max98090->regmap, false); in max98090_runtime_resume()
2619 regcache_sync(max98090->regmap); in max98090_runtime_resume()
2628 regcache_cache_only(max98090->regmap, true); in max98090_runtime_suspend()
2638 regcache_mark_dirty(max98090->regmap); in max98090_resume()
2643 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_resume()
2645 regcache_sync(max98090->regmap); in max98090_resume()