Lines Matching +full:oversampling +full:- +full:ratio
1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
279 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
283 dev_err(max98090->component->dev, in max98090_reset()
300 -600, 600, 0);
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
308 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
311 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
319 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
320 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
324 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
325 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
326 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
327 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
332 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
333 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
334 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
335 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
340 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
341 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
342 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
353 (struct soc_mixer_control *)kcontrol->private_value; in max98090_get_enab_tlv()
354 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_get_enab_tlv()
355 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_get_enab_tlv()
358 switch (mc->reg) { in max98090_get_enab_tlv()
360 select = &(max98090->pa1en); in max98090_get_enab_tlv()
363 select = &(max98090->pa2en); in max98090_get_enab_tlv()
366 select = &(max98090->sidetone); in max98090_get_enab_tlv()
369 return -EINVAL; in max98090_get_enab_tlv()
372 val = (val >> mc->shift) & mask; in max98090_get_enab_tlv()
376 val = val - 1; in max98090_get_enab_tlv()
383 ucontrol->value.integer.value[0] = val; in max98090_get_enab_tlv()
393 (struct soc_mixer_control *)kcontrol->private_value; in max98090_put_enab_tlv()
394 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_put_enab_tlv()
395 int sel_unchecked = ucontrol->value.integer.value[0]; in max98090_put_enab_tlv()
397 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_put_enab_tlv()
401 switch (mc->reg) { in max98090_put_enab_tlv()
403 select = &(max98090->pa1en); in max98090_put_enab_tlv()
406 select = &(max98090->pa2en); in max98090_put_enab_tlv()
409 select = &(max98090->sidetone); in max98090_put_enab_tlv()
412 return -EINVAL; in max98090_put_enab_tlv()
415 val = (val >> mc->shift) & mask; in max98090_put_enab_tlv()
417 if (sel_unchecked < 0 || sel_unchecked > mc->max) in max98090_put_enab_tlv()
418 return -EINVAL; in max98090_put_enab_tlv()
432 snd_soc_component_update_bits(component, mc->reg, in max98090_put_enab_tlv()
433 mask << mc->shift, in max98090_put_enab_tlv()
434 sel << mc->shift); in max98090_put_enab_tlv()
518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
573 SOC_ENUM("ADC Oversampling Rate", max98090_osr128_enum),
575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
624 SOC_ENUM("ALC Compression Ratio", max98090_alccmp_enum),
625 SOC_ENUM("ALC Expansion Ratio", max98090_drcexp_enum),
628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
702 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
707 M98090_FLT_DMIC34HPF_NUM - 1, 0),
710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_micinput_event()
739 unsigned int val = snd_soc_component_read(component, w->reg); in max98090_micinput_event()
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { in max98090_micinput_event()
748 max98090->pa1en = val - 1; /* Update for volatile */ in max98090_micinput_event()
750 max98090->pa2en = val - 1; /* Update for volatile */ in max98090_micinput_event()
757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
758 val = max98090->pa1en + 1; in max98090_micinput_event()
760 val = max98090->pa2en + 1; in max98090_micinput_event()
767 return -EINVAL; in max98090_micinput_event()
770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, in max98090_micinput_event()
774 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, in max98090_micinput_event()
783 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_shdn_event()
787 max98090->shdn_pending = true; in max98090_shdn_event()
1477 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1488 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1531 if (!max98090->sysclk) { in max98090_configure_bclk()
1532 dev_err(component->dev, "No SYSCLK configured\n"); in max98090_configure_bclk()
1536 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1537 dev_err(component->dev, "No audio clocks configured\n"); in max98090_configure_bclk()
1549 if ((pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1550 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1551 dev_dbg(component->dev, in max98090_configure_bclk()
1566 if ((user_pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1567 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1568 dev_dbg(component->dev, in max98090_configure_bclk()
1570 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", in max98090_configure_bclk()
1605 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1606 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1607 do_div(ni, (unsigned long long int)max98090->sysclk); in max98090_configure_bclk()
1608 dev_info(component->dev, "No better method found\n"); in max98090_configure_bclk()
1609 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); in max98090_configure_bclk()
1618 struct snd_soc_component *component = codec_dai->component; in max98090_dai_set_fmt()
1623 max98090->dai_fmt = fmt; in max98090_dai_set_fmt()
1624 cdata = &max98090->dai[0]; in max98090_dai_set_fmt()
1626 if (fmt != cdata->fmt) { in max98090_dai_set_fmt()
1627 cdata->fmt = fmt; in max98090_dai_set_fmt()
1633 /* Set to consumer mode PLL - MAS mode off */ in max98090_dai_set_fmt()
1640 max98090->master = false; in max98090_dai_set_fmt()
1644 if (max98090->tdm_slots == 4) { in max98090_dai_set_fmt()
1648 } else if (max98090->tdm_slots == 3) { in max98090_dai_set_fmt()
1657 max98090->master = true; in max98090_dai_set_fmt()
1660 dev_err(component->dev, "DAI clock mode unsupported"); in max98090_dai_set_fmt()
1661 return -EINVAL; in max98090_dai_set_fmt()
1679 dev_err(component->dev, "DAI format unsupported"); in max98090_dai_set_fmt()
1680 return -EINVAL; in max98090_dai_set_fmt()
1696 dev_err(component->dev, "DAI invert mode unsupported"); in max98090_dai_set_fmt()
1697 return -EINVAL; in max98090_dai_set_fmt()
1714 regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT | in max98090_dai_set_fmt()
1715 max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT | in max98090_dai_set_fmt()
1728 struct snd_soc_component *component = codec_dai->component; in max98090_set_tdm_slot()
1732 return -EINVAL; in max98090_set_tdm_slot()
1735 return -EINVAL; in max98090_set_tdm_slot()
1738 return -EINVAL; in max98090_set_tdm_slot()
1741 return -EINVAL; in max98090_set_tdm_slot()
1743 max98090->tdm_slots = slots; in max98090_set_tdm_slot()
1744 max98090->tdm_lslot = ffs(rx_mask) - 1; in max98090_set_tdm_slot()
1745 max98090->tdm_rslot = fls(rx_mask) - 1; in max98090_set_tdm_slot()
1769 if (IS_ERR(max98090->mclk)) in max98090_set_bias_level()
1773 clk_disable_unprepare(max98090->mclk); in max98090_set_bias_level()
1775 ret = clk_prepare_enable(max98090->mclk); in max98090_set_bias_level()
1783 ret = regcache_sync(max98090->regmap); in max98090_set_bias_level()
1785 dev_err(component->dev, in max98090_set_bias_level()
1793 /* Set internal pull-up to lowest power mode */ in max98090_set_bias_level()
1796 regcache_mark_dirty(max98090->regmap); in max98090_set_bias_level()
1882 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); in max98090_find_divisor()
1904 m1 = pclk - dmic_table[i-1].pclk; in max98090_find_closest_pclk()
1905 m2 = dmic_table[i].pclk - pclk; in max98090_find_closest_pclk()
1907 return i - 1; in max98090_find_closest_pclk()
1913 return -EINVAL; in max98090_find_closest_pclk()
1931 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { in max98090_configure_dmic()
1939 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, in max98090_configure_dmic()
1943 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, in max98090_configure_dmic()
1954 struct snd_soc_component *component = dai->component; in max98090_dai_startup()
1956 unsigned int fmt = max98090->dai_fmt; in max98090_dai_startup()
1958 /* Remove 24-bit format support if it is not in right justified mode. */ in max98090_dai_startup()
1960 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; in max98090_dai_startup()
1961 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); in max98090_dai_startup()
1970 struct snd_soc_component *component = dai->component; in max98090_dai_hw_params()
1974 cdata = &max98090->dai[0]; in max98090_dai_hw_params()
1975 max98090->bclk = snd_soc_params_to_bclk(params); in max98090_dai_hw_params()
1977 max98090->bclk *= 2; in max98090_dai_hw_params()
1979 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1987 return -EINVAL; in max98090_dai_hw_params()
1990 if (max98090->master) in max98090_dai_hw_params()
1993 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
1996 if (max98090->lrclk < 24000) in max98090_dai_hw_params()
2004 if (max98090->lrclk < 50000) in max98090_dai_hw_params()
2011 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, in max98090_dai_hw_params()
2012 max98090->lrclk); in max98090_dai_hw_params()
2023 struct snd_soc_component *component = dai->component; in max98090_dai_set_sysclk()
2027 if (freq == max98090->sysclk) in max98090_dai_set_sysclk()
2030 if (!IS_ERR(max98090->mclk)) { in max98090_dai_set_sysclk()
2031 freq = clk_round_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2032 clk_set_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2043 max98090->pclk = freq; in max98090_dai_set_sysclk()
2047 max98090->pclk = freq >> 1; in max98090_dai_set_sysclk()
2051 max98090->pclk = freq >> 2; in max98090_dai_set_sysclk()
2053 dev_err(component->dev, "Invalid master clock frequency\n"); in max98090_dai_set_sysclk()
2054 return -EINVAL; in max98090_dai_set_sysclk()
2057 max98090->sysclk = freq; in max98090_dai_set_sysclk()
2065 struct snd_soc_component *component = codec_dai->component; in max98090_dai_mute()
2078 struct snd_soc_component *component = dai->component; in max98090_dai_trigger()
2085 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2087 &max98090->pll_det_enable_work, in max98090_dai_trigger()
2093 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2094 schedule_work(&max98090->pll_det_disable_work); in max98090_dai_trigger()
2108 struct snd_soc_component *component = max98090->component; in max98090_pll_det_enable_work()
2117 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_pll_det_enable_work()
2123 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_pll_det_enable_work()
2127 &max98090->jack_work, in max98090_pll_det_enable_work()
2140 struct snd_soc_component *component = max98090->component; in max98090_pll_det_disable_work()
2142 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_pll_det_disable_work()
2151 struct snd_soc_component *component = max98090->component; in max98090_pll_work()
2158 dev_info_ratelimited(component->dev, "PLL unlocked\n"); in max98090_pll_work()
2190 struct snd_soc_component *component = max98090->component; in max98090_jack_work()
2195 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { in max98090_jack_work()
2214 dev_dbg(component->dev, "No Headset Detected\n"); in max98090_jack_work()
2216 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_jack_work()
2223 if (max98090->jack_state == in max98090_jack_work()
2226 dev_dbg(component->dev, in max98090_jack_work()
2243 dev_dbg(component->dev, "Headphone Detected\n"); in max98090_jack_work()
2245 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; in max98090_jack_work()
2252 dev_dbg(component->dev, "Headset Detected\n"); in max98090_jack_work()
2254 max98090->jack_state = M98090_JACK_STATE_HEADSET; in max98090_jack_work()
2261 dev_dbg(component->dev, "Unrecognized Jack Status\n"); in max98090_jack_work()
2265 snd_soc_jack_report(max98090->jack, status, in max98090_jack_work()
2272 struct snd_soc_component *component = max98090->component; in max98090_interrupt()
2281 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); in max98090_interrupt()
2283 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_interrupt()
2286 dev_err(component->dev, in max98090_interrupt()
2292 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); in max98090_interrupt()
2295 dev_err(component->dev, in max98090_interrupt()
2301 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", in max98090_interrupt()
2310 dev_err(component->dev, "M98090_CLD_MASK\n"); in max98090_interrupt()
2313 dev_dbg(component->dev, "M98090_SLD_MASK\n"); in max98090_interrupt()
2316 dev_dbg(component->dev, "M98090_ULK_MASK\n"); in max98090_interrupt()
2321 dev_dbg(component->dev, "M98090_JDET_MASK\n"); in max98090_interrupt()
2323 pm_wakeup_event(component->dev, 100); in max98090_interrupt()
2326 &max98090->jack_work, in max98090_interrupt()
2331 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); in max98090_interrupt()
2334 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); in max98090_interrupt()
2340 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2357 dev_dbg(component->dev, "max98090_mic_detect\n"); in max98090_mic_detect()
2359 max98090->jack = jack; in max98090_mic_detect()
2371 snd_soc_jack_report(max98090->jack, 0, in max98090_mic_detect()
2375 &max98090->jack_work, in max98090_mic_detect()
2424 dev_dbg(component->dev, "max98090_probe\n"); in max98090_probe()
2426 max98090->mclk = devm_clk_get(component->dev, "mclk"); in max98090_probe()
2427 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) in max98090_probe()
2428 return -EPROBE_DEFER; in max98090_probe()
2430 max98090->component = component; in max98090_probe()
2437 max98090->sysclk = (unsigned)-1; in max98090_probe()
2438 max98090->pclk = (unsigned)-1; in max98090_probe()
2439 max98090->master = false; in max98090_probe()
2441 cdata = &max98090->dai[0]; in max98090_probe()
2442 cdata->rate = (unsigned)-1; in max98090_probe()
2443 cdata->fmt = (unsigned)-1; in max98090_probe()
2445 max98090->lin_state = 0; in max98090_probe()
2446 max98090->pa1en = 0; in max98090_probe()
2447 max98090->pa2en = 0; in max98090_probe()
2449 max98090->tdm_lslot = 0; in max98090_probe()
2450 max98090->tdm_rslot = 1; in max98090_probe()
2454 dev_err(component->dev, "Failed to read device revision: %d\n", in max98090_probe()
2461 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); in max98090_probe()
2464 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); in max98090_probe()
2467 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); in max98090_probe()
2470 if (max98090->devtype != devtype) { in max98090_probe()
2471 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); in max98090_probe()
2472 max98090->devtype = devtype; in max98090_probe()
2475 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_probe()
2477 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); in max98090_probe()
2478 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, in max98090_probe()
2480 INIT_WORK(&max98090->pll_det_disable_work, in max98090_probe()
2509 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); in max98090_probe()
2512 dev_info(component->dev, "use default 2.8v micbias\n"); in max98090_probe()
2514 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); in max98090_probe()
2531 cancel_delayed_work_sync(&max98090->jack_work); in max98090_remove()
2532 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_remove()
2533 cancel_work_sync(&max98090->pll_det_disable_work); in max98090_remove()
2534 max98090->component = NULL; in max98090_remove()
2542 if (max98090->shdn_pending) { in max98090_seq_notifier()
2548 max98090->shdn_pending = false; in max98090_seq_notifier()
2588 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), in max98090_i2c_probe()
2591 return -ENOMEM; in max98090_i2c_probe()
2593 max98090->devtype = (uintptr_t)i2c_get_match_data(i2c); in max98090_i2c_probe()
2595 max98090->pdata = i2c->dev.platform_data; in max98090_i2c_probe()
2597 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", in max98090_i2c_probe()
2598 &max98090->dmic_freq); in max98090_i2c_probe()
2600 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; in max98090_i2c_probe()
2602 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); in max98090_i2c_probe()
2603 if (IS_ERR(max98090->regmap)) { in max98090_i2c_probe()
2604 ret = PTR_ERR(max98090->regmap); in max98090_i2c_probe()
2605 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in max98090_i2c_probe()
2609 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in max98090_i2c_probe()
2613 dev_err(&i2c->dev, "request_irq failed: %d\n", in max98090_i2c_probe()
2618 ret = devm_snd_soc_register_component(&i2c->dev, in max98090_i2c_probe()
2627 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); in max98090_i2c_shutdown()
2633 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2635 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2649 regcache_cache_only(max98090->regmap, false); in max98090_runtime_resume()
2653 regcache_sync(max98090->regmap); in max98090_runtime_resume()
2662 regcache_cache_only(max98090->regmap, true); in max98090_runtime_suspend()
2672 regcache_mark_dirty(max98090->regmap); in max98090_resume()
2677 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_resume()
2679 regcache_sync(max98090->regmap); in max98090_resume()