Lines Matching +full:out +full:- +full:of +full:- +full:band
1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
11 #include <linux/of.h>
99 { 0x46, 0x00 }, /* 46 Equalizer Band 1 Coefficient B0 */
100 { 0x47, 0x00 }, /* 47 Equalizer Band 1 Coefficient B0 */
101 { 0x48, 0x00 }, /* 48 Equalizer Band 1 Coefficient B0 */
102 { 0x49, 0x00 }, /* 49 Equalizer Band 1 Coefficient B1 */
103 { 0x4A, 0x00 }, /* 4A Equalizer Band 1 Coefficient B1 */
104 { 0x4B, 0x00 }, /* 4B Equalizer Band 1 Coefficient B1 */
105 { 0x4C, 0x00 }, /* 4C Equalizer Band 1 Coefficient B2 */
106 { 0x4D, 0x00 }, /* 4D Equalizer Band 1 Coefficient B2 */
107 { 0x4E, 0x00 }, /* 4E Equalizer Band 1 Coefficient B2 */
108 { 0x4F, 0x00 }, /* 4F Equalizer Band 1 Coefficient A1 */
110 { 0x50, 0x00 }, /* 50 Equalizer Band 1 Coefficient A1 */
111 { 0x51, 0x00 }, /* 51 Equalizer Band 1 Coefficient A1 */
112 { 0x52, 0x00 }, /* 52 Equalizer Band 1 Coefficient A2 */
113 { 0x53, 0x00 }, /* 53 Equalizer Band 1 Coefficient A2 */
114 { 0x54, 0x00 }, /* 54 Equalizer Band 1 Coefficient A2 */
115 { 0x55, 0x00 }, /* 55 Equalizer Band 2 Coefficient B0 */
116 { 0x56, 0x00 }, /* 56 Equalizer Band 2 Coefficient B0 */
117 { 0x57, 0x00 }, /* 57 Equalizer Band 2 Coefficient B0 */
118 { 0x58, 0x00 }, /* 58 Equalizer Band 2 Coefficient B1 */
119 { 0x59, 0x00 }, /* 59 Equalizer Band 2 Coefficient B1 */
120 { 0x5A, 0x00 }, /* 5A Equalizer Band 2 Coefficient B1 */
121 { 0x5B, 0x00 }, /* 5B Equalizer Band 2 Coefficient B2 */
122 { 0x5C, 0x00 }, /* 5C Equalizer Band 2 Coefficient B2 */
123 { 0x5D, 0x00 }, /* 5D Equalizer Band 2 Coefficient B2 */
124 { 0x5E, 0x00 }, /* 5E Equalizer Band 2 Coefficient A1 */
125 { 0x5F, 0x00 }, /* 5F Equalizer Band 2 Coefficient A1 */
127 { 0x60, 0x00 }, /* 60 Equalizer Band 2 Coefficient A1 */
128 { 0x61, 0x00 }, /* 61 Equalizer Band 2 Coefficient A2 */
129 { 0x62, 0x00 }, /* 62 Equalizer Band 2 Coefficient A2 */
130 { 0x63, 0x00 }, /* 63 Equalizer Band 2 Coefficient A2 */
131 { 0x64, 0x00 }, /* 64 Equalizer Band 3 Coefficient B0 */
132 { 0x65, 0x00 }, /* 65 Equalizer Band 3 Coefficient B0 */
133 { 0x66, 0x00 }, /* 66 Equalizer Band 3 Coefficient B0 */
134 { 0x67, 0x00 }, /* 67 Equalizer Band 3 Coefficient B1 */
135 { 0x68, 0x00 }, /* 68 Equalizer Band 3 Coefficient B1 */
136 { 0x69, 0x00 }, /* 69 Equalizer Band 3 Coefficient B1 */
137 { 0x6A, 0x00 }, /* 6A Equalizer Band 3 Coefficient B2 */
138 { 0x6B, 0x00 }, /* 6B Equalizer Band 3 Coefficient B2 */
139 { 0x6C, 0x00 }, /* 6C Equalizer Band 3 Coefficient B2 */
140 { 0x6D, 0x00 }, /* 6D Equalizer Band 3 Coefficient A1 */
141 { 0x6E, 0x00 }, /* 6E Equalizer Band 3 Coefficient A1 */
142 { 0x6F, 0x00 }, /* 6F Equalizer Band 3 Coefficient A1 */
144 { 0x70, 0x00 }, /* 70 Equalizer Band 3 Coefficient A2 */
145 { 0x71, 0x00 }, /* 71 Equalizer Band 3 Coefficient A2 */
146 { 0x72, 0x00 }, /* 72 Equalizer Band 3 Coefficient A2 */
147 { 0x73, 0x00 }, /* 73 Equalizer Band 4 Coefficient B0 */
148 { 0x74, 0x00 }, /* 74 Equalizer Band 4 Coefficient B0 */
149 { 0x75, 0x00 }, /* 75 Equalizer Band 4 Coefficient B0 */
150 { 0x76, 0x00 }, /* 76 Equalizer Band 4 Coefficient B1 */
151 { 0x77, 0x00 }, /* 77 Equalizer Band 4 Coefficient B1 */
152 { 0x78, 0x00 }, /* 78 Equalizer Band 4 Coefficient B1 */
153 { 0x79, 0x00 }, /* 79 Equalizer Band 4 Coefficient B2 */
154 { 0x7A, 0x00 }, /* 7A Equalizer Band 4 Coefficient B2 */
155 { 0x7B, 0x00 }, /* 7B Equalizer Band 4 Coefficient B2 */
156 { 0x7C, 0x00 }, /* 7C Equalizer Band 4 Coefficient A1 */
157 { 0x7D, 0x00 }, /* 7D Equalizer Band 4 Coefficient A1 */
158 { 0x7E, 0x00 }, /* 7E Equalizer Band 4 Coefficient A1 */
159 { 0x7F, 0x00 }, /* 7F Equalizer Band 4 Coefficient A2 */
161 { 0x80, 0x00 }, /* 80 Equalizer Band 4 Coefficient A2 */
162 { 0x81, 0x00 }, /* 81 Equalizer Band 4 Coefficient A2 */
163 { 0x82, 0x00 }, /* 82 Equalizer Band 5 Coefficient B0 */
164 { 0x83, 0x00 }, /* 83 Equalizer Band 5 Coefficient B0 */
165 { 0x84, 0x00 }, /* 84 Equalizer Band 5 Coefficient B0 */
166 { 0x85, 0x00 }, /* 85 Equalizer Band 5 Coefficient B1 */
167 { 0x86, 0x00 }, /* 86 Equalizer Band 5 Coefficient B1 */
168 { 0x87, 0x00 }, /* 87 Equalizer Band 5 Coefficient B1 */
169 { 0x88, 0x00 }, /* 88 Equalizer Band 5 Coefficient B2 */
170 { 0x89, 0x00 }, /* 89 Equalizer Band 5 Coefficient B2 */
171 { 0x8A, 0x00 }, /* 8A Equalizer Band 5 Coefficient B2 */
172 { 0x8B, 0x00 }, /* 8B Equalizer Band 5 Coefficient A1 */
173 { 0x8C, 0x00 }, /* 8C Equalizer Band 5 Coefficient A1 */
174 { 0x8D, 0x00 }, /* 8D Equalizer Band 5 Coefficient A1 */
175 { 0x8E, 0x00 }, /* 8E Equalizer Band 5 Coefficient A2 */
176 { 0x8F, 0x00 }, /* 8F Equalizer Band 5 Coefficient A2 */
178 { 0x90, 0x00 }, /* 90 Equalizer Band 5 Coefficient A2 */
179 { 0x91, 0x00 }, /* 91 Equalizer Band 6 Coefficient B0 */
180 { 0x92, 0x00 }, /* 92 Equalizer Band 6 Coefficient B0 */
181 { 0x93, 0x00 }, /* 93 Equalizer Band 6 Coefficient B0 */
182 { 0x94, 0x00 }, /* 94 Equalizer Band 6 Coefficient B1 */
183 { 0x95, 0x00 }, /* 95 Equalizer Band 6 Coefficient B1 */
184 { 0x96, 0x00 }, /* 96 Equalizer Band 6 Coefficient B1 */
185 { 0x97, 0x00 }, /* 97 Equalizer Band 6 Coefficient B2 */
186 { 0x98, 0x00 }, /* 98 Equalizer Band 6 Coefficient B2 */
187 { 0x99, 0x00 }, /* 99 Equalizer Band 6 Coefficient B2 */
188 { 0x9A, 0x00 }, /* 9A Equalizer Band 6 Coefficient A1 */
189 { 0x9B, 0x00 }, /* 9B Equalizer Band 6 Coefficient A1 */
190 { 0x9C, 0x00 }, /* 9C Equalizer Band 6 Coefficient A1 */
191 { 0x9D, 0x00 }, /* 9D Equalizer Band 6 Coefficient A2 */
192 { 0x9E, 0x00 }, /* 9E Equalizer Band 6 Coefficient A2 */
193 { 0x9F, 0x00 }, /* 9F Equalizer Band 6 Coefficient A2 */
195 { 0xA0, 0x00 }, /* A0 Equalizer Band 7 Coefficient B0 */
196 { 0xA1, 0x00 }, /* A1 Equalizer Band 7 Coefficient B0 */
197 { 0xA2, 0x00 }, /* A2 Equalizer Band 7 Coefficient B0 */
198 { 0xA3, 0x00 }, /* A3 Equalizer Band 7 Coefficient B1 */
199 { 0xA4, 0x00 }, /* A4 Equalizer Band 7 Coefficient B1 */
200 { 0xA5, 0x00 }, /* A5 Equalizer Band 7 Coefficient B1 */
201 { 0xA6, 0x00 }, /* A6 Equalizer Band 7 Coefficient B2 */
202 { 0xA7, 0x00 }, /* A7 Equalizer Band 7 Coefficient B2 */
203 { 0xA8, 0x00 }, /* A8 Equalizer Band 7 Coefficient B2 */
204 { 0xA9, 0x00 }, /* A9 Equalizer Band 7 Coefficient A1 */
205 { 0xAA, 0x00 }, /* AA Equalizer Band 7 Coefficient A1 */
206 { 0xAB, 0x00 }, /* AB Equalizer Band 7 Coefficient A1 */
207 { 0xAC, 0x00 }, /* AC Equalizer Band 7 Coefficient A2 */
208 { 0xAD, 0x00 }, /* AD Equalizer Band 7 Coefficient A2 */
209 { 0xAE, 0x00 }, /* AE Equalizer Band 7 Coefficient A2 */
279 /* Reset the codec by writing to this write-only reset register */ in max98090_reset()
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET, in max98090_reset()
283 dev_err(max98090->component->dev, in max98090_reset()
300 -600, 600, 0);
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
308 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
311 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
319 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
320 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
324 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
325 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
326 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
327 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
332 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
333 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
334 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
335 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
340 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
341 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
342 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
353 (struct soc_mixer_control *)kcontrol->private_value; in max98090_get_enab_tlv()
354 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_get_enab_tlv()
355 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_get_enab_tlv()
358 switch (mc->reg) { in max98090_get_enab_tlv()
360 select = &(max98090->pa1en); in max98090_get_enab_tlv()
363 select = &(max98090->pa2en); in max98090_get_enab_tlv()
366 select = &(max98090->sidetone); in max98090_get_enab_tlv()
369 return -EINVAL; in max98090_get_enab_tlv()
372 val = (val >> mc->shift) & mask; in max98090_get_enab_tlv()
376 val = val - 1; in max98090_get_enab_tlv()
383 ucontrol->value.integer.value[0] = val; in max98090_get_enab_tlv()
393 (struct soc_mixer_control *)kcontrol->private_value; in max98090_put_enab_tlv()
394 unsigned int mask = (1 << fls(mc->max)) - 1; in max98090_put_enab_tlv()
395 int sel_unchecked = ucontrol->value.integer.value[0]; in max98090_put_enab_tlv()
397 unsigned int val = snd_soc_component_read(component, mc->reg); in max98090_put_enab_tlv()
401 switch (mc->reg) { in max98090_put_enab_tlv()
403 select = &(max98090->pa1en); in max98090_put_enab_tlv()
406 select = &(max98090->pa2en); in max98090_put_enab_tlv()
409 select = &(max98090->sidetone); in max98090_put_enab_tlv()
412 return -EINVAL; in max98090_put_enab_tlv()
415 val = (val >> mc->shift) & mask; in max98090_put_enab_tlv()
417 if (sel_unchecked < 0 || sel_unchecked > mc->max) in max98090_put_enab_tlv()
418 return -EINVAL; in max98090_put_enab_tlv()
432 snd_soc_component_update_bits(component, mc->reg, in max98090_put_enab_tlv()
433 mask << mc->shift, in max98090_put_enab_tlv()
434 sel << mc->shift); in max98090_put_enab_tlv()
518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
604 SOC_SINGLE("Digital EQ 3 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
606 SOC_SINGLE("Digital EQ 5 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
608 SOC_SINGLE("Digital EQ 7 Band Switch", M98090_REG_DSP_FILTER_ENABLE,
609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
702 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
707 M98090_FLT_DMIC34HPF_NUM - 1, 0),
710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_micinput_event()
739 unsigned int val = snd_soc_component_read(component, w->reg); in max98090_micinput_event()
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) { in max98090_micinput_event()
748 max98090->pa1en = val - 1; /* Update for volatile */ in max98090_micinput_event()
750 max98090->pa2en = val - 1; /* Update for volatile */ in max98090_micinput_event()
757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
758 val = max98090->pa1en + 1; in max98090_micinput_event()
760 val = max98090->pa2en + 1; in max98090_micinput_event()
767 return -EINVAL; in max98090_micinput_event()
770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) in max98090_micinput_event()
771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK, in max98090_micinput_event()
774 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK, in max98090_micinput_event()
783 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in max98090_shdn_event()
787 max98090->shdn_pending = true; in max98090_shdn_event()
1098 * Note: Sysclk and misc power supplies are taken care of by SHDN
1209 SND_SOC_DAPM_PGA("HP Left Out", M98090_REG_OUTPUT_ENABLE,
1211 SND_SOC_DAPM_PGA("HP Right Out", M98090_REG_OUTPUT_ENABLE,
1214 SND_SOC_DAPM_PGA("SPK Left Out", M98090_REG_OUTPUT_ENABLE,
1216 SND_SOC_DAPM_PGA("SPK Right Out", M98090_REG_OUTPUT_ENABLE,
1219 SND_SOC_DAPM_PGA("RCV Left Out", M98090_REG_OUTPUT_ENABLE,
1221 SND_SOC_DAPM_PGA("RCV Right Out", M98090_REG_OUTPUT_ENABLE,
1396 {"HP Left Out", NULL, "DACL"},
1397 {"HP Left Out", NULL, "MIXHPLSEL Mux"},
1405 {"HP Right Out", NULL, "DACR"},
1406 {"HP Right Out", NULL, "MIXHPRSEL Mux"},
1408 {"SPK Left Out", NULL, "Left Speaker Mixer"},
1409 {"SPK Right Out", NULL, "Right Speaker Mixer"},
1410 {"RCV Left Out", NULL, "Left Receiver Mixer"},
1414 {"RCV Right Out", NULL, "LINMOD Mux"},
1416 {"HPL", NULL, "HP Left Out"},
1417 {"HPR", NULL, "HP Right Out"},
1418 {"SPKL", NULL, "SPK Left Out"},
1419 {"SPKR", NULL, "SPK Right Out"},
1420 {"RCVL", NULL, "RCV Left Out"},
1421 {"RCVR", NULL, "RCV Right Out"},
1440 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1451 if (max98090->devtype == MAX98091) { in max98090_add_widgets()
1494 if (!max98090->sysclk) { in max98090_configure_bclk()
1495 dev_err(component->dev, "No SYSCLK configured\n"); in max98090_configure_bclk()
1499 if (!max98090->bclk || !max98090->lrclk) { in max98090_configure_bclk()
1500 dev_err(component->dev, "No audio clocks configured\n"); in max98090_configure_bclk()
1512 if ((pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1513 (lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1514 dev_dbg(component->dev, in max98090_configure_bclk()
1529 if ((user_pclk_rates[i] == max98090->sysclk) && in max98090_configure_bclk()
1530 (user_lrclk_rates[i] == max98090->lrclk)) { in max98090_configure_bclk()
1531 dev_dbg(component->dev, in max98090_configure_bclk()
1533 dev_dbg(component->dev, "i %d ni %lld mi %lld\n", in max98090_configure_bclk()
1568 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL) in max98090_configure_bclk()
1569 * (unsigned long long int)max98090->lrclk; in max98090_configure_bclk()
1570 do_div(ni, (unsigned long long int)max98090->sysclk); in max98090_configure_bclk()
1571 dev_info(component->dev, "No better method found\n"); in max98090_configure_bclk()
1572 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni); in max98090_configure_bclk()
1581 struct snd_soc_component *component = codec_dai->component; in max98090_dai_set_fmt()
1586 max98090->dai_fmt = fmt; in max98090_dai_set_fmt()
1587 cdata = &max98090->dai[0]; in max98090_dai_set_fmt()
1589 if (fmt != cdata->fmt) { in max98090_dai_set_fmt()
1590 cdata->fmt = fmt; in max98090_dai_set_fmt()
1596 /* Set to consumer mode PLL - MAS mode off */ in max98090_dai_set_fmt()
1603 max98090->master = false; in max98090_dai_set_fmt()
1607 if (max98090->tdm_slots == 4) { in max98090_dai_set_fmt()
1611 } else if (max98090->tdm_slots == 3) { in max98090_dai_set_fmt()
1620 max98090->master = true; in max98090_dai_set_fmt()
1623 dev_err(component->dev, "DAI clock mode unsupported"); in max98090_dai_set_fmt()
1624 return -EINVAL; in max98090_dai_set_fmt()
1642 dev_err(component->dev, "DAI format unsupported"); in max98090_dai_set_fmt()
1643 return -EINVAL; in max98090_dai_set_fmt()
1659 dev_err(component->dev, "DAI invert mode unsupported"); in max98090_dai_set_fmt()
1660 return -EINVAL; in max98090_dai_set_fmt()
1666 * seen for the case of TDM mode. The remaining cases have in max98090_dai_set_fmt()
1677 regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT | in max98090_dai_set_fmt()
1678 max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT | in max98090_dai_set_fmt()
1691 struct snd_soc_component *component = codec_dai->component; in max98090_set_tdm_slot()
1695 return -EINVAL; in max98090_set_tdm_slot()
1698 return -EINVAL; in max98090_set_tdm_slot()
1701 return -EINVAL; in max98090_set_tdm_slot()
1704 return -EINVAL; in max98090_set_tdm_slot()
1706 max98090->tdm_slots = slots; in max98090_set_tdm_slot()
1707 max98090->tdm_lslot = ffs(rx_mask) - 1; in max98090_set_tdm_slot()
1708 max98090->tdm_rslot = fls(rx_mask) - 1; in max98090_set_tdm_slot()
1731 if (IS_ERR(max98090->mclk)) in max98090_set_bias_level()
1735 clk_disable_unprepare(max98090->mclk); in max98090_set_bias_level()
1737 ret = clk_prepare_enable(max98090->mclk); in max98090_set_bias_level()
1745 ret = regcache_sync(max98090->regmap); in max98090_set_bias_level()
1747 dev_err(component->dev, in max98090_set_bias_level()
1755 /* Set internal pull-up to lowest power mode */ in max98090_set_bias_level()
1758 regcache_mark_dirty(max98090->regmap); in max98090_set_bias_level()
1844 test_diff = abs(target_freq - (pclk / dmic_divisors[i])); in max98090_find_divisor()
1866 m1 = pclk - dmic_table[i-1].pclk; in max98090_find_closest_pclk()
1867 m2 = dmic_table[i].pclk - pclk; in max98090_find_closest_pclk()
1869 return i - 1; in max98090_find_closest_pclk()
1875 return -EINVAL; in max98090_find_closest_pclk()
1893 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) { in max98090_configure_dmic()
1901 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE, in max98090_configure_dmic()
1905 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG, in max98090_configure_dmic()
1916 struct snd_soc_component *component = dai->component; in max98090_dai_startup()
1918 unsigned int fmt = max98090->dai_fmt; in max98090_dai_startup()
1920 /* Remove 24-bit format support if it is not in right justified mode. */ in max98090_dai_startup()
1922 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE; in max98090_dai_startup()
1923 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16); in max98090_dai_startup()
1932 struct snd_soc_component *component = dai->component; in max98090_dai_hw_params()
1936 cdata = &max98090->dai[0]; in max98090_dai_hw_params()
1937 max98090->bclk = snd_soc_params_to_bclk(params); in max98090_dai_hw_params()
1939 max98090->bclk *= 2; in max98090_dai_hw_params()
1941 max98090->lrclk = params_rate(params); in max98090_dai_hw_params()
1949 return -EINVAL; in max98090_dai_hw_params()
1952 if (max98090->master) in max98090_dai_hw_params()
1955 cdata->rate = max98090->lrclk; in max98090_dai_hw_params()
1958 if (max98090->lrclk < 24000) in max98090_dai_hw_params()
1966 if (max98090->lrclk < 50000) in max98090_dai_hw_params()
1973 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk, in max98090_dai_hw_params()
1974 max98090->lrclk); in max98090_dai_hw_params()
1985 struct snd_soc_component *component = dai->component; in max98090_dai_set_sysclk()
1989 if (freq == max98090->sysclk) in max98090_dai_set_sysclk()
1992 if (!IS_ERR(max98090->mclk)) { in max98090_dai_set_sysclk()
1993 freq = clk_round_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
1994 clk_set_rate(max98090->mclk, freq); in max98090_dai_set_sysclk()
2005 max98090->pclk = freq; in max98090_dai_set_sysclk()
2009 max98090->pclk = freq >> 1; in max98090_dai_set_sysclk()
2013 max98090->pclk = freq >> 2; in max98090_dai_set_sysclk()
2015 dev_err(component->dev, "Invalid master clock frequency\n"); in max98090_dai_set_sysclk()
2016 return -EINVAL; in max98090_dai_set_sysclk()
2019 max98090->sysclk = freq; in max98090_dai_set_sysclk()
2027 struct snd_soc_component *component = codec_dai->component; in max98090_dai_mute()
2040 struct snd_soc_component *component = dai->component; in max98090_dai_trigger()
2047 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2049 &max98090->pll_det_enable_work, in max98090_dai_trigger()
2055 if (!max98090->master && snd_soc_dai_active(dai) == 1) in max98090_dai_trigger()
2056 schedule_work(&max98090->pll_det_disable_work); in max98090_dai_trigger()
2070 struct snd_soc_component *component = max98090->component; in max98090_pll_det_enable_work()
2079 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_pll_det_enable_work()
2085 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_pll_det_enable_work()
2089 &max98090->jack_work, in max98090_pll_det_enable_work()
2102 struct snd_soc_component *component = max98090->component; in max98090_pll_det_disable_work()
2104 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_pll_det_disable_work()
2113 struct snd_soc_component *component = max98090->component; in max98090_pll_work()
2120 dev_info_ratelimited(component->dev, "PLL unlocked\n"); in max98090_pll_work()
2152 struct snd_soc_component *component = max98090->component; in max98090_jack_work()
2157 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) { in max98090_jack_work()
2176 dev_dbg(component->dev, "No Headset Detected\n"); in max98090_jack_work()
2178 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_jack_work()
2185 if (max98090->jack_state == in max98090_jack_work()
2188 dev_dbg(component->dev, in max98090_jack_work()
2205 dev_dbg(component->dev, "Headphone Detected\n"); in max98090_jack_work()
2207 max98090->jack_state = M98090_JACK_STATE_HEADPHONE; in max98090_jack_work()
2214 dev_dbg(component->dev, "Headset Detected\n"); in max98090_jack_work()
2216 max98090->jack_state = M98090_JACK_STATE_HEADSET; in max98090_jack_work()
2223 dev_dbg(component->dev, "Unrecognized Jack Status\n"); in max98090_jack_work()
2227 snd_soc_jack_report(max98090->jack, status, in max98090_jack_work()
2234 struct snd_soc_component *component = max98090->component; in max98090_interrupt()
2243 dev_dbg(component->dev, "***** max98090_interrupt *****\n"); in max98090_interrupt()
2245 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask); in max98090_interrupt()
2248 dev_err(component->dev, in max98090_interrupt()
2254 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active); in max98090_interrupt()
2257 dev_err(component->dev, in max98090_interrupt()
2263 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n", in max98090_interrupt()
2272 dev_err(component->dev, "M98090_CLD_MASK\n"); in max98090_interrupt()
2275 dev_dbg(component->dev, "M98090_SLD_MASK\n"); in max98090_interrupt()
2278 dev_dbg(component->dev, "M98090_ULK_MASK\n"); in max98090_interrupt()
2283 dev_dbg(component->dev, "M98090_JDET_MASK\n"); in max98090_interrupt()
2285 pm_wakeup_event(component->dev, 100); in max98090_interrupt()
2288 &max98090->jack_work, in max98090_interrupt()
2293 dev_dbg(component->dev, "M98090_DRCACT_MASK\n"); in max98090_interrupt()
2296 dev_err(component->dev, "M98090_DRCCLP_MASK\n"); in max98090_interrupt()
2302 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2308 * being used to bring out signals to the processor then only platform
2319 dev_dbg(component->dev, "max98090_mic_detect\n"); in max98090_mic_detect()
2321 max98090->jack = jack; in max98090_mic_detect()
2333 snd_soc_jack_report(max98090->jack, 0, in max98090_mic_detect()
2337 &max98090->jack_work, in max98090_mic_detect()
2386 dev_dbg(component->dev, "max98090_probe\n"); in max98090_probe()
2388 max98090->mclk = devm_clk_get(component->dev, "mclk"); in max98090_probe()
2389 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER) in max98090_probe()
2390 return -EPROBE_DEFER; in max98090_probe()
2392 max98090->component = component; in max98090_probe()
2399 max98090->sysclk = (unsigned)-1; in max98090_probe()
2400 max98090->pclk = (unsigned)-1; in max98090_probe()
2401 max98090->master = false; in max98090_probe()
2403 cdata = &max98090->dai[0]; in max98090_probe()
2404 cdata->rate = (unsigned)-1; in max98090_probe()
2405 cdata->fmt = (unsigned)-1; in max98090_probe()
2407 max98090->lin_state = 0; in max98090_probe()
2408 max98090->pa1en = 0; in max98090_probe()
2409 max98090->pa2en = 0; in max98090_probe()
2411 max98090->tdm_lslot = 0; in max98090_probe()
2412 max98090->tdm_rslot = 1; in max98090_probe()
2416 dev_err(component->dev, "Failed to read device revision: %d\n", in max98090_probe()
2423 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret); in max98090_probe()
2426 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret); in max98090_probe()
2429 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret); in max98090_probe()
2432 if (max98090->devtype != devtype) { in max98090_probe()
2433 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n"); in max98090_probe()
2434 max98090->devtype = devtype; in max98090_probe()
2437 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET; in max98090_probe()
2439 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work); in max98090_probe()
2440 INIT_DELAYED_WORK(&max98090->pll_det_enable_work, in max98090_probe()
2442 INIT_WORK(&max98090->pll_det_disable_work, in max98090_probe()
2471 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias); in max98090_probe()
2474 dev_info(component->dev, "use default 2.8v micbias\n"); in max98090_probe()
2476 dev_err(component->dev, "micbias out of range 0x%x\n", micbias); in max98090_probe()
2493 cancel_delayed_work_sync(&max98090->jack_work); in max98090_remove()
2494 cancel_delayed_work_sync(&max98090->pll_det_enable_work); in max98090_remove()
2495 cancel_work_sync(&max98090->pll_det_disable_work); in max98090_remove()
2496 max98090->component = NULL; in max98090_remove()
2504 if (max98090->shdn_pending) { in max98090_seq_notifier()
2510 max98090->shdn_pending = false; in max98090_seq_notifier()
2552 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv), in max98090_i2c_probe()
2555 return -ENOMEM; in max98090_i2c_probe()
2557 if (ACPI_HANDLE(&i2c->dev)) { in max98090_i2c_probe()
2558 acpi_id = acpi_match_device(i2c->dev.driver->acpi_match_table, in max98090_i2c_probe()
2559 &i2c->dev); in max98090_i2c_probe()
2561 dev_err(&i2c->dev, "No driver data\n"); in max98090_i2c_probe()
2562 return -EINVAL; in max98090_i2c_probe()
2564 driver_data = acpi_id->driver_data; in max98090_i2c_probe()
2568 driver_data = i2c_id->driver_data; in max98090_i2c_probe()
2571 max98090->devtype = driver_data; in max98090_i2c_probe()
2573 max98090->pdata = i2c->dev.platform_data; in max98090_i2c_probe()
2575 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq", in max98090_i2c_probe()
2576 &max98090->dmic_freq); in max98090_i2c_probe()
2578 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ; in max98090_i2c_probe()
2580 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap); in max98090_i2c_probe()
2581 if (IS_ERR(max98090->regmap)) { in max98090_i2c_probe()
2582 ret = PTR_ERR(max98090->regmap); in max98090_i2c_probe()
2583 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret); in max98090_i2c_probe()
2587 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL, in max98090_i2c_probe()
2591 dev_err(&i2c->dev, "request_irq failed: %d\n", in max98090_i2c_probe()
2596 ret = devm_snd_soc_register_component(&i2c->dev, in max98090_i2c_probe()
2605 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev); in max98090_i2c_shutdown()
2611 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2613 regmap_write(max98090->regmap, in max98090_i2c_shutdown()
2628 regcache_cache_only(max98090->regmap, false); in max98090_runtime_resume()
2632 regcache_sync(max98090->regmap); in max98090_runtime_resume()
2641 regcache_cache_only(max98090->regmap, true); in max98090_runtime_suspend()
2653 regcache_mark_dirty(max98090->regmap); in max98090_resume()
2658 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status); in max98090_resume()
2660 regcache_sync(max98090->regmap); in max98090_resume()
2678 MODULE_DEVICE_TABLE(of, max98090_of_match);