Lines Matching +full:in4 +full:- +full:in5
1 // SPDX-License-Identifier: GPL-2.0-only
3 * max98090.c -- MAX98090 ALSA SoC Audio driver
5 * Copyright 2011-2012 Maxim Integrated Products
279 /* Reset the codec by writing to this write-only reset register */
280 ret = regmap_write(max98090->regmap, M98090_REG_SOFTWARE_RESET,
283 dev_err(max98090->component->dev,
300 -600, 600, 0);
303 0, 3, TLV_DB_SCALE_ITEM(-600, 300, 0),
308 static const DECLARE_TLV_DB_SCALE(max98090_av_tlv, -1200, 100, 0);
311 static const DECLARE_TLV_DB_SCALE(max98090_dv_tlv, -1500, 100, 0);
314 static const DECLARE_TLV_DB_SCALE(max98090_alccomp_tlv, -3100, 100, 0);
315 static const DECLARE_TLV_DB_SCALE(max98090_drcexp_tlv, -6600, 100, 0);
319 0, 1, TLV_DB_SCALE_ITEM(-1200, 250, 0),
320 2, 3, TLV_DB_SCALE_ITEM(-600, 600, 0)
324 0, 6, TLV_DB_SCALE_ITEM(-6700, 400, 0),
325 7, 14, TLV_DB_SCALE_ITEM(-4000, 300, 0),
326 15, 21, TLV_DB_SCALE_ITEM(-1700, 200, 0),
327 22, 27, TLV_DB_SCALE_ITEM(-400, 100, 0),
332 0, 4, TLV_DB_SCALE_ITEM(-4800, 400, 0),
333 5, 10, TLV_DB_SCALE_ITEM(-2900, 300, 0),
334 11, 14, TLV_DB_SCALE_ITEM(-1200, 200, 0),
335 15, 29, TLV_DB_SCALE_ITEM(-500, 100, 0),
340 0, 6, TLV_DB_SCALE_ITEM(-6200, 400, 0),
341 7, 14, TLV_DB_SCALE_ITEM(-3500, 300, 0),
342 15, 21, TLV_DB_SCALE_ITEM(-1200, 200, 0),
353 (struct soc_mixer_control *)kcontrol->private_value;
354 unsigned int mask = (1 << fls(mc->max)) - 1;
355 unsigned int val = snd_soc_component_read(component, mc->reg);
358 switch (mc->reg) {
360 select = &(max98090->pa1en);
363 select = &(max98090->pa2en);
366 select = &(max98090->sidetone);
369 return -EINVAL;
372 val = (val >> mc->shift) & mask;
376 val = val - 1;
383 ucontrol->value.integer.value[0] = val;
393 (struct soc_mixer_control *)kcontrol->private_value;
394 unsigned int mask = (1 << fls(mc->max)) - 1;
395 int sel_unchecked = ucontrol->value.integer.value[0];
397 unsigned int val = snd_soc_component_read(component, mc->reg);
401 switch (mc->reg) {
403 select = &(max98090->pa1en);
406 select = &(max98090->pa2en);
409 select = &(max98090->sidetone);
412 return -EINVAL;
415 val = (val >> mc->shift) & mask;
417 if (sel_unchecked < 0 || sel_unchecked > mc->max)
418 return -EINVAL;
432 snd_soc_component_update_bits(component, mc->reg,
433 mask << mc->shift,
434 sel << mc->shift);
518 M98090_DMIC_COMP_SHIFT, M98090_DMIC_COMP_NUM - 1, 0),
522 M98090_MIC_PA1EN_NUM - 1, 0, max98090_get_enab_tlv,
527 M98090_MIC_PA2EN_NUM - 1, 0, max98090_get_enab_tlv,
531 M98090_MIC_PGAM1_SHIFT, M98090_MIC_PGAM1_NUM - 1, 1,
535 M98090_MIC_PGAM2_SHIFT, M98090_MIC_PGAM2_NUM - 1, 1,
540 M98090_MIXG135_NUM - 1, 1, max98090_line_single_ended_tlv),
544 M98090_MIXG246_NUM - 1, 1, max98090_line_single_ended_tlv),
547 M98090_LINAPGA_SHIFT, 0, M98090_LINAPGA_NUM - 1, 1,
551 M98090_LINBPGA_SHIFT, 0, M98090_LINBPGA_NUM - 1, 1,
555 M98090_EXTBUFA_SHIFT, M98090_EXTBUFA_NUM - 1, 0),
557 M98090_EXTBUFB_SHIFT, M98090_EXTBUFB_NUM - 1, 0),
560 M98090_AVLG_SHIFT, M98090_AVLG_NUM - 1, 0,
563 M98090_AVRG_SHIFT, M98090_AVLG_NUM - 1, 0,
567 M98090_AVL_SHIFT, M98090_AVL_NUM - 1, 1,
570 M98090_AVR_SHIFT, M98090_AVR_NUM - 1, 1,
575 M98090_ADCDITHER_SHIFT, M98090_ADCDITHER_NUM - 1, 0),
579 M98090_DMONO_SHIFT, M98090_DMONO_NUM - 1, 0),
581 M98090_SDIEN_SHIFT, M98090_SDIEN_NUM - 1, 0),
583 M98090_SDOEN_SHIFT, M98090_SDOEN_NUM - 1, 0),
584 SOC_SINGLE("SDOUT Hi-Z Mode", M98090_REG_IO_CONFIGURATION,
585 M98090_HIZOFF_SHIFT, M98090_HIZOFF_NUM - 1, 1),
588 M98090_AHPF_SHIFT, M98090_AHPF_NUM - 1, 0),
590 M98090_DHPF_SHIFT, M98090_DHPF_NUM - 1, 0),
592 M98090_AVBQ_SHIFT, M98090_AVBQ_NUM - 1, 1, max98090_dv_tlv),
595 M98090_DVST_NUM - 1, 1, max98090_get_enab_tlv,
598 M98090_DVG_SHIFT, M98090_DVG_NUM - 1, 0,
601 M98090_DV_SHIFT, M98090_DV_NUM - 1, 1,
605 M98090_EQ3BANDEN_SHIFT, M98090_EQ3BANDEN_NUM - 1, 0),
607 M98090_EQ5BANDEN_SHIFT, M98090_EQ5BANDEN_NUM - 1, 0),
609 M98090_EQ7BANDEN_SHIFT, M98090_EQ7BANDEN_NUM - 1, 0),
611 M98090_EQCLPN_SHIFT, M98090_EQCLPN_NUM - 1,
614 M98090_DVEQ_SHIFT, M98090_DVEQ_NUM - 1, 1,
618 M98090_DRCEN_SHIFT, M98090_DRCEN_NUM - 1, 0),
622 M98090_DRCG_SHIFT, M98090_DRCG_NUM - 1, 0,
628 M98090_DRCTHC_NUM - 1, 1, max98090_alccomp_tlv),
631 M98090_DRCTHE_NUM - 1, 1, max98090_drcexp_tlv),
639 M98090_MIXHPLG_NUM - 1, 1, max98090_mixout_tlv),
642 M98090_MIXHPRG_NUM - 1, 1, max98090_mixout_tlv),
646 M98090_MIXSPLG_NUM - 1, 1, max98090_mixout_tlv),
649 M98090_MIXSPRG_NUM - 1, 1, max98090_mixout_tlv),
653 M98090_MIXRCVLG_NUM - 1, 1, max98090_mixout_tlv),
656 M98090_MIXRCVRG_NUM - 1, 1, max98090_mixout_tlv),
660 M98090_HPVOLL_NUM - 1, 0, max98090_hp_tlv),
664 M98090_SPVOLL_SHIFT, 24, M98090_SPVOLL_NUM - 1 + 24,
669 M98090_RCVLVOL_NUM - 1, 0, max98090_rcv_lout_tlv),
686 SOC_SINGLE("Zero-Crossing Detection", M98090_REG_LEVEL_CONTROL,
687 M98090_ZDENN_SHIFT, M98090_ZDENN_NUM - 1, 1),
689 M98090_VS2ENN_SHIFT, M98090_VS2ENN_NUM - 1, 1),
691 M98090_VSENN_SHIFT, M98090_VSENN_NUM - 1, 1),
695 M98090_ADCBQEN_SHIFT, M98090_ADCBQEN_NUM - 1, 0),
702 M98090_DMIC34_ZEROPAD_NUM - 1, 0),
707 M98090_FLT_DMIC34HPF_NUM - 1, 0),
710 M98090_DMIC_AV3G_SHIFT, M98090_DMIC_AV3G_NUM - 1, 0,
713 M98090_DMIC_AV4G_SHIFT, M98090_DMIC_AV4G_NUM - 1, 0,
717 M98090_DMIC_AV3_SHIFT, M98090_DMIC_AV3_NUM - 1, 1,
720 M98090_DMIC_AV4_SHIFT, M98090_DMIC_AV4_NUM - 1, 1,
726 M98090_DMIC34BQEN_SHIFT, M98090_DMIC34BQEN_NUM - 1, 0),
730 M98090_AV34BQ_NUM - 1, 1, max98090_dv_tlv),
736 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
739 unsigned int val = snd_soc_component_read(component, w->reg);
741 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
747 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL) {
748 max98090->pa1en = val - 1; /* Update for volatile */
750 max98090->pa2en = val - 1; /* Update for volatile */
757 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
758 val = max98090->pa1en + 1;
760 val = max98090->pa2en + 1;
767 return -EINVAL;
770 if (w->reg == M98090_REG_MIC1_INPUT_LEVEL)
771 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA1EN_MASK,
774 snd_soc_component_update_bits(component, w->reg, M98090_MIC_PA2EN_MASK,
783 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
787 max98090->shdn_pending = true;
826 SOC_DAPM_SINGLE("IN5 Switch", M98090_REG_LINE_INPUT_CONFIG,
836 SOC_DAPM_SINGLE("IN4 Switch", M98090_REG_LINE_INPUT_CONFIG,
1073 SND_SOC_DAPM_INPUT("IN4"),
1074 SND_SOC_DAPM_INPUT("IN5"),
1285 {"LINEA Mixer", "IN5 Switch", "IN5"},
1290 {"LINEB Mixer", "IN4 Switch", "IN4"},
1440 if (max98090->devtype == MAX98091) {
1451 if (max98090->devtype == MAX98091) {
1494 if (!max98090->sysclk) {
1495 dev_err(component->dev, "No SYSCLK configured\n");
1499 if (!max98090->bclk || !max98090->lrclk) {
1500 dev_err(component->dev, "No audio clocks configured\n");
1512 if ((pclk_rates[i] == max98090->sysclk) &&
1513 (lrclk_rates[i] == max98090->lrclk)) {
1514 dev_dbg(component->dev,
1529 if ((user_pclk_rates[i] == max98090->sysclk) &&
1530 (user_lrclk_rates[i] == max98090->lrclk)) {
1531 dev_dbg(component->dev,
1533 dev_dbg(component->dev, "i %d ni %lld mi %lld\n",
1568 ni = 65536ULL * (max98090->lrclk < 50000 ? 96ULL : 48ULL)
1569 * (unsigned long long int)max98090->lrclk;
1570 do_div(ni, (unsigned long long int)max98090->sysclk);
1571 dev_info(component->dev, "No better method found\n");
1572 dev_info(component->dev, "Calculating ni %lld with mi 65536\n", ni);
1581 struct snd_soc_component *component = codec_dai->component;
1586 max98090->dai_fmt = fmt;
1587 cdata = &max98090->dai[0];
1589 if (fmt != cdata->fmt) {
1590 cdata->fmt = fmt;
1596 /* Set to consumer mode PLL - MAS mode off */
1603 max98090->master = false;
1607 if (max98090->tdm_slots == 4) {
1611 } else if (max98090->tdm_slots == 3) {
1620 max98090->master = true;
1623 dev_err(component->dev, "DAI clock mode unsupported");
1624 return -EINVAL;
1642 dev_err(component->dev, "DAI format unsupported");
1643 return -EINVAL;
1659 dev_err(component->dev, "DAI invert mode unsupported");
1660 return -EINVAL;
1677 regval = max98090->tdm_lslot << M98090_TDM_SLOTL_SHIFT |
1678 max98090->tdm_rslot << M98090_TDM_SLOTR_SHIFT |
1691 struct snd_soc_component *component = codec_dai->component;
1695 return -EINVAL;
1698 return -EINVAL;
1701 return -EINVAL;
1704 return -EINVAL;
1706 max98090->tdm_slots = slots;
1707 max98090->tdm_lslot = ffs(rx_mask) - 1;
1708 max98090->tdm_rslot = fls(rx_mask) - 1;
1731 if (IS_ERR(max98090->mclk))
1735 clk_disable_unprepare(max98090->mclk);
1737 ret = clk_prepare_enable(max98090->mclk);
1745 ret = regcache_sync(max98090->regmap);
1747 dev_err(component->dev,
1755 /* Set internal pull-up to lowest power mode */
1758 regcache_mark_dirty(max98090->regmap);
1844 test_diff = abs(target_freq - (pclk / dmic_divisors[i]));
1866 m1 = pclk - dmic_table[i-1].pclk;
1867 m2 = dmic_table[i].pclk - pclk;
1869 return i - 1;
1875 return -EINVAL;
1893 for (i = 0; i < ARRAY_SIZE(comp_lrclk_rates) - 1; i++) {
1901 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_ENABLE,
1905 regmap_update_bits(max98090->regmap, M98090_REG_DIGITAL_MIC_CONFIG,
1916 struct snd_soc_component *component = dai->component;
1918 unsigned int fmt = max98090->dai_fmt;
1920 /* Remove 24-bit format support if it is not in right justified mode. */
1922 substream->runtime->hw.formats = SNDRV_PCM_FMTBIT_S16_LE;
1923 snd_pcm_hw_constraint_msbits(substream->runtime, 0, 16, 16);
1932 struct snd_soc_component *component = dai->component;
1936 cdata = &max98090->dai[0];
1937 max98090->bclk = snd_soc_params_to_bclk(params);
1939 max98090->bclk *= 2;
1941 max98090->lrclk = params_rate(params);
1949 return -EINVAL;
1952 if (max98090->master)
1955 cdata->rate = max98090->lrclk;
1958 if (max98090->lrclk < 24000)
1966 if (max98090->lrclk < 50000)
1973 max98090_configure_dmic(max98090, max98090->dmic_freq, max98090->pclk,
1974 max98090->lrclk);
1985 struct snd_soc_component *component = dai->component;
1989 if (freq == max98090->sysclk)
1992 if (!IS_ERR(max98090->mclk)) {
1993 freq = clk_round_rate(max98090->mclk, freq);
1994 clk_set_rate(max98090->mclk, freq);
2005 max98090->pclk = freq;
2009 max98090->pclk = freq >> 1;
2013 max98090->pclk = freq >> 2;
2015 dev_err(component->dev, "Invalid master clock frequency\n");
2016 return -EINVAL;
2019 max98090->sysclk = freq;
2027 struct snd_soc_component *component = codec_dai->component;
2040 struct snd_soc_component *component = dai->component;
2047 if (!max98090->master && snd_soc_dai_active(dai) == 1)
2049 &max98090->pll_det_enable_work,
2055 if (!max98090->master && snd_soc_dai_active(dai) == 1)
2056 schedule_work(&max98090->pll_det_disable_work);
2070 struct snd_soc_component *component = max98090->component;
2079 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2085 regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2089 &max98090->jack_work,
2102 struct snd_soc_component *component = max98090->component;
2104 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2113 struct snd_soc_component *component = max98090->component;
2120 dev_info_ratelimited(component->dev, "PLL unlocked\n");
2152 struct snd_soc_component *component = max98090->component;
2157 if (max98090->jack_state == M98090_JACK_STATE_NO_HEADSET) {
2176 dev_dbg(component->dev, "No Headset Detected\n");
2178 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2185 if (max98090->jack_state ==
2188 dev_dbg(component->dev,
2205 dev_dbg(component->dev, "Headphone Detected\n");
2207 max98090->jack_state = M98090_JACK_STATE_HEADPHONE;
2214 dev_dbg(component->dev, "Headset Detected\n");
2216 max98090->jack_state = M98090_JACK_STATE_HEADSET;
2223 dev_dbg(component->dev, "Unrecognized Jack Status\n");
2227 snd_soc_jack_report(max98090->jack, status,
2234 struct snd_soc_component *component = max98090->component;
2243 dev_dbg(component->dev, "***** max98090_interrupt *****\n");
2245 ret = regmap_read(max98090->regmap, M98090_REG_INTERRUPT_S, &mask);
2248 dev_err(component->dev,
2254 ret = regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &active);
2257 dev_err(component->dev,
2263 dev_dbg(component->dev, "active=0x%02x mask=0x%02x -> active=0x%02x\n",
2272 dev_err(component->dev, "M98090_CLD_MASK\n");
2275 dev_dbg(component->dev, "M98090_SLD_MASK\n");
2278 dev_dbg(component->dev, "M98090_ULK_MASK\n");
2283 dev_dbg(component->dev, "M98090_JDET_MASK\n");
2285 pm_wakeup_event(component->dev, 100);
2288 &max98090->jack_work,
2293 dev_dbg(component->dev, "M98090_DRCACT_MASK\n");
2296 dev_err(component->dev, "M98090_DRCCLP_MASK\n");
2302 * max98090_mic_detect - Enable microphone detection via the MAX98090 IRQ
2319 dev_dbg(component->dev, "max98090_mic_detect\n");
2321 max98090->jack = jack;
2333 snd_soc_jack_report(max98090->jack, 0,
2337 &max98090->jack_work,
2386 dev_dbg(component->dev, "max98090_probe\n");
2388 max98090->mclk = devm_clk_get(component->dev, "mclk");
2389 if (PTR_ERR(max98090->mclk) == -EPROBE_DEFER)
2390 return -EPROBE_DEFER;
2392 max98090->component = component;
2399 max98090->sysclk = (unsigned)-1;
2400 max98090->pclk = (unsigned)-1;
2401 max98090->master = false;
2403 cdata = &max98090->dai[0];
2404 cdata->rate = (unsigned)-1;
2405 cdata->fmt = (unsigned)-1;
2407 max98090->lin_state = 0;
2408 max98090->pa1en = 0;
2409 max98090->pa2en = 0;
2411 max98090->tdm_lslot = 0;
2412 max98090->tdm_rslot = 1;
2416 dev_err(component->dev, "Failed to read device revision: %d\n",
2423 dev_info(component->dev, "MAX98090 REVID=0x%02x\n", ret);
2426 dev_info(component->dev, "MAX98091 REVID=0x%02x\n", ret);
2429 dev_err(component->dev, "Unrecognized revision 0x%02x\n", ret);
2432 if (max98090->devtype != devtype) {
2433 dev_warn(component->dev, "Mismatch in DT specified CODEC type.\n");
2434 max98090->devtype = devtype;
2437 max98090->jack_state = M98090_JACK_STATE_NO_HEADSET;
2439 INIT_DELAYED_WORK(&max98090->jack_work, max98090_jack_work);
2440 INIT_DELAYED_WORK(&max98090->pll_det_enable_work,
2442 INIT_WORK(&max98090->pll_det_disable_work,
2471 err = device_property_read_u32(component->dev, "maxim,micbias", &micbias);
2474 dev_info(component->dev, "use default 2.8v micbias\n");
2476 dev_err(component->dev, "micbias out of range 0x%x\n", micbias);
2493 cancel_delayed_work_sync(&max98090->jack_work);
2494 cancel_delayed_work_sync(&max98090->pll_det_enable_work);
2495 cancel_work_sync(&max98090->pll_det_disable_work);
2496 max98090->component = NULL;
2504 if (max98090->shdn_pending) {
2510 max98090->shdn_pending = false;
2550 max98090 = devm_kzalloc(&i2c->dev, sizeof(struct max98090_priv),
2553 return -ENOMEM;
2555 max98090->devtype = (uintptr_t)i2c_get_match_data(i2c);
2557 max98090->pdata = i2c->dev.platform_data;
2559 ret = of_property_read_u32(i2c->dev.of_node, "maxim,dmic-freq",
2560 &max98090->dmic_freq);
2562 max98090->dmic_freq = MAX98090_DEFAULT_DMIC_FREQ;
2564 max98090->regmap = devm_regmap_init_i2c(i2c, &max98090_regmap);
2565 if (IS_ERR(max98090->regmap)) {
2566 ret = PTR_ERR(max98090->regmap);
2567 dev_err(&i2c->dev, "Failed to allocate regmap: %d\n", ret);
2571 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
2575 dev_err(&i2c->dev, "request_irq failed: %d\n",
2580 ret = devm_snd_soc_register_component(&i2c->dev,
2589 struct max98090_priv *max98090 = dev_get_drvdata(&i2c->dev);
2595 regmap_write(max98090->regmap,
2597 regmap_write(max98090->regmap,
2612 regcache_cache_only(max98090->regmap, false);
2616 regcache_sync(max98090->regmap);
2625 regcache_cache_only(max98090->regmap, true);
2637 regcache_mark_dirty(max98090->regmap);
2642 regmap_read(max98090->regmap, M98090_REG_DEVICE_STATUS, &status);
2644 regcache_sync(max98090->regmap);