Lines Matching +full:sm8250 +full:- +full:lpass +full:- +full:tx +full:- +full:macro
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
5 #include <linux/clk-provider.h>
16 #include <sound/soc-dapm.h>
19 #include "lpass-macro-common.h"
21 /* VA macro registers */
165 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
209 struct clk *macro;
266 /* VA macro */
454 struct regmap *regmap = va->regmap;
487 struct regmap *regmap = va->regmap;
503 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
508 return clk_prepare_enable(va->fsgen);
510 clk_disable_unprepare(va->fsgen);
522 snd_soc_dapm_to_component(widget->dapm);
523 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
527 val = ucontrol->value.enumerated.item[0];
529 switch (e->reg) {
543 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n",
544 __func__, e->reg);
545 return -EINVAL;
562 snd_soc_dapm_to_component(widget->dapm);
564 (struct soc_mixer_control *)kcontrol->private_value;
565 u32 dai_id = widget->shift;
566 u32 dec_id = mc->shift;
569 if (test_bit(dec_id, &va->active_ch_mask[dai_id]))
570 ucontrol->value.integer.value[0] = 1;
572 ucontrol->value.integer.value[0] = 0;
583 snd_soc_dapm_to_component(widget->dapm);
586 (struct soc_mixer_control *)kcontrol->private_value;
587 u32 dai_id = widget->shift;
588 u32 dec_id = mc->shift;
589 u32 enable = ucontrol->value.integer.value[0];
593 set_bit(dec_id, &va->active_ch_mask[dai_id]);
594 va->active_ch_cnt[dai_id]++;
596 clear_bit(dec_id, &va->active_ch_mask[dai_id]);
597 va->active_ch_cnt[dai_id]--;
600 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
618 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt);
619 dmic_clk_div = &(va->dmic_0_1_clk_div);
625 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt);
626 dmic_clk_div = &(va->dmic_2_3_clk_div);
632 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt);
633 dmic_clk_div = &(va->dmic_4_5_clk_div);
639 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt);
640 dmic_clk_div = &(va->dmic_6_7_clk_div);
645 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
647 return -EINVAL;
651 clk_div = va->dmic_clk_div;
683 (*dmic_clk_cnt)--;
692 clk_div = va->dmic_clk_div;
694 clk_div = va->dmic_clk_div;
719 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
720 unsigned int dmic = w->shift;
737 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
745 decimator = w->shift;
760 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT);
761 /* Enable TX PGA Mute */
764 /* Enable TX CLK */
810 /* Disable TX CLK */
824 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
825 int path = e->shift_l;
827 ucontrol->value.enumerated.item[0] = va->dec_mode[path];
836 int value = ucontrol->value.enumerated.item[0];
837 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
838 int path = e->shift_l;
841 va->dec_mode[path] = value;
851 struct snd_soc_component *component = dai->component;
854 struct device *va_dev = component->dev;
881 dev_err(va_dev, "%s: Invalid TX sample rate: %d\n",
883 return -EINVAL;
886 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
900 struct snd_soc_component *component = dai->component;
901 struct device *va_dev = component->dev;
904 switch (dai->id) {
908 *tx_slot = va->active_ch_mask[dai->id];
909 *tx_num = va->active_ch_cnt[dai->id];
920 struct snd_soc_component *component = dai->component;
924 for_each_set_bit(decimator, &va->active_ch_mask[dai->id],
1131 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1206 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1302 -84, 40, digital_gain),
1304 -84, 40, digital_gain),
1306 -84, 40, digital_gain),
1308 -84, 40, digital_gain),
1324 snd_soc_component_init_regmap(component, va->regmap);
1330 .name = "VA MACRO",
1343 struct regmap *regmap = va->regmap;
1346 if (va->has_swr_master) {
1347 ret = clk_prepare_enable(va->mclk);
1353 if (va->has_swr_master)
1363 struct regmap *regmap = va->regmap;
1365 if (va->has_swr_master)
1370 if (va->has_swr_master)
1371 clk_disable_unprepare(va->mclk);
1379 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val);
1392 struct clk *parent = va->mclk;
1393 struct device *dev = va->dev;
1394 struct device_node *np = dev->of_node;
1400 if (va->has_npl_clk)
1401 parent = va->npl;
1405 of_property_read_string(np, "clock-output-names", &clk_name);
1412 va->hw.init = &init;
1413 ret = devm_clk_hw_register(va->dev, &va->hw);
1417 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw);
1433 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1436 va->dmic_clk_div = VA_MACRO_CLK_DIV_3;
1439 va->dmic_clk_div = VA_MACRO_CLK_DIV_4;
1442 va->dmic_clk_div = VA_MACRO_CLK_DIV_6;
1445 va->dmic_clk_div = VA_MACRO_CLK_DIV_8;
1448 va->dmic_clk_div = VA_MACRO_CLK_DIV_16;
1458 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n",
1470 regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_0, &core_id_0);
1471 regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_1, &core_id_1);
1472 regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_2, &core_id_2);
1492 dev_warn(va->dev, "Unknown Codec version, ID: %02x / %02x / %02x\n",
1497 dev_dbg(va->dev, "LPASS Codec Version %s\n", lpass_macro_get_codec_version_string(version));
1502 struct device *dev = &pdev->dev;
1511 return -ENOMEM;
1513 va->dev = dev;
1515 va->macro = devm_clk_get_optional(dev, "macro");
1516 if (IS_ERR(va->macro))
1517 return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n");
1519 va->dcodec = devm_clk_get_optional(dev, "dcodec");
1520 if (IS_ERR(va->dcodec))
1521 return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n");
1523 va->mclk = devm_clk_get(dev, "mclk");
1524 if (IS_ERR(va->mclk))
1525 return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n");
1527 va->pds = lpass_macro_pds_init(dev);
1528 if (IS_ERR(va->pds))
1529 return PTR_ERR(va->pds);
1531 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate",
1534 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n");
1535 va->dmic_clk_div = VA_MACRO_CLK_DIV_2;
1539 ret = -EINVAL;
1550 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config);
1551 if (IS_ERR(va->regmap)) {
1552 ret = -EINVAL;
1559 va->has_swr_master = data->has_swr_master;
1560 va->has_npl_clk = data->has_npl_clk;
1563 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ);
1565 if (va->has_npl_clk) {
1566 va->npl = devm_clk_get(dev, "npl");
1567 if (IS_ERR(va->npl)) {
1568 ret = PTR_ERR(va->npl);
1572 clk_set_rate(va->npl, 2 * VA_MACRO_MCLK_FREQ);
1575 ret = clk_prepare_enable(va->macro);
1579 ret = clk_prepare_enable(va->dcodec);
1583 ret = clk_prepare_enable(va->mclk);
1587 if (va->has_npl_clk) {
1588 ret = clk_prepare_enable(va->npl);
1597 if (data->version)
1598 lpass_macro_set_codec_version(data->version);
1602 if (va->has_swr_master) {
1604 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
1607 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1,
1610 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2,
1616 if (va->has_swr_master) {
1617 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1619 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1621 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL,
1641 va->fsgen = clk_hw_get_clk(&va->hw, "fsgen");
1642 if (IS_ERR(va->fsgen)) {
1643 ret = PTR_ERR(va->fsgen);
1650 if (va->has_npl_clk)
1651 clk_disable_unprepare(va->npl);
1653 clk_disable_unprepare(va->mclk);
1655 clk_disable_unprepare(va->dcodec);
1657 clk_disable_unprepare(va->macro);
1659 lpass_macro_pds_exit(va->pds);
1666 struct va_macro *va = dev_get_drvdata(&pdev->dev);
1668 if (va->has_npl_clk)
1669 clk_disable_unprepare(va->npl);
1671 clk_disable_unprepare(va->mclk);
1672 clk_disable_unprepare(va->dcodec);
1673 clk_disable_unprepare(va->macro);
1675 lpass_macro_pds_exit(va->pds);
1682 regcache_cache_only(va->regmap, true);
1683 regcache_mark_dirty(va->regmap);
1685 if (va->has_npl_clk)
1686 clk_disable_unprepare(va->npl);
1688 clk_disable_unprepare(va->mclk);
1698 ret = clk_prepare_enable(va->mclk);
1700 dev_err(va->dev, "unable to prepare mclk\n");
1704 if (va->has_npl_clk) {
1705 ret = clk_prepare_enable(va->npl);
1707 clk_disable_unprepare(va->mclk);
1708 dev_err(va->dev, "unable to prepare npl\n");
1713 regcache_cache_only(va->regmap, false);
1714 regcache_sync(va->regmap);
1725 { .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
1726 { .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
1727 { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
1728 { .compatible = "qcom,sm8550-lpass-va-macro", .data = &sm8550_va_data },
1729 { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },
1746 MODULE_DESCRIPTION("VA macro driver");