Lines Matching full:tx
246 struct tx_macro *tx; member
252 struct tx_macro *tx; member
295 /* TX Macro */
439 /* Update volatile list for tx/tx macros */ in tx_is_volatile_register()
614 static int tx_macro_mclk_enable(struct tx_macro *tx, in tx_macro_mclk_enable() argument
617 struct regmap *regmap = tx->regmap; in tx_macro_mclk_enable()
620 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
632 tx->tx_mclk_users++; in tx_macro_mclk_enable()
634 if (tx->tx_mclk_users <= 0) { in tx_macro_mclk_enable()
635 dev_err(tx->dev, "clock already disabled\n"); in tx_macro_mclk_enable()
636 tx->tx_mclk_users = 0; in tx_macro_mclk_enable()
639 tx->tx_mclk_users--; in tx_macro_mclk_enable()
640 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
652 struct tx_macro *tx, u8 decimator) in is_amic_enabled() argument
659 if (tx->data->ver > LPASS_VER_9_0_0) in is_amic_enabled()
677 struct tx_macro *tx; in tx_macro_tx_hpf_corner_freq_callback() local
684 tx = hpf_work->tx; in tx_macro_tx_hpf_corner_freq_callback()
685 component = tx->component; in tx_macro_tx_hpf_corner_freq_callback()
691 if (is_amic_enabled(component, tx, hpf_work->decimator)) { in tx_macro_tx_hpf_corner_freq_callback()
721 struct tx_macro *tx; in tx_macro_mute_update_callback() local
727 tx = tx_mute_dwork->tx; in tx_macro_mute_update_callback()
728 component = tx->component; in tx_macro_mute_update_callback()
739 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_mclk_event() local
743 tx_macro_mclk_enable(tx, true); in tx_macro_mclk_event()
746 tx_macro_mclk_enable(tx, false); in tx_macro_mclk_event()
757 struct tx_macro *tx, u16 mic_sel_reg, in tx_macro_update_smic_sel_v9() argument
779 struct tx_macro *tx, u16 mic_sel_reg, in tx_macro_update_smic_sel_v9_2() argument
807 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_put_dec_enum() local
849 else if (tx->data->ver <= LPASS_VER_9_0_0) in tx_macro_put_dec_enum()
850 tx_macro_update_smic_sel_v9(component, widget, tx, in tx_macro_put_dec_enum()
853 tx_macro_update_smic_sel_v9_2(component, widget, tx, in tx_macro_put_dec_enum()
868 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_tx_mixer_get() local
870 if (test_bit(dec_id, &tx->active_ch_mask[dai_id])) in tx_macro_tx_mixer_get()
888 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_tx_mixer_put() local
891 if (tx->active_decimator[dai_id] == dec_id) in tx_macro_tx_mixer_put()
894 set_bit(dec_id, &tx->active_ch_mask[dai_id]); in tx_macro_tx_mixer_put()
895 tx->active_ch_cnt[dai_id]++; in tx_macro_tx_mixer_put()
896 tx->active_decimator[dai_id] = dec_id; in tx_macro_tx_mixer_put()
898 if (tx->active_decimator[dai_id] == -1) in tx_macro_tx_mixer_put()
901 tx->active_ch_cnt[dai_id]--; in tx_macro_tx_mixer_put()
902 clear_bit(dec_id, &tx->active_ch_mask[dai_id]); in tx_macro_tx_mixer_put()
903 tx->active_decimator[dai_id] = -1; in tx_macro_tx_mixer_put()
921 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_enable_dec() local
947 tx->dec_mode[decimator]); in tx_macro_enable_dec()
948 /* Enable TX PGA Mute */ in tx_macro_enable_dec()
955 if (!is_amic_enabled(component, tx, decimator)) { in tx_macro_enable_dec()
963 tx->tx_hpf_work[decimator].hpf_cut_off_freq = in tx_macro_enable_dec()
971 if (is_amic_enabled(component, tx, decimator)) { in tx_macro_enable_dec()
977 &tx->tx_mute_dwork[decimator].dwork, in tx_macro_enable_dec()
979 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) { in tx_macro_enable_dec()
981 &tx->tx_hpf_work[decimator].dwork, in tx_macro_enable_dec()
987 if (!is_amic_enabled(component, tx, decimator)) in tx_macro_enable_dec()
1006 if (tx->bcs_enable) { in tx_macro_enable_dec()
1009 tx->bcs_clk_en = true; in tx_macro_enable_dec()
1014 tx->tx_hpf_work[decimator].hpf_cut_off_freq; in tx_macro_enable_dec()
1018 &tx->tx_hpf_work[decimator].dwork)) { in tx_macro_enable_dec()
1024 if (is_amic_enabled(component, tx, decimator)) in tx_macro_enable_dec()
1048 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork); in tx_macro_enable_dec()
1057 if (tx->bcs_enable) { in tx_macro_enable_dec()
1064 tx->bcs_clk_en = false; in tx_macro_enable_dec()
1075 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_dec_mode_get() local
1079 ucontrol->value.integer.value[0] = tx->dec_mode[path]; in tx_macro_dec_mode_get()
1091 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_dec_mode_put() local
1093 if (tx->dec_mode[path] == value) in tx_macro_dec_mode_put()
1096 tx->dec_mode[path] = value; in tx_macro_dec_mode_put()
1105 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_get_bcs() local
1107 ucontrol->value.integer.value[0] = tx->bcs_enable; in tx_macro_get_bcs()
1117 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_set_bcs() local
1119 tx->bcs_enable = value; in tx_macro_set_bcs()
1132 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_hw_params() local
1158 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", in tx_macro_hw_params()
1163 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX) in tx_macro_hw_params()
1175 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_get_channel_map() local
1181 *tx_slot = tx->active_ch_mask[dai->id]; in tx_macro_get_channel_map()
1182 *tx_num = tx->active_ch_cnt[dai->id]; in tx_macro_get_channel_map()
1193 struct tx_macro *tx = snd_soc_component_get_drvdata(component); in tx_macro_digital_mute() local
1197 if (tx->active_decimator[dai->id] == -1) in tx_macro_digital_mute()
1200 decimator = tx->active_decimator[dai->id]; in tx_macro_digital_mute()
1440 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1441 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1442 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1443 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1444 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1445 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1446 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1447 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1449 SND_SOC_DAPM_INPUT("TX DMIC0"),
1450 SND_SOC_DAPM_INPUT("TX DMIC1"),
1451 SND_SOC_DAPM_INPUT("TX DMIC2"),
1452 SND_SOC_DAPM_INPUT("TX DMIC3"),
1453 SND_SOC_DAPM_INPUT("TX DMIC4"),
1454 SND_SOC_DAPM_INPUT("TX DMIC5"),
1455 SND_SOC_DAPM_INPUT("TX DMIC6"),
1456 SND_SOC_DAPM_INPUT("TX DMIC7"),
1458 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1464 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1470 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1476 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1482 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1488 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1494 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1500 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1524 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1525 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1526 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1527 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1528 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1529 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1530 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1531 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1533 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1534 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1535 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1536 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1537 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1538 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1539 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1540 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1542 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1543 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1544 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1545 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1546 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1547 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1548 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1549 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1551 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1552 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1553 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1554 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1555 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1556 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1557 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1558 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1560 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1561 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
1562 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
1563 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
1564 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
1565 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
1566 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
1567 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
1568 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
1570 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1571 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
1572 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
1573 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
1574 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
1575 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
1576 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
1577 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
1578 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
1580 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1581 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
1582 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
1583 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
1584 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
1585 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
1586 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
1587 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
1588 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
1590 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1591 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
1592 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
1593 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
1594 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
1595 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
1596 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
1597 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
1598 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
1600 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1601 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
1602 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
1603 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
1604 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
1605 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
1606 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
1607 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
1608 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
1610 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1611 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
1612 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
1613 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
1614 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
1615 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
1616 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
1617 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
1618 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
1620 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1621 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
1622 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
1623 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
1624 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
1625 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
1626 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
1627 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
1628 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
1630 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1631 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
1632 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
1633 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
1634 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
1635 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
1636 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
1637 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
1638 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
1690 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9),
1691 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9),
1692 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9),
1693 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9),
1694 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9),
1695 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9),
1696 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9),
1697 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9),
1699 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1700 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1701 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1702 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1703 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1704 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1705 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1706 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1707 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1708 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1709 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1710 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1714 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1715 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1716 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1717 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1718 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1719 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1720 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1721 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1722 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1723 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1724 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1725 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1726 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1727 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1729 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1730 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1731 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1732 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1733 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1734 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1735 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1736 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1737 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1738 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1739 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1740 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1741 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1742 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1744 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1745 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1746 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1747 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1748 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1749 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1750 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1751 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1752 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1753 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1754 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1755 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1756 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1757 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1759 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1760 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1761 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1762 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1763 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1764 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1765 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1766 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1767 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1768 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1769 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1770 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1771 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1772 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1774 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1775 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1776 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1777 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1778 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1779 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1780 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1781 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1782 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1783 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1784 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1785 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1786 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1787 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1789 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1790 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1791 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1792 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1793 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1794 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1795 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1796 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1797 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1798 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1799 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1800 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1801 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1802 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1804 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1805 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1806 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1807 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1808 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1809 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1810 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1811 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1812 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1813 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1814 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1815 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1816 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1817 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1819 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1820 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1821 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1822 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1823 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1824 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1825 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1826 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1827 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1828 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1829 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1830 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1831 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1832 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1884 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_2),
1885 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_2),
1886 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_2),
1887 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_2),
1888 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_2),
1889 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_2),
1890 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_2),
1891 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_2),
1893 SND_SOC_DAPM_INPUT("TX SWR_INPUT0"),
1894 SND_SOC_DAPM_INPUT("TX SWR_INPUT1"),
1895 SND_SOC_DAPM_INPUT("TX SWR_INPUT2"),
1896 SND_SOC_DAPM_INPUT("TX SWR_INPUT3"),
1897 SND_SOC_DAPM_INPUT("TX SWR_INPUT4"),
1898 SND_SOC_DAPM_INPUT("TX SWR_INPUT5"),
1899 SND_SOC_DAPM_INPUT("TX SWR_INPUT6"),
1900 SND_SOC_DAPM_INPUT("TX SWR_INPUT7"),
1901 SND_SOC_DAPM_INPUT("TX SWR_INPUT8"),
1902 SND_SOC_DAPM_INPUT("TX SWR_INPUT9"),
1903 SND_SOC_DAPM_INPUT("TX SWR_INPUT10"),
1904 SND_SOC_DAPM_INPUT("TX SWR_INPUT11"),
1908 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1909 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1910 {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_INPUT0"},
1911 {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_INPUT1"},
1912 {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_INPUT2"},
1913 {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_INPUT3"},
1914 {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_INPUT4"},
1915 {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_INPUT5"},
1916 {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_INPUT6"},
1917 {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_INPUT7"},
1918 {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_INPUT8"},
1919 {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_INPUT9"},
1920 {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_INPUT11"},
1921 {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_INPUT10"},
1923 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1924 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1925 {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_INPUT0"},
1926 {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_INPUT1"},
1927 {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_INPUT2"},
1928 {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_INPUT3"},
1929 {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_INPUT4"},
1930 {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_INPUT5"},
1931 {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_INPUT6"},
1932 {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_INPUT7"},
1933 {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_INPUT8"},
1934 {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_INPUT9"},
1935 {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_INPUT10"},
1936 {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_INPUT11"},
1938 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1939 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1940 {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_INPUT0"},
1941 {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_INPUT1"},
1942 {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_INPUT2"},
1943 {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_INPUT3"},
1944 {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_INPUT4"},
1945 {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_INPUT5"},
1946 {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_INPUT6"},
1947 {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_INPUT7"},
1948 {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_INPUT8"},
1949 {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_INPUT9"},
1950 {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_INPUT10"},
1951 {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_INPUT11"},
1953 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1954 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1955 {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_INPUT0"},
1956 {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_INPUT1"},
1957 {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_INPUT2"},
1958 {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_INPUT3"},
1959 {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_INPUT4"},
1960 {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_INPUT5"},
1961 {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_INPUT6"},
1962 {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_INPUT7"},
1963 {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_INPUT8"},
1964 {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT9"},
1965 {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT10"},
1966 {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT11"},
1968 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1969 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1970 {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_INPUT0"},
1971 {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_INPUT1"},
1972 {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_INPUT2"},
1973 {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_INPUT3"},
1974 {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_INPUT4"},
1975 {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_INPUT5"},
1976 {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_INPUT6"},
1977 {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_INPUT7"},
1978 {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_INPUT8"},
1979 {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_INPUT9"},
1980 {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_INPUT10"},
1981 {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_INPUT11"},
1983 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1984 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1985 {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_INPUT0"},
1986 {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_INPUT1"},
1987 {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_INPUT2"},
1988 {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_INPUT3"},
1989 {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_INPUT4"},
1990 {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_INPUT5"},
1991 {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_INPUT6"},
1992 {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_INPUT7"},
1993 {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_INPUT8"},
1994 {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_INPUT9"},
1995 {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_INPUT10"},
1996 {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_INPUT11"},
1998 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1999 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
2000 {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_INPUT0"},
2001 {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_INPUT1"},
2002 {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_INPUT2"},
2003 {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_INPUT3"},
2004 {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_INPUT4"},
2005 {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_INPUT5"},
2006 {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_INPUT6"},
2007 {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_INPUT7"},
2008 {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_INPUT8"},
2009 {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_INPUT9"},
2010 {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_INPUT10"},
2011 {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_INPUT11"},
2013 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
2014 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
2015 {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_INPUT0"},
2016 {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_INPUT1"},
2017 {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_INPUT2"},
2018 {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_INPUT3"},
2019 {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_INPUT4"},
2020 {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_INPUT5"},
2021 {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_INPUT6"},
2022 {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_INPUT7"},
2023 {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_INPUT8"},
2024 {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT9"},
2025 {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT10"},
2026 {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT11"},
2086 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); in tx_macro_component_extend() local
2089 if (tx->data->extra_widgets_num) { in tx_macro_component_extend()
2090 ret = snd_soc_dapm_new_controls(dapm, tx->data->extra_widgets, in tx_macro_component_extend()
2091 tx->data->extra_widgets_num); in tx_macro_component_extend()
2093 dev_err(tx->dev, "failed to add extra widgets: %d\n", ret); in tx_macro_component_extend()
2098 if (tx->data->extra_routes_num) { in tx_macro_component_extend()
2099 ret = snd_soc_dapm_add_routes(dapm, tx->data->extra_routes, in tx_macro_component_extend()
2100 tx->data->extra_routes_num); in tx_macro_component_extend()
2102 dev_err(tx->dev, "failed to add extra routes: %d\n", ret); in tx_macro_component_extend()
2112 struct tx_macro *tx = snd_soc_component_get_drvdata(comp); in tx_macro_component_probe() local
2119 snd_soc_component_init_regmap(comp, tx->regmap); in tx_macro_component_probe()
2122 tx->tx_hpf_work[i].tx = tx; in tx_macro_component_probe()
2123 tx->tx_hpf_work[i].decimator = i; in tx_macro_component_probe()
2124 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork, in tx_macro_component_probe()
2129 tx->tx_mute_dwork[i].tx = tx; in tx_macro_component_probe()
2130 tx->tx_mute_dwork[i].decimator = i; in tx_macro_component_probe()
2131 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork, in tx_macro_component_probe()
2134 tx->component = comp; in tx_macro_component_probe()
2149 struct tx_macro *tx = to_tx_macro(hw); in swclk_gate_enable() local
2150 struct regmap *regmap = tx->regmap; in swclk_gate_enable()
2153 ret = clk_prepare_enable(tx->mclk); in swclk_gate_enable()
2155 dev_err(tx->dev, "failed to enable mclk\n"); in swclk_gate_enable()
2159 tx_macro_mclk_enable(tx, true); in swclk_gate_enable()
2169 struct tx_macro *tx = to_tx_macro(hw); in swclk_gate_disable() local
2170 struct regmap *regmap = tx->regmap; in swclk_gate_disable()
2175 tx_macro_mclk_enable(tx, false); in swclk_gate_disable()
2176 clk_disable_unprepare(tx->mclk); in swclk_gate_disable()
2181 struct tx_macro *tx = to_tx_macro(hw); in swclk_gate_is_enabled() local
2184 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
2204 static int tx_macro_register_mclk_output(struct tx_macro *tx) in tx_macro_register_mclk_output() argument
2206 struct device *dev = tx->dev; in tx_macro_register_mclk_output()
2208 const char *clk_name = "lpass-tx-mclk"; in tx_macro_register_mclk_output()
2213 if (tx->npl) in tx_macro_register_mclk_output()
2214 parent_clk_name = __clk_get_name(tx->npl); in tx_macro_register_mclk_output()
2216 parent_clk_name = __clk_get_name(tx->mclk); in tx_macro_register_mclk_output()
2223 tx->hw.init = &init; in tx_macro_register_mclk_output()
2224 hw = &tx->hw; in tx_macro_register_mclk_output()
2247 struct tx_macro *tx; in tx_macro_probe() local
2251 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL); in tx_macro_probe()
2252 if (!tx) in tx_macro_probe()
2255 tx->data = device_get_match_data(dev); in tx_macro_probe()
2257 tx->macro = devm_clk_get_optional(dev, "macro"); in tx_macro_probe()
2258 if (IS_ERR(tx->macro)) in tx_macro_probe()
2259 return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n"); in tx_macro_probe()
2261 tx->dcodec = devm_clk_get_optional(dev, "dcodec"); in tx_macro_probe()
2262 if (IS_ERR(tx->dcodec)) in tx_macro_probe()
2263 return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n"); in tx_macro_probe()
2265 tx->mclk = devm_clk_get(dev, "mclk"); in tx_macro_probe()
2266 if (IS_ERR(tx->mclk)) in tx_macro_probe()
2267 return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n"); in tx_macro_probe()
2269 if (tx->data->flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) { in tx_macro_probe()
2270 tx->npl = devm_clk_get(dev, "npl"); in tx_macro_probe()
2271 if (IS_ERR(tx->npl)) in tx_macro_probe()
2272 return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n"); in tx_macro_probe()
2275 tx->fsgen = devm_clk_get(dev, "fsgen"); in tx_macro_probe()
2276 if (IS_ERR(tx->fsgen)) in tx_macro_probe()
2277 return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n"); in tx_macro_probe()
2279 tx->pds = lpass_macro_pds_init(dev); in tx_macro_probe()
2280 if (IS_ERR(tx->pds)) in tx_macro_probe()
2281 return PTR_ERR(tx->pds); in tx_macro_probe()
2290 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) { in tx_macro_probe()
2303 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config); in tx_macro_probe()
2304 if (IS_ERR(tx->regmap)) { in tx_macro_probe()
2305 ret = PTR_ERR(tx->regmap); in tx_macro_probe()
2309 dev_set_drvdata(dev, tx); in tx_macro_probe()
2311 tx->dev = dev; in tx_macro_probe()
2314 tx->active_decimator[TX_MACRO_AIF1_CAP] = -1; in tx_macro_probe()
2315 tx->active_decimator[TX_MACRO_AIF2_CAP] = -1; in tx_macro_probe()
2316 tx->active_decimator[TX_MACRO_AIF3_CAP] = -1; in tx_macro_probe()
2319 clk_set_rate(tx->mclk, MCLK_FREQ); in tx_macro_probe()
2320 clk_set_rate(tx->npl, MCLK_FREQ); in tx_macro_probe()
2322 ret = clk_prepare_enable(tx->macro); in tx_macro_probe()
2326 ret = clk_prepare_enable(tx->dcodec); in tx_macro_probe()
2330 ret = clk_prepare_enable(tx->mclk); in tx_macro_probe()
2334 ret = clk_prepare_enable(tx->npl); in tx_macro_probe()
2338 ret = clk_prepare_enable(tx->fsgen); in tx_macro_probe()
2344 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) in tx_macro_probe()
2345 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2348 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2352 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR) in tx_macro_probe()
2353 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, in tx_macro_probe()
2368 ret = tx_macro_register_mclk_output(tx); in tx_macro_probe()
2375 clk_disable_unprepare(tx->fsgen); in tx_macro_probe()
2377 clk_disable_unprepare(tx->npl); in tx_macro_probe()
2379 clk_disable_unprepare(tx->mclk); in tx_macro_probe()
2381 clk_disable_unprepare(tx->dcodec); in tx_macro_probe()
2383 clk_disable_unprepare(tx->macro); in tx_macro_probe()
2385 lpass_macro_pds_exit(tx->pds); in tx_macro_probe()
2392 struct tx_macro *tx = dev_get_drvdata(&pdev->dev); in tx_macro_remove() local
2394 clk_disable_unprepare(tx->macro); in tx_macro_remove()
2395 clk_disable_unprepare(tx->dcodec); in tx_macro_remove()
2396 clk_disable_unprepare(tx->mclk); in tx_macro_remove()
2397 clk_disable_unprepare(tx->npl); in tx_macro_remove()
2398 clk_disable_unprepare(tx->fsgen); in tx_macro_remove()
2400 lpass_macro_pds_exit(tx->pds); in tx_macro_remove()
2405 struct tx_macro *tx = dev_get_drvdata(dev); in tx_macro_runtime_suspend() local
2407 regcache_cache_only(tx->regmap, true); in tx_macro_runtime_suspend()
2408 regcache_mark_dirty(tx->regmap); in tx_macro_runtime_suspend()
2410 clk_disable_unprepare(tx->fsgen); in tx_macro_runtime_suspend()
2411 clk_disable_unprepare(tx->npl); in tx_macro_runtime_suspend()
2412 clk_disable_unprepare(tx->mclk); in tx_macro_runtime_suspend()
2419 struct tx_macro *tx = dev_get_drvdata(dev); in tx_macro_runtime_resume() local
2422 ret = clk_prepare_enable(tx->mclk); in tx_macro_runtime_resume()
2428 ret = clk_prepare_enable(tx->npl); in tx_macro_runtime_resume()
2434 ret = clk_prepare_enable(tx->fsgen); in tx_macro_runtime_resume()
2440 regcache_cache_only(tx->regmap, false); in tx_macro_runtime_resume()
2441 regcache_sync(tx->regmap); in tx_macro_runtime_resume()
2445 clk_disable_unprepare(tx->npl); in tx_macro_runtime_resume()
2447 clk_disable_unprepare(tx->mclk); in tx_macro_runtime_resume()
2502 .compatible = "qcom,sc7280-lpass-tx-macro",
2505 .compatible = "qcom,sm6115-lpass-tx-macro",
2508 .compatible = "qcom,sm8250-lpass-tx-macro",
2511 .compatible = "qcom,sm8450-lpass-tx-macro",
2514 .compatible = "qcom,sm8550-lpass-tx-macro",
2517 .compatible = "qcom,sc8280xp-lpass-tx-macro",
2542 MODULE_DESCRIPTION("TX macro driver");