Lines Matching +full:0 +full:x078c
19 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
20 #define CDC_TX_MCLK_EN_MASK BIT(0)
21 #define CDC_TX_MCLK_ENABLE BIT(0)
22 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
23 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE BIT(0)
25 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
28 #define CDC_TX_SWR_CLK_EN_MASK BIT(0)
29 #define CDC_TX_SWR_CLK_ENABLE BIT(0)
30 #define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
31 #define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
32 #define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
33 #define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
34 #define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
35 #define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
36 #define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
37 #define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
38 #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
39 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
40 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
42 #define CDC_TX_SWR_MIC_CLK_DEFAULT 0
44 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
45 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
46 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
47 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
48 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
49 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
50 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
52 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
53 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
54 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
55 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
56 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
57 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
58 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
59 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
60 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
61 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
62 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
63 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
64 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
65 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
66 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
67 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
68 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
69 #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
70 #define CDC_TX_ANC0_MODE_1_CTL (0x0204)
71 #define CDC_TX_ANC0_MODE_2_CTL (0x0208)
72 #define CDC_TX_ANC0_FF_SHIFT (0x020C)
73 #define CDC_TX_ANC0_FB_SHIFT (0x0210)
74 #define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
75 #define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
76 #define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
77 #define CDC_TX_ANC0_SMLPF_CTL (0x0220)
78 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
79 #define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
80 #define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
81 #define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
82 #define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
83 #define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
84 #define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
85 #define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
86 #define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
89 #define CDC_TX0_TX_PATH_CTL (0x0400)
90 #define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
91 #define CDC_TX0_TX_PATH_CFG0 (0x0404)
92 #define CDC_TXn_PH_EN_MASK BIT(0)
96 #define CDC_TX0_TX_PATH_CFG1 (0x0408)
97 #define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
98 #define CDC_TX0_TX_VOL_CTL (0x040C)
99 #define CDC_TX0_TX_PATH_SEC0 (0x0410)
100 #define CDC_TX0_TX_PATH_SEC1 (0x0414)
101 #define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
103 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
104 #define CDC_TX0_TX_PATH_SEC2 (0x0418)
105 #define CDC_TX0_TX_PATH_SEC3 (0x041C)
106 #define CDC_TX0_TX_PATH_SEC4 (0x0420)
107 #define CDC_TX0_TX_PATH_SEC5 (0x0424)
108 #define CDC_TX0_TX_PATH_SEC6 (0x0428)
109 #define CDC_TX0_TX_PATH_SEC7 (0x042C)
111 #define CDC_TX1_TX_PATH_CTL (0x0480)
112 #define CDC_TX1_TX_PATH_CFG0 (0x0484)
113 #define CDC_TX1_TX_PATH_CFG1 (0x0488)
114 #define CDC_TX1_TX_VOL_CTL (0x048C)
115 #define CDC_TX1_TX_PATH_SEC0 (0x0490)
116 #define CDC_TX1_TX_PATH_SEC1 (0x0494)
117 #define CDC_TX1_TX_PATH_SEC2 (0x0498)
118 #define CDC_TX1_TX_PATH_SEC3 (0x049C)
119 #define CDC_TX1_TX_PATH_SEC4 (0x04A0)
120 #define CDC_TX1_TX_PATH_SEC5 (0x04A4)
121 #define CDC_TX1_TX_PATH_SEC6 (0x04A8)
122 #define CDC_TX2_TX_PATH_CTL (0x0500)
123 #define CDC_TX2_TX_PATH_CFG0 (0x0504)
124 #define CDC_TX2_TX_PATH_CFG1 (0x0508)
125 #define CDC_TX2_TX_VOL_CTL (0x050C)
126 #define CDC_TX2_TX_PATH_SEC0 (0x0510)
127 #define CDC_TX2_TX_PATH_SEC1 (0x0514)
128 #define CDC_TX2_TX_PATH_SEC2 (0x0518)
129 #define CDC_TX2_TX_PATH_SEC3 (0x051C)
130 #define CDC_TX2_TX_PATH_SEC4 (0x0520)
131 #define CDC_TX2_TX_PATH_SEC5 (0x0524)
132 #define CDC_TX2_TX_PATH_SEC6 (0x0528)
133 #define CDC_TX3_TX_PATH_CTL (0x0580)
134 #define CDC_TX3_TX_PATH_CFG0 (0x0584)
135 #define CDC_TX3_TX_PATH_CFG1 (0x0588)
136 #define CDC_TX3_TX_VOL_CTL (0x058C)
137 #define CDC_TX3_TX_PATH_SEC0 (0x0590)
138 #define CDC_TX3_TX_PATH_SEC1 (0x0594)
139 #define CDC_TX3_TX_PATH_SEC2 (0x0598)
140 #define CDC_TX3_TX_PATH_SEC3 (0x059C)
141 #define CDC_TX3_TX_PATH_SEC4 (0x05A0)
142 #define CDC_TX3_TX_PATH_SEC5 (0x05A4)
143 #define CDC_TX3_TX_PATH_SEC6 (0x05A8)
144 #define CDC_TX4_TX_PATH_CTL (0x0600)
145 #define CDC_TX4_TX_PATH_CFG0 (0x0604)
146 #define CDC_TX4_TX_PATH_CFG1 (0x0608)
147 #define CDC_TX4_TX_VOL_CTL (0x060C)
148 #define CDC_TX4_TX_PATH_SEC0 (0x0610)
149 #define CDC_TX4_TX_PATH_SEC1 (0x0614)
150 #define CDC_TX4_TX_PATH_SEC2 (0x0618)
151 #define CDC_TX4_TX_PATH_SEC3 (0x061C)
152 #define CDC_TX4_TX_PATH_SEC4 (0x0620)
153 #define CDC_TX4_TX_PATH_SEC5 (0x0624)
154 #define CDC_TX4_TX_PATH_SEC6 (0x0628)
155 #define CDC_TX5_TX_PATH_CTL (0x0680)
156 #define CDC_TX5_TX_PATH_CFG0 (0x0684)
157 #define CDC_TX5_TX_PATH_CFG1 (0x0688)
158 #define CDC_TX5_TX_VOL_CTL (0x068C)
159 #define CDC_TX5_TX_PATH_SEC0 (0x0690)
160 #define CDC_TX5_TX_PATH_SEC1 (0x0694)
161 #define CDC_TX5_TX_PATH_SEC2 (0x0698)
162 #define CDC_TX5_TX_PATH_SEC3 (0x069C)
163 #define CDC_TX5_TX_PATH_SEC4 (0x06A0)
164 #define CDC_TX5_TX_PATH_SEC5 (0x06A4)
165 #define CDC_TX5_TX_PATH_SEC6 (0x06A8)
166 #define CDC_TX6_TX_PATH_CTL (0x0700)
167 #define CDC_TX6_TX_PATH_CFG0 (0x0704)
168 #define CDC_TX6_TX_PATH_CFG1 (0x0708)
169 #define CDC_TX6_TX_VOL_CTL (0x070C)
170 #define CDC_TX6_TX_PATH_SEC0 (0x0710)
171 #define CDC_TX6_TX_PATH_SEC1 (0x0714)
172 #define CDC_TX6_TX_PATH_SEC2 (0x0718)
173 #define CDC_TX6_TX_PATH_SEC3 (0x071C)
174 #define CDC_TX6_TX_PATH_SEC4 (0x0720)
175 #define CDC_TX6_TX_PATH_SEC5 (0x0724)
176 #define CDC_TX6_TX_PATH_SEC6 (0x0728)
177 #define CDC_TX7_TX_PATH_CTL (0x0780)
178 #define CDC_TX7_TX_PATH_CFG0 (0x0784)
179 #define CDC_TX7_TX_PATH_CFG1 (0x0788)
180 #define CDC_TX7_TX_VOL_CTL (0x078C)
181 #define CDC_TX7_TX_PATH_SEC0 (0x0790)
182 #define CDC_TX7_TX_PATH_SEC1 (0x0794)
183 #define CDC_TX7_TX_PATH_SEC2 (0x0798)
184 #define CDC_TX7_TX_PATH_SEC3 (0x079C)
185 #define CDC_TX7_TX_PATH_SEC4 (0x07A0)
186 #define CDC_TX7_TX_PATH_SEC5 (0x07A4)
187 #define CDC_TX7_TX_PATH_SEC6 (0x07A8)
188 #define TX_MAX_OFFSET (0x07A8)
197 #define CF_MIN_3DB_4HZ 0x0
198 #define CF_MIN_3DB_75HZ 0x1
199 #define CF_MIN_3DB_150HZ 0x2
295 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
296 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
297 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
298 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
299 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
300 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
301 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
302 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
303 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
304 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
305 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
306 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
307 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
308 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
309 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
310 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
311 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
312 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
313 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
314 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
315 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
316 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
317 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
318 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
319 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
320 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
321 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
322 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
323 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
324 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
325 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
326 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
327 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
328 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
329 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
330 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
331 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
332 { CDC_TX_ANC0_FF_SHIFT, 0x00},
333 { CDC_TX_ANC0_FB_SHIFT, 0x00},
334 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
335 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
336 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
337 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
338 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
339 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
340 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
341 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
342 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
343 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
344 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
345 { CDC_TX0_TX_PATH_CTL, 0x04},
346 { CDC_TX0_TX_PATH_CFG0, 0x10},
347 { CDC_TX0_TX_PATH_CFG1, 0x0B},
348 { CDC_TX0_TX_VOL_CTL, 0x00},
349 { CDC_TX0_TX_PATH_SEC0, 0x00},
350 { CDC_TX0_TX_PATH_SEC1, 0x00},
351 { CDC_TX0_TX_PATH_SEC2, 0x01},
352 { CDC_TX0_TX_PATH_SEC3, 0x3C},
353 { CDC_TX0_TX_PATH_SEC4, 0x20},
354 { CDC_TX0_TX_PATH_SEC5, 0x00},
355 { CDC_TX0_TX_PATH_SEC6, 0x00},
356 { CDC_TX0_TX_PATH_SEC7, 0x25},
357 { CDC_TX1_TX_PATH_CTL, 0x04},
358 { CDC_TX1_TX_PATH_CFG0, 0x10},
359 { CDC_TX1_TX_PATH_CFG1, 0x0B},
360 { CDC_TX1_TX_VOL_CTL, 0x00},
361 { CDC_TX1_TX_PATH_SEC0, 0x00},
362 { CDC_TX1_TX_PATH_SEC1, 0x00},
363 { CDC_TX1_TX_PATH_SEC2, 0x01},
364 { CDC_TX1_TX_PATH_SEC3, 0x3C},
365 { CDC_TX1_TX_PATH_SEC4, 0x20},
366 { CDC_TX1_TX_PATH_SEC5, 0x00},
367 { CDC_TX1_TX_PATH_SEC6, 0x00},
368 { CDC_TX2_TX_PATH_CTL, 0x04},
369 { CDC_TX2_TX_PATH_CFG0, 0x10},
370 { CDC_TX2_TX_PATH_CFG1, 0x0B},
371 { CDC_TX2_TX_VOL_CTL, 0x00},
372 { CDC_TX2_TX_PATH_SEC0, 0x00},
373 { CDC_TX2_TX_PATH_SEC1, 0x00},
374 { CDC_TX2_TX_PATH_SEC2, 0x01},
375 { CDC_TX2_TX_PATH_SEC3, 0x3C},
376 { CDC_TX2_TX_PATH_SEC4, 0x20},
377 { CDC_TX2_TX_PATH_SEC5, 0x00},
378 { CDC_TX2_TX_PATH_SEC6, 0x00},
379 { CDC_TX3_TX_PATH_CTL, 0x04},
380 { CDC_TX3_TX_PATH_CFG0, 0x10},
381 { CDC_TX3_TX_PATH_CFG1, 0x0B},
382 { CDC_TX3_TX_VOL_CTL, 0x00},
383 { CDC_TX3_TX_PATH_SEC0, 0x00},
384 { CDC_TX3_TX_PATH_SEC1, 0x00},
385 { CDC_TX3_TX_PATH_SEC2, 0x01},
386 { CDC_TX3_TX_PATH_SEC3, 0x3C},
387 { CDC_TX3_TX_PATH_SEC4, 0x20},
388 { CDC_TX3_TX_PATH_SEC5, 0x00},
389 { CDC_TX3_TX_PATH_SEC6, 0x00},
390 { CDC_TX4_TX_PATH_CTL, 0x04},
391 { CDC_TX4_TX_PATH_CFG0, 0x10},
392 { CDC_TX4_TX_PATH_CFG1, 0x0B},
393 { CDC_TX4_TX_VOL_CTL, 0x00},
394 { CDC_TX4_TX_PATH_SEC0, 0x00},
395 { CDC_TX4_TX_PATH_SEC1, 0x00},
396 { CDC_TX4_TX_PATH_SEC2, 0x01},
397 { CDC_TX4_TX_PATH_SEC3, 0x3C},
398 { CDC_TX4_TX_PATH_SEC4, 0x20},
399 { CDC_TX4_TX_PATH_SEC5, 0x00},
400 { CDC_TX4_TX_PATH_SEC6, 0x00},
401 { CDC_TX5_TX_PATH_CTL, 0x04},
402 { CDC_TX5_TX_PATH_CFG0, 0x10},
403 { CDC_TX5_TX_PATH_CFG1, 0x0B},
404 { CDC_TX5_TX_VOL_CTL, 0x00},
405 { CDC_TX5_TX_PATH_SEC0, 0x00},
406 { CDC_TX5_TX_PATH_SEC1, 0x00},
407 { CDC_TX5_TX_PATH_SEC2, 0x01},
408 { CDC_TX5_TX_PATH_SEC3, 0x3C},
409 { CDC_TX5_TX_PATH_SEC4, 0x20},
410 { CDC_TX5_TX_PATH_SEC5, 0x00},
411 { CDC_TX5_TX_PATH_SEC6, 0x00},
412 { CDC_TX6_TX_PATH_CTL, 0x04},
413 { CDC_TX6_TX_PATH_CFG0, 0x10},
414 { CDC_TX6_TX_PATH_CFG1, 0x0B},
415 { CDC_TX6_TX_VOL_CTL, 0x00},
416 { CDC_TX6_TX_PATH_SEC0, 0x00},
417 { CDC_TX6_TX_PATH_SEC1, 0x00},
418 { CDC_TX6_TX_PATH_SEC2, 0x01},
419 { CDC_TX6_TX_PATH_SEC3, 0x3C},
420 { CDC_TX6_TX_PATH_SEC4, 0x20},
421 { CDC_TX6_TX_PATH_SEC5, 0x00},
422 { CDC_TX6_TX_PATH_SEC6, 0x00},
423 { CDC_TX7_TX_PATH_CTL, 0x04},
424 { CDC_TX7_TX_PATH_CFG0, 0x10},
425 { CDC_TX7_TX_PATH_CFG1, 0x0B},
426 { CDC_TX7_TX_VOL_CTL, 0x00},
427 { CDC_TX7_TX_PATH_SEC0, 0x00},
428 { CDC_TX7_TX_PATH_SEC1, 0x00},
429 { CDC_TX7_TX_PATH_SEC2, 0x01},
430 { CDC_TX7_TX_PATH_SEC3, 0x3C},
431 { CDC_TX7_TX_PATH_SEC4, 0x20},
432 { CDC_TX7_TX_PATH_SEC5, 0x00},
433 { CDC_TX7_TX_PATH_SEC6, 0x00},
619 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
620 /* 9.6MHz MCLK, set value 0x00 if other frequency */ in tx_macro_mclk_enable()
621 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); in tx_macro_mclk_enable()
633 if (tx->tx_mclk_users <= 0) { in tx_macro_mclk_enable()
635 tx->tx_mclk_users = 0; in tx_macro_mclk_enable()
639 if (tx->tx_mclk_users == 0) { in tx_macro_mclk_enable()
641 CDC_TX_FS_CNT_EN_MASK, 0x0); in tx_macro_mclk_enable()
643 CDC_TX_MCLK_EN_MASK, 0x0); in tx_macro_mclk_enable()
647 return 0; in tx_macro_mclk_enable()
698 0x02); in tx_macro_tx_hpf_corner_freq_callback()
702 0x01); in tx_macro_tx_hpf_corner_freq_callback()
708 CDC_TXn_HPF_F_CHANGE_MASK, 0x1); in tx_macro_tx_hpf_corner_freq_callback()
712 CDC_TXn_HPF_F_CHANGE_MASK, 0x0); in tx_macro_tx_hpf_corner_freq_callback()
731 CDC_TXn_PGA_MUTE_MASK, 0x0); in tx_macro_mute_update_callback()
751 return 0; in tx_macro_mclk_event()
764 CDC_TXn_ADC_DMIC_SEL_MASK, 0); in tx_macro_update_smic_sel_v9()
796 CDC_TXn_ADC_DMIC_SEL_MASK, 0); in tx_macro_update_smic_sel_v9_2()
810 val = ucontrol->value.enumerated.item[0]; in tx_macro_put_dec_enum()
844 if (val != 0) { in tx_macro_put_dec_enum()
870 ucontrol->value.integer.value[0] = 1; in tx_macro_tx_mixer_get()
872 ucontrol->value.integer.value[0] = 0; in tx_macro_tx_mixer_get()
874 return 0; in tx_macro_tx_mixer_get()
886 u32 enable = ucontrol->value.integer.value[0]; in tx_macro_tx_mixer_put()
891 return 0; in tx_macro_tx_mixer_put()
898 return 0; in tx_macro_tx_mixer_put()
949 CDC_TXn_PGA_MUTE_MASK, 0x1); in tx_macro_enable_dec()
953 CDC_TXn_CLK_EN_MASK, 0x1); in tx_macro_enable_dec()
955 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00); in tx_macro_enable_dec()
985 0x02); in tx_macro_enable_dec()
990 0x00); in tx_macro_enable_dec()
994 0x01); in tx_macro_enable_dec()
1007 0x01, 0x01); in tx_macro_enable_dec()
1015 CDC_TXn_PGA_MUTE_MASK, 0x1); in tx_macro_enable_dec()
1028 0x02); in tx_macro_enable_dec()
1034 0x03); in tx_macro_enable_dec()
1044 0x1); in tx_macro_enable_dec()
1051 CDC_TXn_CLK_EN_MASK, 0x0); in tx_macro_enable_dec()
1053 CDC_TXn_ADC_MODE_MASK, 0x0); in tx_macro_enable_dec()
1055 CDC_TXn_PGA_MUTE_MASK, 0x0); in tx_macro_enable_dec()
1058 CDC_TXn_PH_EN_MASK, 0x0); in tx_macro_enable_dec()
1062 0x0); in tx_macro_enable_dec()
1067 return 0; in tx_macro_enable_dec()
1078 ucontrol->value.integer.value[0] = tx->dec_mode[path]; in tx_macro_dec_mode_get()
1080 return 0; in tx_macro_dec_mode_get()
1087 int value = ucontrol->value.integer.value[0]; in tx_macro_dec_mode_put()
1093 return 0; in tx_macro_dec_mode_put()
1106 ucontrol->value.integer.value[0] = tx->bcs_enable; in tx_macro_get_bcs()
1108 return 0; in tx_macro_get_bcs()
1115 int value = ucontrol->value.integer.value[0]; in tx_macro_set_bcs()
1120 return 0; in tx_macro_set_bcs()
1136 tx_fs_rate = 0; in tx_macro_hw_params()
1166 return 0; in tx_macro_hw_params()
1186 return 0; in tx_macro_get_channel_map()
1197 return 0; in tx_macro_digital_mute()
1204 CDC_TXn_PGA_MUTE_MASK, 0x1); in tx_macro_digital_mute()
1208 CDC_TXn_PGA_MUTE_MASK, 0x0); in tx_macro_digital_mute()
1210 return 0; in tx_macro_digital_mute()
1269 0, adc_mux_text);
1271 0, adc_mux_text);
1273 0, adc_mux_text);
1275 0, adc_mux_text);
1277 0, adc_mux_text);
1279 0, adc_mux_text);
1281 0, adc_mux_text);
1283 0, adc_mux_text);
1345 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1364 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1366 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1368 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1370 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1372 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1374 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1376 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1378 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1383 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1385 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1387 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1389 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1391 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1393 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1395 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1397 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1402 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1404 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1406 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1408 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1410 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1412 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1414 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1416 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1421 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1422 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1424 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1425 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1427 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1428 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1430 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1433 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1436 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1439 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1440 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1441 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1442 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1443 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1444 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1445 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1446 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1458 TX_MACRO_DEC0, 0,
1464 TX_MACRO_DEC1, 0,
1470 TX_MACRO_DEC2, 0,
1476 TX_MACRO_DEC3, 0,
1482 TX_MACRO_DEC4, 0,
1488 TX_MACRO_DEC5, 0,
1494 TX_MACRO_DEC6, 0,
1500 TX_MACRO_DEC7, 0,
1505 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1508 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1510 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1511 NULL, 0),
1648 0, smic_mux_text_v9);
1651 0, smic_mux_text_v9);
1654 0, smic_mux_text_v9);
1657 0, smic_mux_text_v9);
1660 0, smic_mux_text_v9);
1663 0, smic_mux_text_v9);
1666 0, smic_mux_text_v9);
1669 0, smic_mux_text_v9);
1689 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9),
1690 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9),
1691 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9),
1692 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9),
1693 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9),
1694 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9),
1695 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9),
1696 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9),
1842 0, smic_mux_text_v9_2);
1845 0, smic_mux_text_v9_2);
1848 0, smic_mux_text_v9_2);
1851 0, smic_mux_text_v9_2);
1854 0, smic_mux_text_v9_2);
1857 0, smic_mux_text_v9_2);
1860 0, smic_mux_text_v9_2);
1863 0, smic_mux_text_v9_2);
1883 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_2),
1884 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_2),
1885 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_2),
1886 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_2),
1887 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_2),
1888 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_2),
1889 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_2),
1890 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_2),
2054 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
2078 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
2106 return 0; in tx_macro_component_extend()
2120 for (i = 0; i < NUM_DECIMATORS; i++) { in tx_macro_component_probe()
2127 for (i = 0; i < NUM_DECIMATORS; i++) { in tx_macro_component_probe()
2135 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F, in tx_macro_component_probe()
2136 0x0A); in tx_macro_component_probe()
2143 return 0; in tx_macro_component_probe()
2163 return 0; in swclk_gate_enable()
2172 CDC_TX_SWR_CLK_EN_MASK, 0x0); in swclk_gate_disable()
2184 ret = val & BIT(0); in swclk_gate_is_enabled()
2219 init.flags = 0; in tx_macro_register_mclk_output()
2282 base = devm_platform_ioremap_resource(pdev, 0); in tx_macro_probe()
2290 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) { in tx_macro_probe()
2294 tx_defaults[reg].def = 0x0E; in tx_macro_probe()
2353 CDC_TX_SWR_RESET_MASK, 0x0); in tx_macro_probe()
2371 return 0; in tx_macro_probe()
2413 return 0; in tx_macro_runtime_suspend()
2442 return 0; in tx_macro_runtime_resume()