Lines Matching +full:sm8250 +full:- +full:lpass +full:- +full:tx +full:- +full:macro
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
14 #include <sound/soc-dapm.h>
17 #include <linux/clk-provider.h>
19 #include "lpass-macro-common.h"
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n)
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n)
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n)
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n)
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n)
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n)
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n)
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n)
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n)
206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
269 /* LPASS CODEC version 2.5 rx reg offsets */
665 struct clk *macro; member
678 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
889 /* RX Macro */
1243 /* Update volatile list for rx/tx macros */ in rx_is_volatile_register()
1604 switch (rx->codec_version) { in rx_is_rw_register()
1686 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_int_dem_inp_mux_put()
1688 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_int_dem_inp_mux_put()
1692 val = ucontrol->value.enumerated.item[0]; in rx_macro_int_dem_inp_mux_put()
1694 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) in rx_macro_int_dem_inp_mux_put()
1696 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) in rx_macro_int_dem_inp_mux_put()
1731 struct snd_soc_component *component = dai->component; in rx_macro_set_prim_interpolator_rate()
1734 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1776 struct snd_soc_component *component = dai->component; in rx_macro_set_mix_interpolator_rate()
1779 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1822 struct snd_soc_component *component = dai->component; in rx_macro_hw_params()
1826 switch (substream->stream) { in rx_macro_hw_params()
1830 dev_err(component->dev, "%s: cannot set sample rate: %u\n", in rx_macro_hw_params()
1834 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1846 struct snd_soc_component *component = dai->component; in rx_macro_get_channel_map()
1850 switch (dai->id) { in rx_macro_get_channel_map()
1855 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1862 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1863 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1864 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 in rx_macro_get_channel_map()
1865 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 in rx_macro_get_channel_map()
1876 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1898 dev_err(component->dev, "%s: Invalid AIF\n", __func__); in rx_macro_get_channel_map()
1906 struct snd_soc_component *component = dai->component; in rx_macro_digital_mute()
1912 switch (dai->id) { in rx_macro_digital_mute()
2039 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
2042 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2056 rx->rx_mclk_users++; in rx_macro_mclk_enable()
2058 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
2059 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
2060 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
2063 rx->rx_mclk_users--; in rx_macro_mclk_enable()
2064 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2080 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_mclk_event()
2092 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); in rx_macro_mclk_event()
2093 ret = -EINVAL; in rx_macro_mclk_event()
2141 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_main_path()
2145 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); in rx_macro_enable_main_path()
2146 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); in rx_macro_enable_main_path()
2150 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2151 if (rx_macro_adie_lb(component, w->shift)) in rx_macro_enable_main_path()
2161 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2195 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2236 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2250 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2269 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2272 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2274 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2275 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2285 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2310 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2326 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2327 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2329 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2330 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2358 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2374 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2439 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_get_compander()
2442 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2450 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_set_compander()
2451 int value = ucontrol->value.integer.value[0]; in rx_macro_set_compander()
2454 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2463 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_get()
2466 ucontrol->value.enumerated.item[0] = in rx_macro_mux_get()
2467 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2475 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_put()
2476 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_mux_put()
2478 u32 rx_port_value = ucontrol->value.enumerated.item[0]; in rx_macro_mux_put()
2483 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2488 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); in rx_macro_mux_put()
2492 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2500 dai_id = aif_rst - 1; in rx_macro_mux_put()
2501 if (rx->active_ch_cnt[dai_id]) { in rx_macro_mux_put()
2502 clear_bit(widget->shift, &rx->active_ch_mask[dai_id]); in rx_macro_mux_put()
2503 rx->active_ch_cnt[dai_id]--; in rx_macro_mux_put()
2511 dai_id = rx_port_value - 1; in rx_macro_mux_put()
2512 set_bit(widget->shift, &rx->active_ch_mask[dai_id]); in rx_macro_mux_put()
2513 rx->active_ch_cnt[dai_id]++; in rx_macro_mux_put()
2516 dev_err(component->dev, in rx_macro_mux_put()
2522 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, in rx_macro_mux_put()
2526 return -EINVAL; in rx_macro_mux_put()
2554 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2564 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2574 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2584 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2594 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2604 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2614 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2625 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2636 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2647 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2669 return -EINVAL; in rx_macro_hphdelay_lutbypass()
2674 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2686 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2715 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2724 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2734 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2738 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2739 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2740 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2767 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2772 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2778 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_mix_path()
2782 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2783 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2787 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2797 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2813 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_rx_path_clk()
2818 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2819 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2821 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), in rx_macro_enable_rx_path_clk()
2825 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2827 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2838 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_set_iir_gain()
2843 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { in rx_macro_set_iir_gain()
2925 /* Mask top 2 bits, 7-8 are reserved */ in set_iir_band_coeff()
2936 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_put_iir_band_audio_mixer()
2937 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_put_iir_band_audio_mixer()
2938 int iir_idx = ctl->iir_idx; in rx_macro_put_iir_band_audio_mixer()
2939 int band_idx = ctl->band_idx; in rx_macro_put_iir_band_audio_mixer()
2943 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); in rx_macro_put_iir_band_audio_mixer()
2965 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_get_iir_band_audio_mixer()
2966 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_get_iir_band_audio_mixer()
2967 int iir_idx = ctl->iir_idx; in rx_macro_get_iir_band_audio_mixer()
2968 int band_idx = ctl->band_idx; in rx_macro_get_iir_band_audio_mixer()
2977 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); in rx_macro_get_iir_band_audio_mixer()
2986 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_iir_filter_info()
2987 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_iir_filter_info()
2989 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in rx_macro_iir_filter_info()
2990 ucontrol->count = params->max; in rx_macro_iir_filter_info()
2997 -84, 40, digital_gain),
2999 -84, 40, digital_gain),
3001 -84, 40, digital_gain),
3003 -84, 40, digital_gain),
3009 -84, 40, digital_gain),
3011 -84, 40, digital_gain),
3013 -84, 40, digital_gain),
3015 -84, 40, digital_gain),
3020 -84, 40, digital_gain),
3022 -84, 40, digital_gain),
3045 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3048 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3051 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3054 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3057 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3060 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3063 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3066 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3108 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_echo()
3110 int ec_tx = -1; in rx_macro_enable_echo()
3115 ec_tx = ((val & 0xf0) >> 0x4) - 1; in rx_macro_enable_echo()
3117 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3122 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3125 dev_err(component->dev, "%s: EC mix control not set correctly\n", in rx_macro_enable_echo()
3127 return -EINVAL; in rx_macro_enable_echo()
3622 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3643 switch (rx->codec_version) { in rx_macro_component_probe()
3664 return -EINVAL; in rx_macro_component_probe()
3667 rx->component = component; in rx_macro_component_probe()
3681 ret = clk_prepare_enable(rx->mclk); in swclk_gate_enable()
3683 dev_err(rx->dev, "unable to prepare mclk\n"); in swclk_gate_enable()
3689 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3699 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3703 clk_disable_unprepare(rx->mclk); in swclk_gate_disable()
3711 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3733 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3735 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3740 if (rx->npl) in rx_macro_register_mclk_output()
3741 parent_clk_name = __clk_get_name(rx->npl); in rx_macro_register_mclk_output()
3743 parent_clk_name = __clk_get_name(rx->mclk); in rx_macro_register_mclk_output()
3750 rx->hw.init = &init; in rx_macro_register_mclk_output()
3751 hw = &rx->hw; in rx_macro_register_mclk_output()
3752 ret = devm_clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3760 .name = "RX-MACRO",
3772 struct device *dev = &pdev->dev; in rx_macro_probe()
3782 return -ENOMEM; in rx_macro_probe()
3784 rx->macro = devm_clk_get_optional(dev, "macro"); in rx_macro_probe()
3785 if (IS_ERR(rx->macro)) in rx_macro_probe()
3786 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); in rx_macro_probe()
3788 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); in rx_macro_probe()
3789 if (IS_ERR(rx->dcodec)) in rx_macro_probe()
3790 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); in rx_macro_probe()
3792 rx->mclk = devm_clk_get(dev, "mclk"); in rx_macro_probe()
3793 if (IS_ERR(rx->mclk)) in rx_macro_probe()
3794 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); in rx_macro_probe()
3797 rx->npl = devm_clk_get(dev, "npl"); in rx_macro_probe()
3798 if (IS_ERR(rx->npl)) in rx_macro_probe()
3799 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); in rx_macro_probe()
3802 rx->fsgen = devm_clk_get(dev, "fsgen"); in rx_macro_probe()
3803 if (IS_ERR(rx->fsgen)) in rx_macro_probe()
3804 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); in rx_macro_probe()
3806 rx->pds = lpass_macro_pds_init(dev); in rx_macro_probe()
3807 if (IS_ERR(rx->pds)) in rx_macro_probe()
3808 return PTR_ERR(rx->pds); in rx_macro_probe()
3810 ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds); in rx_macro_probe()
3818 rx->codec_version = lpass_macro_get_codec_version(); in rx_macro_probe()
3821 switch (rx->codec_version) { in rx_macro_probe()
3827 rx->rxn_reg_stride = 0x80; in rx_macro_probe()
3828 rx->rxn_reg_stride2 = 0xc; in rx_macro_probe()
3832 return -ENOMEM; in rx_macro_probe()
3841 rx->rxn_reg_stride = 0xc0; in rx_macro_probe()
3842 rx->rxn_reg_stride2 = 0x0; in rx_macro_probe()
3846 return -ENOMEM; in rx_macro_probe()
3852 dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version); in rx_macro_probe()
3853 return -EINVAL; in rx_macro_probe()
3860 return -ENOMEM; in rx_macro_probe()
3862 reg_config->reg_defaults = reg_defaults; in rx_macro_probe()
3863 reg_config->num_reg_defaults = def_count; in rx_macro_probe()
3865 rx->regmap = devm_regmap_init_mmio(dev, base, reg_config); in rx_macro_probe()
3866 if (IS_ERR(rx->regmap)) in rx_macro_probe()
3867 return PTR_ERR(rx->regmap); in rx_macro_probe()
3871 rx->dev = dev; in rx_macro_probe()
3874 clk_set_rate(rx->mclk, MCLK_FREQ); in rx_macro_probe()
3875 clk_set_rate(rx->npl, MCLK_FREQ); in rx_macro_probe()
3877 ret = clk_prepare_enable(rx->macro); in rx_macro_probe()
3881 ret = clk_prepare_enable(rx->dcodec); in rx_macro_probe()
3885 ret = clk_prepare_enable(rx->mclk); in rx_macro_probe()
3889 ret = clk_prepare_enable(rx->npl); in rx_macro_probe()
3893 ret = clk_prepare_enable(rx->fsgen); in rx_macro_probe()
3898 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3902 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3905 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3928 clk_disable_unprepare(rx->fsgen); in rx_macro_probe()
3930 clk_disable_unprepare(rx->npl); in rx_macro_probe()
3932 clk_disable_unprepare(rx->mclk); in rx_macro_probe()
3934 clk_disable_unprepare(rx->dcodec); in rx_macro_probe()
3936 clk_disable_unprepare(rx->macro); in rx_macro_probe()
3943 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove()
3945 clk_disable_unprepare(rx->mclk); in rx_macro_remove()
3946 clk_disable_unprepare(rx->npl); in rx_macro_remove()
3947 clk_disable_unprepare(rx->fsgen); in rx_macro_remove()
3948 clk_disable_unprepare(rx->macro); in rx_macro_remove()
3949 clk_disable_unprepare(rx->dcodec); in rx_macro_remove()
3954 .compatible = "qcom,sc7280-lpass-rx-macro",
3958 .compatible = "qcom,sm8250-lpass-rx-macro",
3961 .compatible = "qcom,sm8450-lpass-rx-macro",
3964 .compatible = "qcom,sm8550-lpass-rx-macro",
3966 .compatible = "qcom,sc8280xp-lpass-rx-macro",
3977 regcache_cache_only(rx->regmap, true); in rx_macro_runtime_suspend()
3978 regcache_mark_dirty(rx->regmap); in rx_macro_runtime_suspend()
3980 clk_disable_unprepare(rx->fsgen); in rx_macro_runtime_suspend()
3981 clk_disable_unprepare(rx->npl); in rx_macro_runtime_suspend()
3982 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_suspend()
3992 ret = clk_prepare_enable(rx->mclk); in rx_macro_runtime_resume()
3998 ret = clk_prepare_enable(rx->npl); in rx_macro_runtime_resume()
4004 ret = clk_prepare_enable(rx->fsgen); in rx_macro_runtime_resume()
4009 regcache_cache_only(rx->regmap, false); in rx_macro_runtime_resume()
4010 regcache_sync(rx->regmap); in rx_macro_runtime_resume()
4014 clk_disable_unprepare(rx->npl); in rx_macro_runtime_resume()
4016 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_resume()
4038 MODULE_DESCRIPTION("RX macro driver");