Lines Matching +full:sm8250 +full:- +full:lpass +full:- +full:rx +full:- +full:macro
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
14 #include <sound/soc-dapm.h>
17 #include <linux/clk-provider.h>
19 #include "lpass-macro-common.h"
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n) argument
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n) argument
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n) argument
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n) argument
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n) argument
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n) argument
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n) argument
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n) argument
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n) argument
205 #define CDC_RX_RXn_RX_PATH_SEC7(rx, n) \ argument
206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
211 #define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n) \ argument
212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
221 /* RX offsets prior to 2.5 codec version */
269 /* LPASS CODEC version 2.5 rx reg offsets */
665 struct clk *macro; member
678 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
703 "ZERO", "RX INT0_1 MIX1",
707 "ZERO", "RX INT1_1 MIX1",
711 "ZERO", "RX INT2_1 MIX1",
715 "ZERO", "RX INT0_2 MUX",
719 "ZERO", "RX INT1_2 MUX",
723 "ZERO", "RX INT2_2 MUX",
824 SOC_DAPM_ENUM("RX MIX TX1_MUX Mux", rx_mix_tx1_mux_enum);
826 SOC_DAPM_ENUM("RX MIX TX2_MUX Mux", rx_mix_tx2_mux_enum);
886 SOC_DAPM_ENUM("RX MIX TX0_MUX Mux", rx_mix_tx0_mux_enum);
889 /* RX Macro */
1243 /* Update volatile list for rx/tx macros */ in rx_is_volatile_register()
1387 struct rx_macro *rx = dev_get_drvdata(dev); in rx_is_rw_register() local
1604 switch (rx->codec_version) { in rx_is_rw_register()
1686 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_int_dem_inp_mux_put()
1687 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_int_dem_inp_mux_put() local
1688 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_int_dem_inp_mux_put()
1692 val = ucontrol->value.enumerated.item[0]; in rx_macro_int_dem_inp_mux_put()
1694 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) in rx_macro_int_dem_inp_mux_put()
1695 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); in rx_macro_int_dem_inp_mux_put()
1696 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) in rx_macro_int_dem_inp_mux_put()
1697 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); in rx_macro_int_dem_inp_mux_put()
1731 struct snd_soc_component *component = dai->component; in rx_macro_set_prim_interpolator_rate()
1732 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_prim_interpolator_rate() local
1734 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1739 * to which interpolator input, the rx port in rx_macro_set_prim_interpolator_rate()
1755 int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); in rx_macro_set_prim_interpolator_rate()
1776 struct snd_soc_component *component = dai->component; in rx_macro_set_mix_interpolator_rate()
1777 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_mix_interpolator_rate() local
1779 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1788 int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); in rx_macro_set_mix_interpolator_rate()
1822 struct snd_soc_component *component = dai->component; in rx_macro_hw_params()
1823 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_hw_params() local
1826 switch (substream->stream) { in rx_macro_hw_params()
1830 dev_err(component->dev, "%s: cannot set sample rate: %u\n", in rx_macro_hw_params()
1834 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1846 struct snd_soc_component *component = dai->component; in rx_macro_get_channel_map()
1847 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_channel_map() local
1850 switch (dai->id) { in rx_macro_get_channel_map()
1855 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1862 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1863 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1864 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 in rx_macro_get_channel_map()
1865 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 in rx_macro_get_channel_map()
1876 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1898 dev_err(component->dev, "%s: Invalid AIF\n", __func__); in rx_macro_get_channel_map()
1906 struct snd_soc_component *component = dai->component; in rx_macro_digital_mute()
1907 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_digital_mute() local
1912 switch (dai->id) { in rx_macro_digital_mute()
1918 reg = CDC_RX_RXn_RX_PATH_CTL(rx, j); in rx_macro_digital_mute()
1919 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j); in rx_macro_digital_mute()
1920 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j); in rx_macro_digital_mute()
2037 static void rx_macro_mclk_enable(struct rx_macro *rx, bool mclk_enable) in rx_macro_mclk_enable() argument
2039 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
2042 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2056 rx->rx_mclk_users++; in rx_macro_mclk_enable()
2058 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
2059 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
2060 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
2063 rx->rx_mclk_users--; in rx_macro_mclk_enable()
2064 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2080 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_mclk_event()
2081 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mclk_event() local
2086 rx_macro_mclk_enable(rx, true); in rx_macro_mclk_event()
2089 rx_macro_mclk_enable(rx, false); in rx_macro_mclk_event()
2092 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); in rx_macro_mclk_event()
2093 ret = -EINVAL; in rx_macro_mclk_event()
2141 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_main_path()
2142 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_main_path() local
2145 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); in rx_macro_enable_main_path()
2146 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); in rx_macro_enable_main_path()
2150 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2151 if (rx_macro_adie_lb(component, w->shift)) in rx_macro_enable_main_path()
2161 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2169 struct rx_macro *rx, in rx_macro_config_compander() argument
2178 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F; in rx_macro_config_compander()
2189 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), in rx_macro_config_compander()
2193 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp), in rx_macro_config_compander()
2195 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2206 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), in rx_macro_config_compander()
2213 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp), in rx_macro_config_compander()
2225 struct rx_macro *rx, in rx_macro_load_compander_coeff() argument
2236 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2250 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2266 struct rx_macro *rx, bool enable) in rx_macro_enable_softclip_clk() argument
2269 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2272 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2274 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2275 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2282 struct rx_macro *rx, int event) in rx_macro_config_softclip() argument
2285 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2290 rx_macro_enable_softclip_clk(component, rx, true); in rx_macro_config_softclip()
2299 rx_macro_enable_softclip_clk(component, rx, false); in rx_macro_config_softclip()
2306 struct rx_macro *rx, int event) in rx_macro_config_aux_hpf() argument
2310 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2312 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00); in rx_macro_config_aux_hpf()
2318 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04); in rx_macro_config_aux_hpf()
2324 static inline void rx_macro_enable_clsh_block(struct rx_macro *rx, bool enable) in rx_macro_enable_clsh_block() argument
2326 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2327 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2329 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2330 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2334 struct rx_macro *rx, in rx_macro_config_classh() argument
2338 rx_macro_enable_clsh_block(rx, false); in rx_macro_config_classh()
2345 rx_macro_enable_clsh_block(rx, true); in rx_macro_config_classh()
2358 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2370 CDC_RX_RXn_RX_PATH_CFG0(rx, 0), in rx_macro_config_classh()
2374 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2386 CDC_RX_RXn_RX_PATH_CFG0(rx, 1), in rx_macro_config_classh()
2391 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), in rx_macro_config_classh()
2394 CDC_RX_RXn_RX_PATH_CFG0(rx, 2), in rx_macro_config_classh()
2405 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_hd2_control() local
2410 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0); in rx_macro_hd2_control()
2411 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); in rx_macro_hd2_control()
2414 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1); in rx_macro_hd2_control()
2415 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1); in rx_macro_hd2_control()
2439 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_get_compander()
2440 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_compander() local
2442 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2450 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_set_compander()
2451 int value = ucontrol->value.integer.value[0]; in rx_macro_set_compander()
2452 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_set_compander() local
2454 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2463 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_get()
2464 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_get() local
2466 ucontrol->value.enumerated.item[0] = in rx_macro_mux_get()
2467 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2475 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_put()
2476 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_mux_put()
2478 u32 rx_port_value = ucontrol->value.enumerated.item[0]; in rx_macro_mux_put()
2481 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_mux_put() local
2483 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2488 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); in rx_macro_mux_put()
2492 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2500 dai_id = aif_rst - 1; in rx_macro_mux_put()
2501 if (rx->active_ch_cnt[dai_id]) { in rx_macro_mux_put()
2502 clear_bit(widget->shift, &rx->active_ch_mask[dai_id]); in rx_macro_mux_put()
2503 rx->active_ch_cnt[dai_id]--; in rx_macro_mux_put()
2511 dai_id = rx_port_value - 1; in rx_macro_mux_put()
2512 set_bit(widget->shift, &rx->active_ch_mask[dai_id]); in rx_macro_mux_put()
2513 rx->active_ch_cnt[dai_id]++; in rx_macro_mux_put()
2516 dev_err(component->dev, in rx_macro_mux_put()
2522 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, in rx_macro_mux_put()
2526 return -EINVAL; in rx_macro_mux_put()
2552 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_ear_mode() local
2554 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2562 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_ear_mode() local
2564 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2572 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_hd2_mode() local
2574 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2582 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_hd2_mode() local
2584 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2592 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_get_hph_pwr_mode() local
2594 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2602 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_put_hph_pwr_mode() local
2604 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2612 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_get() local
2614 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2623 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_soft_clip_enable_put() local
2625 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2634 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_get() local
2636 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2645 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_aux_hpf_mode_put() local
2647 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2653 struct rx_macro *rx, in rx_macro_hphdelay_lutbypass() argument
2669 return -EINVAL; in rx_macro_hphdelay_lutbypass()
2674 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2676 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), in rx_macro_hphdelay_lutbypass()
2686 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2693 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), in rx_macro_hphdelay_lutbypass()
2708 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_interp_clk() local
2710 main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx); in rx_macro_enable_interp_clk()
2711 dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx); in rx_macro_enable_interp_clk()
2712 rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx); in rx_macro_enable_interp_clk()
2715 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2723 rx_macro_load_compander_coeff(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2724 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2726 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2727 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2729 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2730 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2732 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2734 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2738 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2739 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2740 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2760 rx_macro_config_classh(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2761 rx_macro_config_compander(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2763 rx_macro_config_softclip(component, rx, event); in rx_macro_enable_interp_clk()
2764 rx_macro_config_aux_hpf(component, rx, event); in rx_macro_enable_interp_clk()
2766 rx_macro_hphdelay_lutbypass(component, rx, interp_idx, event); in rx_macro_enable_interp_clk()
2767 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2772 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2778 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_mix_path()
2779 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_mix_path() local
2782 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2783 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2787 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2797 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2813 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_rx_path_clk()
2814 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_enable_rx_path_clk() local
2818 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2819 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2821 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), in rx_macro_enable_rx_path_clk()
2825 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2827 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2838 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_set_iir_gain()
2843 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { in rx_macro_set_iir_gain()
2925 /* Mask top 2 bits, 7-8 are reserved */ in set_iir_band_coeff()
2936 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_put_iir_band_audio_mixer()
2937 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_put_iir_band_audio_mixer()
2938 int iir_idx = ctl->iir_idx; in rx_macro_put_iir_band_audio_mixer()
2939 int band_idx = ctl->band_idx; in rx_macro_put_iir_band_audio_mixer()
2943 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); in rx_macro_put_iir_band_audio_mixer()
2965 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_get_iir_band_audio_mixer()
2966 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_get_iir_band_audio_mixer()
2967 int iir_idx = ctl->iir_idx; in rx_macro_get_iir_band_audio_mixer()
2968 int band_idx = ctl->band_idx; in rx_macro_get_iir_band_audio_mixer()
2977 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); in rx_macro_get_iir_band_audio_mixer()
2986 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_iir_filter_info()
2987 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_iir_filter_info()
2989 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in rx_macro_iir_filter_info()
2990 ucontrol->count = params->max; in rx_macro_iir_filter_info()
2997 -84, 40, digital_gain),
2999 -84, 40, digital_gain),
3001 -84, 40, digital_gain),
3003 -84, 40, digital_gain),
3009 -84, 40, digital_gain),
3011 -84, 40, digital_gain),
3013 -84, 40, digital_gain),
3015 -84, 40, digital_gain),
3020 -84, 40, digital_gain),
3022 -84, 40, digital_gain),
3045 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3048 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3051 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3054 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3057 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3060 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3063 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3066 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3108 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_echo()
3110 int ec_tx = -1; in rx_macro_enable_echo()
3114 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX0 MUX"))) in rx_macro_enable_echo()
3115 ec_tx = ((val & 0xf0) >> 0x4) - 1; in rx_macro_enable_echo()
3116 else if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX1 MUX"))) in rx_macro_enable_echo()
3117 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3121 if (!(snd_soc_dapm_widget_name_cmp(w, "RX MIX TX2 MUX"))) in rx_macro_enable_echo()
3122 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3125 dev_err(component->dev, "%s: EC mix control not set correctly\n", in rx_macro_enable_echo()
3127 return -EINVAL; in rx_macro_enable_echo()
3141 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3146 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3151 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
3154 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
3157 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
3160 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
3163 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
3195 SND_SOC_DAPM_MUX_E("RX MIX TX0 MUX", SND_SOC_NOPM,
3199 SND_SOC_DAPM_MUX_E("RX MIX TX1 MUX", SND_SOC_NOPM,
3203 SND_SOC_DAPM_MUX_E("RX MIX TX2 MUX", SND_SOC_NOPM,
3219 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3222 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3226 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3230 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3235 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3236 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3237 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3238 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3239 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3240 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3241 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3242 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3243 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3245 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3249 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3253 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3258 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3260 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3262 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3265 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3266 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3267 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3268 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3269 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3270 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3272 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", SND_SOC_NOPM, INTERP_HPHL,
3275 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", SND_SOC_NOPM, INTERP_HPHR,
3278 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", SND_SOC_NOPM, INTERP_AUX,
3282 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3283 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3284 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3300 {"RX AIF1 PB", NULL, "RX_MCLK"},
3301 {"RX AIF2 PB", NULL, "RX_MCLK"},
3302 {"RX AIF3 PB", NULL, "RX_MCLK"},
3303 {"RX AIF4 PB", NULL, "RX_MCLK"},
3305 {"RX_MACRO RX0 MUX", "AIF1_PB", "RX AIF1 PB"},
3306 {"RX_MACRO RX1 MUX", "AIF1_PB", "RX AIF1 PB"},
3307 {"RX_MACRO RX2 MUX", "AIF1_PB", "RX AIF1 PB"},
3308 {"RX_MACRO RX3 MUX", "AIF1_PB", "RX AIF1 PB"},
3309 {"RX_MACRO RX4 MUX", "AIF1_PB", "RX AIF1 PB"},
3310 {"RX_MACRO RX5 MUX", "AIF1_PB", "RX AIF1 PB"},
3312 {"RX_MACRO RX0 MUX", "AIF2_PB", "RX AIF2 PB"},
3313 {"RX_MACRO RX1 MUX", "AIF2_PB", "RX AIF2 PB"},
3314 {"RX_MACRO RX2 MUX", "AIF2_PB", "RX AIF2 PB"},
3315 {"RX_MACRO RX3 MUX", "AIF2_PB", "RX AIF2 PB"},
3316 {"RX_MACRO RX4 MUX", "AIF2_PB", "RX AIF2 PB"},
3317 {"RX_MACRO RX5 MUX", "AIF2_PB", "RX AIF2 PB"},
3319 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3320 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3321 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3322 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3323 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3324 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3326 {"RX_MACRO RX0 MUX", "AIF4_PB", "RX AIF4 PB"},
3327 {"RX_MACRO RX1 MUX", "AIF4_PB", "RX AIF4 PB"},
3328 {"RX_MACRO RX2 MUX", "AIF4_PB", "RX AIF4 PB"},
3329 {"RX_MACRO RX3 MUX", "AIF4_PB", "RX AIF4 PB"},
3330 {"RX_MACRO RX4 MUX", "AIF4_PB", "RX AIF4 PB"},
3331 {"RX_MACRO RX5 MUX", "AIF4_PB", "RX AIF4 PB"},
3340 {"RX INT0_1 MIX1 INP0", "RX0", "RX_RX0"},
3341 {"RX INT0_1 MIX1 INP0", "RX1", "RX_RX1"},
3342 {"RX INT0_1 MIX1 INP0", "RX2", "RX_RX2"},
3343 {"RX INT0_1 MIX1 INP0", "RX3", "RX_RX3"},
3344 {"RX INT0_1 MIX1 INP0", "RX4", "RX_RX4"},
3345 {"RX INT0_1 MIX1 INP0", "RX5", "RX_RX5"},
3346 {"RX INT0_1 MIX1 INP0", "IIR0", "IIR0"},
3347 {"RX INT0_1 MIX1 INP0", "IIR1", "IIR1"},
3348 {"RX INT0_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3349 {"RX INT0_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3350 {"RX INT0_1 MIX1 INP1", "RX0", "RX_RX0"},
3351 {"RX INT0_1 MIX1 INP1", "RX1", "RX_RX1"},
3352 {"RX INT0_1 MIX1 INP1", "RX2", "RX_RX2"},
3353 {"RX INT0_1 MIX1 INP1", "RX3", "RX_RX3"},
3354 {"RX INT0_1 MIX1 INP1", "RX4", "RX_RX4"},
3355 {"RX INT0_1 MIX1 INP1", "RX5", "RX_RX5"},
3356 {"RX INT0_1 MIX1 INP1", "IIR0", "IIR0"},
3357 {"RX INT0_1 MIX1 INP1", "IIR1", "IIR1"},
3358 {"RX INT0_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3359 {"RX INT0_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3360 {"RX INT0_1 MIX1 INP2", "RX0", "RX_RX0"},
3361 {"RX INT0_1 MIX1 INP2", "RX1", "RX_RX1"},
3362 {"RX INT0_1 MIX1 INP2", "RX2", "RX_RX2"},
3363 {"RX INT0_1 MIX1 INP2", "RX3", "RX_RX3"},
3364 {"RX INT0_1 MIX1 INP2", "RX4", "RX_RX4"},
3365 {"RX INT0_1 MIX1 INP2", "RX5", "RX_RX5"},
3366 {"RX INT0_1 MIX1 INP2", "IIR0", "IIR0"},
3367 {"RX INT0_1 MIX1 INP2", "IIR1", "IIR1"},
3368 {"RX INT0_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3369 {"RX INT0_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3371 {"RX INT1_1 MIX1 INP0", "RX0", "RX_RX0"},
3372 {"RX INT1_1 MIX1 INP0", "RX1", "RX_RX1"},
3373 {"RX INT1_1 MIX1 INP0", "RX2", "RX_RX2"},
3374 {"RX INT1_1 MIX1 INP0", "RX3", "RX_RX3"},
3375 {"RX INT1_1 MIX1 INP0", "RX4", "RX_RX4"},
3376 {"RX INT1_1 MIX1 INP0", "RX5", "RX_RX5"},
3377 {"RX INT1_1 MIX1 INP0", "IIR0", "IIR0"},
3378 {"RX INT1_1 MIX1 INP0", "IIR1", "IIR1"},
3379 {"RX INT1_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3380 {"RX INT1_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3381 {"RX INT1_1 MIX1 INP1", "RX0", "RX_RX0"},
3382 {"RX INT1_1 MIX1 INP1", "RX1", "RX_RX1"},
3383 {"RX INT1_1 MIX1 INP1", "RX2", "RX_RX2"},
3384 {"RX INT1_1 MIX1 INP1", "RX3", "RX_RX3"},
3385 {"RX INT1_1 MIX1 INP1", "RX4", "RX_RX4"},
3386 {"RX INT1_1 MIX1 INP1", "RX5", "RX_RX5"},
3387 {"RX INT1_1 MIX1 INP1", "IIR0", "IIR0"},
3388 {"RX INT1_1 MIX1 INP1", "IIR1", "IIR1"},
3389 {"RX INT1_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3390 {"RX INT1_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3391 {"RX INT1_1 MIX1 INP2", "RX0", "RX_RX0"},
3392 {"RX INT1_1 MIX1 INP2", "RX1", "RX_RX1"},
3393 {"RX INT1_1 MIX1 INP2", "RX2", "RX_RX2"},
3394 {"RX INT1_1 MIX1 INP2", "RX3", "RX_RX3"},
3395 {"RX INT1_1 MIX1 INP2", "RX4", "RX_RX4"},
3396 {"RX INT1_1 MIX1 INP2", "RX5", "RX_RX5"},
3397 {"RX INT1_1 MIX1 INP2", "IIR0", "IIR0"},
3398 {"RX INT1_1 MIX1 INP2", "IIR1", "IIR1"},
3399 {"RX INT1_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3400 {"RX INT1_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3402 {"RX INT2_1 MIX1 INP0", "RX0", "RX_RX0"},
3403 {"RX INT2_1 MIX1 INP0", "RX1", "RX_RX1"},
3404 {"RX INT2_1 MIX1 INP0", "RX2", "RX_RX2"},
3405 {"RX INT2_1 MIX1 INP0", "RX3", "RX_RX3"},
3406 {"RX INT2_1 MIX1 INP0", "RX4", "RX_RX4"},
3407 {"RX INT2_1 MIX1 INP0", "RX5", "RX_RX5"},
3408 {"RX INT2_1 MIX1 INP0", "IIR0", "IIR0"},
3409 {"RX INT2_1 MIX1 INP0", "IIR1", "IIR1"},
3410 {"RX INT2_1 MIX1 INP0", "DEC0", "RX_TX DEC0_INP"},
3411 {"RX INT2_1 MIX1 INP0", "DEC1", "RX_TX DEC1_INP"},
3412 {"RX INT2_1 MIX1 INP1", "RX0", "RX_RX0"},
3413 {"RX INT2_1 MIX1 INP1", "RX1", "RX_RX1"},
3414 {"RX INT2_1 MIX1 INP1", "RX2", "RX_RX2"},
3415 {"RX INT2_1 MIX1 INP1", "RX3", "RX_RX3"},
3416 {"RX INT2_1 MIX1 INP1", "RX4", "RX_RX4"},
3417 {"RX INT2_1 MIX1 INP1", "RX5", "RX_RX5"},
3418 {"RX INT2_1 MIX1 INP1", "IIR0", "IIR0"},
3419 {"RX INT2_1 MIX1 INP1", "IIR1", "IIR1"},
3420 {"RX INT2_1 MIX1 INP1", "DEC0", "RX_TX DEC0_INP"},
3421 {"RX INT2_1 MIX1 INP1", "DEC1", "RX_TX DEC1_INP"},
3422 {"RX INT2_1 MIX1 INP2", "RX0", "RX_RX0"},
3423 {"RX INT2_1 MIX1 INP2", "RX1", "RX_RX1"},
3424 {"RX INT2_1 MIX1 INP2", "RX2", "RX_RX2"},
3425 {"RX INT2_1 MIX1 INP2", "RX3", "RX_RX3"},
3426 {"RX INT2_1 MIX1 INP2", "RX4", "RX_RX4"},
3427 {"RX INT2_1 MIX1 INP2", "RX5", "RX_RX5"},
3428 {"RX INT2_1 MIX1 INP2", "IIR0", "IIR0"},
3429 {"RX INT2_1 MIX1 INP2", "IIR1", "IIR1"},
3430 {"RX INT2_1 MIX1 INP2", "DEC0", "RX_TX DEC0_INP"},
3431 {"RX INT2_1 MIX1 INP2", "DEC1", "RX_TX DEC1_INP"},
3433 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP0"},
3434 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP1"},
3435 {"RX INT0_1 MIX1", NULL, "RX INT0_1 MIX1 INP2"},
3436 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP0"},
3437 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP1"},
3438 {"RX INT1_1 MIX1", NULL, "RX INT1_1 MIX1 INP2"},
3439 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP0"},
3440 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP1"},
3441 {"RX INT2_1 MIX1", NULL, "RX INT2_1 MIX1 INP2"},
3443 {"RX MIX TX0 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3444 {"RX MIX TX0 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3445 {"RX MIX TX0 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3446 {"RX MIX TX1 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3447 {"RX MIX TX1 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3448 {"RX MIX TX1 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3449 {"RX MIX TX2 MUX", "RX_MIX0", "RX INT0 SEC MIX"},
3450 {"RX MIX TX2 MUX", "RX_MIX1", "RX INT1 SEC MIX"},
3451 {"RX MIX TX2 MUX", "RX_MIX2", "RX INT2 SEC MIX"},
3452 {"RX AIF_ECHO", NULL, "RX MIX TX0 MUX"},
3453 {"RX AIF_ECHO", NULL, "RX MIX TX1 MUX"},
3454 {"RX AIF_ECHO", NULL, "RX MIX TX2 MUX"},
3455 {"RX AIF_ECHO", NULL, "RX_MCLK"},
3458 {"RX INT0_2 MUX", "RX0", "RX_RX0"},
3459 {"RX INT0_2 MUX", "RX1", "RX_RX1"},
3460 {"RX INT0_2 MUX", "RX2", "RX_RX2"},
3461 {"RX INT0_2 MUX", "RX3", "RX_RX3"},
3462 {"RX INT0_2 MUX", "RX4", "RX_RX4"},
3463 {"RX INT0_2 MUX", "RX5", "RX_RX5"},
3464 {"RX INT0_2 INTERP", NULL, "RX INT0_2 MUX"},
3465 {"RX INT0 SEC MIX", NULL, "RX INT0_2 INTERP"},
3468 {"RX INT1_2 MUX", "RX0", "RX_RX0"},
3469 {"RX INT1_2 MUX", "RX1", "RX_RX1"},
3470 {"RX INT1_2 MUX", "RX2", "RX_RX2"},
3471 {"RX INT1_2 MUX", "RX3", "RX_RX3"},
3472 {"RX INT1_2 MUX", "RX4", "RX_RX4"},
3473 {"RX INT1_2 MUX", "RX5", "RX_RX5"},
3474 {"RX INT1_2 INTERP", NULL, "RX INT1_2 MUX"},
3475 {"RX INT1 SEC MIX", NULL, "RX INT1_2 INTERP"},
3478 {"RX INT2_2 MUX", "RX0", "RX_RX0"},
3479 {"RX INT2_2 MUX", "RX1", "RX_RX1"},
3480 {"RX INT2_2 MUX", "RX2", "RX_RX2"},
3481 {"RX INT2_2 MUX", "RX3", "RX_RX3"},
3482 {"RX INT2_2 MUX", "RX4", "RX_RX4"},
3483 {"RX INT2_2 MUX", "RX5", "RX_RX5"},
3484 {"RX INT2_2 INTERP", NULL, "RX INT2_2 MUX"},
3485 {"RX INT2 SEC MIX", NULL, "RX INT2_2 INTERP"},
3487 {"RX INT0_1 INTERP", NULL, "RX INT0_1 MIX1"},
3488 {"RX INT0 SEC MIX", NULL, "RX INT0_1 INTERP"},
3489 {"RX INT0 MIX2", NULL, "RX INT0 SEC MIX"},
3490 {"RX INT0 MIX2", NULL, "RX INT0 MIX2 INP"},
3491 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
3492 {"HPHL_OUT", NULL, "RX INT0 DEM MUX"},
3495 {"RX INT1_1 INTERP", NULL, "RX INT1_1 MIX1"},
3496 {"RX INT1 SEC MIX", NULL, "RX INT1_1 INTERP"},
3497 {"RX INT1 MIX2", NULL, "RX INT1 SEC MIX"},
3498 {"RX INT1 MIX2", NULL, "RX INT1 MIX2 INP"},
3499 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX2"},
3500 {"HPHR_OUT", NULL, "RX INT1 DEM MUX"},
3503 {"RX INT2_1 INTERP", NULL, "RX INT2_1 MIX1"},
3505 {"RX INT2 SEC MIX", NULL, "RX INT2_1 INTERP"},
3506 {"RX INT2 MIX2", NULL, "RX INT2 SEC MIX"},
3507 {"RX INT2 MIX2", NULL, "RX INT2 MIX2 INP"},
3508 {"AUX_OUT", NULL, "RX INT2 MIX2"},
3605 {"RX INT0 MIX2 INP", "SRC0", "SRC0"},
3606 {"RX INT0 MIX2 INP", "SRC1", "SRC1"},
3607 {"RX INT1 MIX2 INP", "SRC0", "SRC0"},
3608 {"RX INT1 MIX2 INP", "SRC1", "SRC1"},
3609 {"RX INT2 MIX2 INP", "SRC0", "SRC0"},
3610 {"RX INT2 MIX2 INP", "SRC1", "SRC1"},
3616 struct rx_macro *rx = snd_soc_component_get_drvdata(component); in rx_macro_component_probe() local
3622 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3624 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0), in rx_macro_component_probe()
3627 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1), in rx_macro_component_probe()
3630 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2), in rx_macro_component_probe()
3633 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0), in rx_macro_component_probe()
3636 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1), in rx_macro_component_probe()
3639 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2), in rx_macro_component_probe()
3643 switch (rx->codec_version) { in rx_macro_component_probe()
3664 return -EINVAL; in rx_macro_component_probe()
3667 rx->component = component; in rx_macro_component_probe()
3678 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_enable() local
3681 ret = clk_prepare_enable(rx->mclk); in swclk_gate_enable()
3683 dev_err(rx->dev, "unable to prepare mclk\n"); in swclk_gate_enable()
3687 rx_macro_mclk_enable(rx, true); in swclk_gate_enable()
3689 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3697 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_disable() local
3699 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3702 rx_macro_mclk_enable(rx, false); in swclk_gate_disable()
3703 clk_disable_unprepare(rx->mclk); in swclk_gate_disable()
3708 struct rx_macro *rx = to_rx_macro(hw); in swclk_gate_is_enabled() local
3711 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3731 static int rx_macro_register_mclk_output(struct rx_macro *rx) in rx_macro_register_mclk_output() argument
3733 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3735 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3740 if (rx->npl) in rx_macro_register_mclk_output()
3741 parent_clk_name = __clk_get_name(rx->npl); in rx_macro_register_mclk_output()
3743 parent_clk_name = __clk_get_name(rx->mclk); in rx_macro_register_mclk_output()
3750 rx->hw.init = &init; in rx_macro_register_mclk_output()
3751 hw = &rx->hw; in rx_macro_register_mclk_output()
3752 ret = devm_clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3760 .name = "RX-MACRO",
3772 struct device *dev = &pdev->dev; in rx_macro_probe()
3774 struct rx_macro *rx; in rx_macro_probe() local
3780 rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL); in rx_macro_probe()
3781 if (!rx) in rx_macro_probe()
3782 return -ENOMEM; in rx_macro_probe()
3784 rx->macro = devm_clk_get_optional(dev, "macro"); in rx_macro_probe()
3785 if (IS_ERR(rx->macro)) in rx_macro_probe()
3786 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); in rx_macro_probe()
3788 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); in rx_macro_probe()
3789 if (IS_ERR(rx->dcodec)) in rx_macro_probe()
3790 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); in rx_macro_probe()
3792 rx->mclk = devm_clk_get(dev, "mclk"); in rx_macro_probe()
3793 if (IS_ERR(rx->mclk)) in rx_macro_probe()
3794 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); in rx_macro_probe()
3797 rx->npl = devm_clk_get(dev, "npl"); in rx_macro_probe()
3798 if (IS_ERR(rx->npl)) in rx_macro_probe()
3799 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); in rx_macro_probe()
3802 rx->fsgen = devm_clk_get(dev, "fsgen"); in rx_macro_probe()
3803 if (IS_ERR(rx->fsgen)) in rx_macro_probe()
3804 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); in rx_macro_probe()
3806 rx->pds = lpass_macro_pds_init(dev); in rx_macro_probe()
3807 if (IS_ERR(rx->pds)) in rx_macro_probe()
3808 return PTR_ERR(rx->pds); in rx_macro_probe()
3810 ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds); in rx_macro_probe()
3818 rx->codec_version = lpass_macro_get_codec_version(); in rx_macro_probe()
3821 switch (rx->codec_version) { in rx_macro_probe()
3827 rx->rxn_reg_stride = 0x80; in rx_macro_probe()
3828 rx->rxn_reg_stride2 = 0xc; in rx_macro_probe()
3832 return -ENOMEM; in rx_macro_probe()
3841 rx->rxn_reg_stride = 0xc0; in rx_macro_probe()
3842 rx->rxn_reg_stride2 = 0x0; in rx_macro_probe()
3846 return -ENOMEM; in rx_macro_probe()
3852 dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version); in rx_macro_probe()
3853 return -EINVAL; in rx_macro_probe()
3860 return -ENOMEM; in rx_macro_probe()
3862 reg_config->reg_defaults = reg_defaults; in rx_macro_probe()
3863 reg_config->num_reg_defaults = def_count; in rx_macro_probe()
3865 rx->regmap = devm_regmap_init_mmio(dev, base, reg_config); in rx_macro_probe()
3866 if (IS_ERR(rx->regmap)) in rx_macro_probe()
3867 return PTR_ERR(rx->regmap); in rx_macro_probe()
3869 dev_set_drvdata(dev, rx); in rx_macro_probe()
3871 rx->dev = dev; in rx_macro_probe()
3874 clk_set_rate(rx->mclk, MCLK_FREQ); in rx_macro_probe()
3875 clk_set_rate(rx->npl, MCLK_FREQ); in rx_macro_probe()
3877 ret = clk_prepare_enable(rx->macro); in rx_macro_probe()
3881 ret = clk_prepare_enable(rx->dcodec); in rx_macro_probe()
3885 ret = clk_prepare_enable(rx->mclk); in rx_macro_probe()
3889 ret = clk_prepare_enable(rx->npl); in rx_macro_probe()
3893 ret = clk_prepare_enable(rx->fsgen); in rx_macro_probe()
3898 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3902 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3905 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3921 ret = rx_macro_register_mclk_output(rx); in rx_macro_probe()
3928 clk_disable_unprepare(rx->fsgen); in rx_macro_probe()
3930 clk_disable_unprepare(rx->npl); in rx_macro_probe()
3932 clk_disable_unprepare(rx->mclk); in rx_macro_probe()
3934 clk_disable_unprepare(rx->dcodec); in rx_macro_probe()
3936 clk_disable_unprepare(rx->macro); in rx_macro_probe()
3943 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove() local
3945 clk_disable_unprepare(rx->mclk); in rx_macro_remove()
3946 clk_disable_unprepare(rx->npl); in rx_macro_remove()
3947 clk_disable_unprepare(rx->fsgen); in rx_macro_remove()
3948 clk_disable_unprepare(rx->macro); in rx_macro_remove()
3949 clk_disable_unprepare(rx->dcodec); in rx_macro_remove()
3954 .compatible = "qcom,sc7280-lpass-rx-macro",
3958 .compatible = "qcom,sm8250-lpass-rx-macro",
3961 .compatible = "qcom,sm8450-lpass-rx-macro",
3964 .compatible = "qcom,sm8550-lpass-rx-macro",
3966 .compatible = "qcom,sc8280xp-lpass-rx-macro",
3975 struct rx_macro *rx = dev_get_drvdata(dev); in rx_macro_runtime_suspend() local
3977 regcache_cache_only(rx->regmap, true); in rx_macro_runtime_suspend()
3978 regcache_mark_dirty(rx->regmap); in rx_macro_runtime_suspend()
3980 clk_disable_unprepare(rx->fsgen); in rx_macro_runtime_suspend()
3981 clk_disable_unprepare(rx->npl); in rx_macro_runtime_suspend()
3982 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_suspend()
3989 struct rx_macro *rx = dev_get_drvdata(dev); in rx_macro_runtime_resume() local
3992 ret = clk_prepare_enable(rx->mclk); in rx_macro_runtime_resume()
3998 ret = clk_prepare_enable(rx->npl); in rx_macro_runtime_resume()
4004 ret = clk_prepare_enable(rx->fsgen); in rx_macro_runtime_resume()
4009 regcache_cache_only(rx->regmap, false); in rx_macro_runtime_resume()
4010 regcache_sync(rx->regmap); in rx_macro_runtime_resume()
4014 clk_disable_unprepare(rx->npl); in rx_macro_runtime_resume()
4016 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_resume()
4038 MODULE_DESCRIPTION("RX macro driver");