Lines Matching +full:codec +full:- +full:aif3
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
14 #include <sound/soc-dapm.h>
17 #include <linux/clk-provider.h>
19 #include "lpass-macro-common.h"
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n)
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n)
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n)
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n)
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n)
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n)
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n)
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n)
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n)
206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
221 /* RX offsets prior to 2.5 codec version */
269 /* LPASS CODEC version 2.5 rx reg offsets */
578 /* Codec supports 2 IIR filters */
677 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
1602 switch (rx->codec_version) { in rx_is_rw_register()
1684 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_int_dem_inp_mux_put()
1686 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_int_dem_inp_mux_put()
1690 val = ucontrol->value.enumerated.item[0]; in rx_macro_int_dem_inp_mux_put()
1692 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) in rx_macro_int_dem_inp_mux_put()
1694 else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1)) in rx_macro_int_dem_inp_mux_put()
1729 struct snd_soc_component *component = dai->component; in rx_macro_set_prim_interpolator_rate()
1732 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_prim_interpolator_rate()
1774 struct snd_soc_component *component = dai->component; in rx_macro_set_mix_interpolator_rate()
1777 for_each_set_bit(port, &rx->active_ch_mask[dai->id], RX_MACRO_PORTS_MAX) { in rx_macro_set_mix_interpolator_rate()
1820 struct snd_soc_component *component = dai->component; in rx_macro_hw_params()
1824 switch (substream->stream) { in rx_macro_hw_params()
1828 dev_err(component->dev, "%s: cannot set sample rate: %u\n", in rx_macro_hw_params()
1832 rx->bit_width[dai->id] = params_width(params); in rx_macro_hw_params()
1844 struct snd_soc_component *component = dai->component; in rx_macro_get_channel_map()
1848 switch (dai->id) { in rx_macro_get_channel_map()
1853 for_each_set_bit(temp, &rx->active_ch_mask[dai->id], in rx_macro_get_channel_map()
1860 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1861 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1862 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 in rx_macro_get_channel_map()
1863 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 in rx_macro_get_channel_map()
1867 * CDC_DMA_RX_2(AIF3)/CDC_DMA_RX_3(AIF4) in rx_macro_get_channel_map()
1874 *rx_num = rx->active_ch_cnt[dai->id]; in rx_macro_get_channel_map()
1896 dev_err(component->dev, "%s: Invalid AIF\n", __func__); in rx_macro_get_channel_map()
1904 struct snd_soc_component *component = dai->component; in rx_macro_digital_mute()
1910 switch (dai->id) { in rx_macro_digital_mute()
2037 struct regmap *regmap = rx->regmap; in rx_macro_mclk_enable()
2040 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2054 rx->rx_mclk_users++; in rx_macro_mclk_enable()
2056 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
2057 dev_err(rx->dev, "%s: clock already disabled\n", __func__); in rx_macro_mclk_enable()
2058 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
2061 rx->rx_mclk_users--; in rx_macro_mclk_enable()
2062 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2078 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_mclk_event()
2090 dev_err(component->dev, "%s: invalid DAPM event %d\n", __func__, event); in rx_macro_mclk_event()
2091 ret = -EINVAL; in rx_macro_mclk_event()
2139 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_main_path()
2143 reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift); in rx_macro_enable_main_path()
2144 gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift); in rx_macro_enable_main_path()
2148 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2149 if (rx_macro_adie_lb(component, w->shift)) in rx_macro_enable_main_path()
2159 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_main_path()
2193 if (!rx->comp_enabled[comp]) in rx_macro_config_compander()
2234 if (!rx->comp_enabled[comp]) in rx_macro_load_compander_coeff()
2248 hph_pwr_mode = rx->hph_pwr_mode; in rx_macro_load_compander_coeff()
2267 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2270 rx->softclip_clk_users++; in rx_macro_enable_softclip_clk()
2272 rx->softclip_clk_users--; in rx_macro_enable_softclip_clk()
2273 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2283 if (!rx->is_softclip_on) in rx_macro_config_softclip()
2308 if (!rx->is_aux_hpf_on) in rx_macro_config_aux_hpf()
2324 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2325 snd_soc_component_update_bits(rx->component, CDC_RX_CLSH_CRC, in rx_macro_enable_clsh_block()
2327 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2328 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2356 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2372 if (rx->is_ear_mode_on) in rx_macro_config_classh()
2437 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_get_compander()
2440 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2448 int comp = ((struct soc_mixer_control *) kcontrol->private_value)->shift; in rx_macro_set_compander()
2449 int value = ucontrol->value.integer.value[0]; in rx_macro_set_compander()
2452 rx->comp_enabled[comp] = value; in rx_macro_set_compander()
2461 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_get()
2464 ucontrol->value.enumerated.item[0] = in rx_macro_mux_get()
2465 rx->rx_port_value[widget->shift]; in rx_macro_mux_get()
2473 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm); in rx_macro_mux_put()
2474 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in rx_macro_mux_put()
2476 u32 rx_port_value = ucontrol->value.enumerated.item[0]; in rx_macro_mux_put()
2480 aif_rst = rx->rx_port_value[widget->shift]; in rx_macro_mux_put()
2485 dev_err(component->dev, "%s: Invalid AIF reset\n", __func__); in rx_macro_mux_put()
2489 rx->rx_port_value[widget->shift] = rx_port_value; in rx_macro_mux_put()
2493 if (rx->active_ch_cnt[aif_rst]) { in rx_macro_mux_put()
2494 clear_bit(widget->shift, in rx_macro_mux_put()
2495 &rx->active_ch_mask[aif_rst]); in rx_macro_mux_put()
2496 rx->active_ch_cnt[aif_rst]--; in rx_macro_mux_put()
2503 set_bit(widget->shift, in rx_macro_mux_put()
2504 &rx->active_ch_mask[rx_port_value]); in rx_macro_mux_put()
2505 rx->active_ch_cnt[rx_port_value]++; in rx_macro_mux_put()
2508 dev_err(component->dev, in rx_macro_mux_put()
2514 snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, in rx_macro_mux_put()
2518 return -EINVAL; in rx_macro_mux_put()
2546 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2556 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2566 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2576 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2586 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2596 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2606 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2617 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2628 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2639 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2661 return -EINVAL; in rx_macro_hphdelay_lutbypass()
2666 if (rx->is_ear_mode_on) in rx_macro_hphdelay_lutbypass()
2678 if (rx->hph_pwr_mode) in rx_macro_hphdelay_lutbypass()
2707 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2716 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2726 rx->main_clk_users[interp_idx]++; in rx_macro_enable_interp_clk()
2730 rx->main_clk_users[interp_idx]--; in rx_macro_enable_interp_clk()
2731 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2732 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2759 if (rx->hph_hd2_mode) in rx_macro_enable_interp_clk()
2764 return rx->main_clk_users[interp_idx]; in rx_macro_enable_interp_clk()
2770 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_mix_path()
2774 gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2775 mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift); in rx_macro_enable_mix_path()
2779 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2789 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_mix_path()
2805 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_rx_path_clk()
2810 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2811 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2813 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift), in rx_macro_enable_rx_path_clk()
2817 snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift), in rx_macro_enable_rx_path_clk()
2819 rx_macro_enable_interp_clk(component, event, w->shift); in rx_macro_enable_rx_path_clk()
2830 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_set_iir_gain()
2835 if (strnstr(w->name, "IIR0", sizeof("IIR0"))) { in rx_macro_set_iir_gain()
2917 /* Mask top 2 bits, 7-8 are reserved */ in set_iir_band_coeff()
2928 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_put_iir_band_audio_mixer()
2929 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_put_iir_band_audio_mixer()
2930 int iir_idx = ctl->iir_idx; in rx_macro_put_iir_band_audio_mixer()
2931 int band_idx = ctl->band_idx; in rx_macro_put_iir_band_audio_mixer()
2935 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); in rx_macro_put_iir_band_audio_mixer()
2957 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_get_iir_band_audio_mixer()
2958 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_get_iir_band_audio_mixer()
2959 int iir_idx = ctl->iir_idx; in rx_macro_get_iir_band_audio_mixer()
2960 int band_idx = ctl->band_idx; in rx_macro_get_iir_band_audio_mixer()
2969 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); in rx_macro_get_iir_band_audio_mixer()
2978 (struct wcd_iir_filter_ctl *)kcontrol->private_value; in rx_macro_iir_filter_info()
2979 struct soc_bytes_ext *params = &ctl->bytes_ext; in rx_macro_iir_filter_info()
2981 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES; in rx_macro_iir_filter_info()
2982 ucontrol->count = params->max; in rx_macro_iir_filter_info()
2989 -84, 40, digital_gain),
2991 -84, 40, digital_gain),
2993 -84, 40, digital_gain),
2995 -84, 40, digital_gain),
3001 -84, 40, digital_gain),
3003 -84, 40, digital_gain),
3005 -84, 40, digital_gain),
3007 -84, 40, digital_gain),
3012 -84, 40, digital_gain),
3014 -84, 40, digital_gain),
3037 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
3040 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
3043 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
3046 CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
3049 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
3052 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
3055 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
3058 CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
3100 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); in rx_macro_enable_echo()
3102 int ec_tx = -1; in rx_macro_enable_echo()
3107 ec_tx = ((val & 0xf0) >> 0x4) - 1; in rx_macro_enable_echo()
3109 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3114 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3117 dev_err(component->dev, "%s: EC mix control not set correctly\n", in rx_macro_enable_echo()
3119 return -EINVAL; in rx_macro_enable_echo()
3149 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
3294 {"RX AIF3 PB", NULL, "RX_MCLK"},
3311 {"RX_MACRO RX0 MUX", "AIF3_PB", "RX AIF3 PB"},
3312 {"RX_MACRO RX1 MUX", "AIF3_PB", "RX AIF3 PB"},
3313 {"RX_MACRO RX2 MUX", "AIF3_PB", "RX AIF3 PB"},
3314 {"RX_MACRO RX3 MUX", "AIF3_PB", "RX AIF3 PB"},
3315 {"RX_MACRO RX4 MUX", "AIF3_PB", "RX AIF3 PB"},
3316 {"RX_MACRO RX5 MUX", "AIF3_PB", "RX AIF3 PB"},
3614 snd_soc_component_init_regmap(component, rx->regmap); in rx_macro_component_probe()
3635 switch (rx->codec_version) { in rx_macro_component_probe()
3656 return -EINVAL; in rx_macro_component_probe()
3659 rx->component = component; in rx_macro_component_probe()
3673 ret = clk_prepare_enable(rx->mclk); in swclk_gate_enable()
3675 dev_err(rx->dev, "unable to prepare mclk\n"); in swclk_gate_enable()
3681 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_enable()
3691 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in swclk_gate_disable()
3695 clk_disable_unprepare(rx->mclk); in swclk_gate_disable()
3703 regmap_read(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, &val); in swclk_gate_is_enabled()
3725 struct device *dev = rx->dev; in rx_macro_register_mclk_output()
3727 const char *clk_name = "lpass-rx-mclk"; in rx_macro_register_mclk_output()
3732 if (rx->npl) in rx_macro_register_mclk_output()
3733 parent_clk_name = __clk_get_name(rx->npl); in rx_macro_register_mclk_output()
3735 parent_clk_name = __clk_get_name(rx->mclk); in rx_macro_register_mclk_output()
3742 rx->hw.init = &init; in rx_macro_register_mclk_output()
3743 hw = &rx->hw; in rx_macro_register_mclk_output()
3744 ret = devm_clk_hw_register(rx->dev, hw); in rx_macro_register_mclk_output()
3752 .name = "RX-MACRO",
3764 struct device *dev = &pdev->dev; in rx_macro_probe()
3774 return -ENOMEM; in rx_macro_probe()
3776 rx->macro = devm_clk_get_optional(dev, "macro"); in rx_macro_probe()
3777 if (IS_ERR(rx->macro)) in rx_macro_probe()
3778 return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n"); in rx_macro_probe()
3780 rx->dcodec = devm_clk_get_optional(dev, "dcodec"); in rx_macro_probe()
3781 if (IS_ERR(rx->dcodec)) in rx_macro_probe()
3782 return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n"); in rx_macro_probe()
3784 rx->mclk = devm_clk_get(dev, "mclk"); in rx_macro_probe()
3785 if (IS_ERR(rx->mclk)) in rx_macro_probe()
3786 return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n"); in rx_macro_probe()
3789 rx->npl = devm_clk_get(dev, "npl"); in rx_macro_probe()
3790 if (IS_ERR(rx->npl)) in rx_macro_probe()
3791 return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n"); in rx_macro_probe()
3794 rx->fsgen = devm_clk_get(dev, "fsgen"); in rx_macro_probe()
3795 if (IS_ERR(rx->fsgen)) in rx_macro_probe()
3796 return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n"); in rx_macro_probe()
3798 rx->pds = lpass_macro_pds_init(dev); in rx_macro_probe()
3799 if (IS_ERR(rx->pds)) in rx_macro_probe()
3800 return PTR_ERR(rx->pds); in rx_macro_probe()
3802 ret = devm_add_action_or_reset(dev, lpass_macro_pds_exit_action, rx->pds); in rx_macro_probe()
3810 rx->codec_version = lpass_macro_get_codec_version(); in rx_macro_probe()
3813 switch (rx->codec_version) { in rx_macro_probe()
3819 rx->rxn_reg_stride = 0x80; in rx_macro_probe()
3820 rx->rxn_reg_stride2 = 0xc; in rx_macro_probe()
3824 return -ENOMEM; in rx_macro_probe()
3833 rx->rxn_reg_stride = 0xc0; in rx_macro_probe()
3834 rx->rxn_reg_stride2 = 0x0; in rx_macro_probe()
3838 return -ENOMEM; in rx_macro_probe()
3844 dev_err(dev, "Unsupported Codec version (%d)\n", rx->codec_version); in rx_macro_probe()
3845 return -EINVAL; in rx_macro_probe()
3852 return -ENOMEM; in rx_macro_probe()
3854 reg_config->reg_defaults = reg_defaults; in rx_macro_probe()
3855 reg_config->num_reg_defaults = def_count; in rx_macro_probe()
3857 rx->regmap = devm_regmap_init_mmio(dev, base, reg_config); in rx_macro_probe()
3858 if (IS_ERR(rx->regmap)) in rx_macro_probe()
3859 return PTR_ERR(rx->regmap); in rx_macro_probe()
3863 rx->dev = dev; in rx_macro_probe()
3866 clk_set_rate(rx->mclk, MCLK_FREQ); in rx_macro_probe()
3867 clk_set_rate(rx->npl, MCLK_FREQ); in rx_macro_probe()
3869 ret = clk_prepare_enable(rx->macro); in rx_macro_probe()
3873 ret = clk_prepare_enable(rx->dcodec); in rx_macro_probe()
3877 ret = clk_prepare_enable(rx->mclk); in rx_macro_probe()
3881 ret = clk_prepare_enable(rx->npl); in rx_macro_probe()
3885 ret = clk_prepare_enable(rx->fsgen); in rx_macro_probe()
3890 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3894 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3897 regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL, in rx_macro_probe()
3920 clk_disable_unprepare(rx->fsgen); in rx_macro_probe()
3922 clk_disable_unprepare(rx->npl); in rx_macro_probe()
3924 clk_disable_unprepare(rx->mclk); in rx_macro_probe()
3926 clk_disable_unprepare(rx->dcodec); in rx_macro_probe()
3928 clk_disable_unprepare(rx->macro); in rx_macro_probe()
3935 struct rx_macro *rx = dev_get_drvdata(&pdev->dev); in rx_macro_remove()
3937 clk_disable_unprepare(rx->mclk); in rx_macro_remove()
3938 clk_disable_unprepare(rx->npl); in rx_macro_remove()
3939 clk_disable_unprepare(rx->fsgen); in rx_macro_remove()
3940 clk_disable_unprepare(rx->macro); in rx_macro_remove()
3941 clk_disable_unprepare(rx->dcodec); in rx_macro_remove()
3946 .compatible = "qcom,sc7280-lpass-rx-macro",
3950 .compatible = "qcom,sm8250-lpass-rx-macro",
3953 .compatible = "qcom,sm8450-lpass-rx-macro",
3956 .compatible = "qcom,sm8550-lpass-rx-macro",
3958 .compatible = "qcom,sc8280xp-lpass-rx-macro",
3969 regcache_cache_only(rx->regmap, true); in rx_macro_runtime_suspend()
3970 regcache_mark_dirty(rx->regmap); in rx_macro_runtime_suspend()
3972 clk_disable_unprepare(rx->fsgen); in rx_macro_runtime_suspend()
3973 clk_disable_unprepare(rx->npl); in rx_macro_runtime_suspend()
3974 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_suspend()
3984 ret = clk_prepare_enable(rx->mclk); in rx_macro_runtime_resume()
3990 ret = clk_prepare_enable(rx->npl); in rx_macro_runtime_resume()
3996 ret = clk_prepare_enable(rx->fsgen); in rx_macro_runtime_resume()
4001 regcache_cache_only(rx->regmap, false); in rx_macro_runtime_resume()
4002 regcache_sync(rx->regmap); in rx_macro_runtime_resume()
4006 clk_disable_unprepare(rx->npl); in rx_macro_runtime_resume()
4008 clk_disable_unprepare(rx->mclk); in rx_macro_runtime_resume()