Lines Matching +full:0 +full:x078c
21 #define CDC_RX_TOP_TOP_CFG0 (0x0000)
22 #define CDC_RX_TOP_SWR_CTRL (0x0008)
23 #define CDC_RX_TOP_DEBUG (0x000C)
24 #define CDC_RX_TOP_DEBUG_BUS (0x0010)
25 #define CDC_RX_TOP_DEBUG_EN0 (0x0014)
26 #define CDC_RX_TOP_DEBUG_EN1 (0x0018)
27 #define CDC_RX_TOP_DEBUG_EN2 (0x001C)
28 #define CDC_RX_TOP_HPHL_COMP_WR_LSB (0x0020)
29 #define CDC_RX_TOP_HPHL_COMP_WR_MSB (0x0024)
30 #define CDC_RX_TOP_HPHL_COMP_LUT (0x0028)
32 #define CDC_RX_TOP_HPHL_COMP_RD_LSB (0x002C)
33 #define CDC_RX_TOP_HPHL_COMP_RD_MSB (0x0030)
34 #define CDC_RX_TOP_HPHR_COMP_WR_LSB (0x0034)
35 #define CDC_RX_TOP_HPHR_COMP_WR_MSB (0x0038)
36 #define CDC_RX_TOP_HPHR_COMP_LUT (0x003C)
37 #define CDC_RX_TOP_HPHR_COMP_RD_LSB (0x0040)
38 #define CDC_RX_TOP_HPHR_COMP_RD_MSB (0x0044)
39 #define CDC_RX_TOP_DSD0_DEBUG_CFG0 (0x0070)
40 #define CDC_RX_TOP_DSD0_DEBUG_CFG1 (0x0074)
41 #define CDC_RX_TOP_DSD0_DEBUG_CFG2 (0x0078)
42 #define CDC_RX_TOP_DSD0_DEBUG_CFG3 (0x007C)
43 #define CDC_RX_TOP_DSD1_DEBUG_CFG0 (0x0080)
44 #define CDC_RX_TOP_DSD1_DEBUG_CFG1 (0x0084)
45 #define CDC_RX_TOP_DSD1_DEBUG_CFG2 (0x0088)
46 #define CDC_RX_TOP_DSD1_DEBUG_CFG3 (0x008C)
47 #define CDC_RX_TOP_RX_I2S_CTL (0x0090)
48 #define CDC_RX_TOP_TX_I2S2_CTL (0x0094)
49 #define CDC_RX_TOP_I2S_CLK (0x0098)
50 #define CDC_RX_TOP_I2S_RESET (0x009C)
51 #define CDC_RX_TOP_I2S_MUX (0x00A0)
52 #define CDC_RX_CLK_RST_CTRL_MCLK_CONTROL (0x0100)
53 #define CDC_RX_CLK_MCLK_EN_MASK BIT(0)
54 #define CDC_RX_CLK_MCLK_ENABLE BIT(0)
57 #define CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0104)
58 #define CDC_RX_FS_MCLK_CNT_EN_MASK BIT(0)
59 #define CDC_RX_FS_MCLK_CNT_ENABLE BIT(0)
62 #define CDC_RX_CLK_RST_CTRL_SWR_CONTROL (0x0108)
63 #define CDC_RX_SWR_CLK_EN_MASK BIT(0)
66 #define CDC_RX_CLK_RST_CTRL_DSD_CONTROL (0x010C)
67 #define CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL (0x0110)
68 #define CDC_RX_SOFTCLIP_CRC (0x0140)
69 #define CDC_RX_SOFTCLIP_CLK_EN_MASK BIT(0)
70 #define CDC_RX_SOFTCLIP_SOFTCLIP_CTRL (0x0144)
71 #define CDC_RX_SOFTCLIP_EN_MASK BIT(0)
72 #define CDC_RX_INP_MUX_RX_INT0_CFG0 (0x0180)
73 #define CDC_RX_INTX_1_MIX_INP0_SEL_MASK GENMASK(3, 0)
75 #define CDC_RX_INP_MUX_RX_INT0_CFG1 (0x0184)
76 #define CDC_RX_INTX_2_SEL_MASK GENMASK(3, 0)
78 #define CDC_RX_INP_MUX_RX_INT1_CFG0 (0x0188)
79 #define CDC_RX_INP_MUX_RX_INT1_CFG1 (0x018C)
80 #define CDC_RX_INP_MUX_RX_INT2_CFG0 (0x0190)
81 #define CDC_RX_INP_MUX_RX_INT2_CFG1 (0x0194)
82 #define CDC_RX_INP_MUX_RX_MIX_CFG4 (0x0198)
83 #define CDC_RX_INP_MUX_RX_MIX_CFG5 (0x019C)
84 #define CDC_RX_INP_MUX_SIDETONE_SRC_CFG0 (0x01A0)
85 #define CDC_RX_CLSH_CRC (0x0200)
86 #define CDC_RX_CLSH_CLK_EN_MASK BIT(0)
87 #define CDC_RX_CLSH_DLY_CTRL (0x0204)
88 #define CDC_RX_CLSH_DECAY_CTRL (0x0208)
89 #define CDC_RX_CLSH_DECAY_RATE_MASK GENMASK(2, 0)
90 #define CDC_RX_CLSH_HPH_V_PA (0x020C)
91 #define CDC_RX_CLSH_HPH_V_PA_MIN_MASK GENMASK(5, 0)
92 #define CDC_RX_CLSH_EAR_V_PA (0x0210)
93 #define CDC_RX_CLSH_HPH_V_HD (0x0214)
94 #define CDC_RX_CLSH_EAR_V_HD (0x0218)
95 #define CDC_RX_CLSH_K1_MSB (0x021C)
96 #define CDC_RX_CLSH_K1_MSB_COEFF_MASK GENMASK(3, 0)
97 #define CDC_RX_CLSH_K1_LSB (0x0220)
98 #define CDC_RX_CLSH_K2_MSB (0x0224)
99 #define CDC_RX_CLSH_K2_LSB (0x0228)
100 #define CDC_RX_CLSH_IDLE_CTRL (0x022C)
101 #define CDC_RX_CLSH_IDLE_HPH (0x0230)
102 #define CDC_RX_CLSH_IDLE_EAR (0x0234)
103 #define CDC_RX_CLSH_TEST0 (0x0238)
104 #define CDC_RX_CLSH_TEST1 (0x023C)
105 #define CDC_RX_CLSH_OVR_VREF (0x0240)
106 #define CDC_RX_CLSH_CLSG_CTL (0x0244)
107 #define CDC_RX_CLSH_CLSG_CFG1 (0x0248)
108 #define CDC_RX_CLSH_CLSG_CFG2 (0x024C)
109 #define CDC_RX_BCL_VBAT_PATH_CTL (0x0280)
110 #define CDC_RX_BCL_VBAT_CFG (0x0284)
111 #define CDC_RX_BCL_VBAT_ADC_CAL1 (0x0288)
112 #define CDC_RX_BCL_VBAT_ADC_CAL2 (0x028C)
113 #define CDC_RX_BCL_VBAT_ADC_CAL3 (0x0290)
114 #define CDC_RX_BCL_VBAT_PK_EST1 (0x0294)
115 #define CDC_RX_BCL_VBAT_PK_EST2 (0x0298)
116 #define CDC_RX_BCL_VBAT_PK_EST3 (0x029C)
117 #define CDC_RX_BCL_VBAT_RF_PROC1 (0x02A0)
118 #define CDC_RX_BCL_VBAT_RF_PROC2 (0x02A4)
119 #define CDC_RX_BCL_VBAT_TAC1 (0x02A8)
120 #define CDC_RX_BCL_VBAT_TAC2 (0x02AC)
121 #define CDC_RX_BCL_VBAT_TAC3 (0x02B0)
122 #define CDC_RX_BCL_VBAT_TAC4 (0x02B4)
123 #define CDC_RX_BCL_VBAT_GAIN_UPD1 (0x02B8)
124 #define CDC_RX_BCL_VBAT_GAIN_UPD2 (0x02BC)
125 #define CDC_RX_BCL_VBAT_GAIN_UPD3 (0x02C0)
126 #define CDC_RX_BCL_VBAT_GAIN_UPD4 (0x02C4)
127 #define CDC_RX_BCL_VBAT_GAIN_UPD5 (0x02C8)
128 #define CDC_RX_BCL_VBAT_DEBUG1 (0x02CC)
129 #define CDC_RX_BCL_VBAT_GAIN_UPD_MON (0x02D0)
130 #define CDC_RX_BCL_VBAT_GAIN_MON_VAL (0x02D4)
131 #define CDC_RX_BCL_VBAT_BAN (0x02D8)
132 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD1 (0x02DC)
133 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD2 (0x02E0)
134 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD3 (0x02E4)
135 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD4 (0x02E8)
136 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD5 (0x02EC)
137 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD6 (0x02F0)
138 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD7 (0x02F4)
139 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD8 (0x02F8)
140 #define CDC_RX_BCL_VBAT_BCL_GAIN_UPD9 (0x02FC)
141 #define CDC_RX_BCL_VBAT_ATTN1 (0x0300)
142 #define CDC_RX_BCL_VBAT_ATTN2 (0x0304)
143 #define CDC_RX_BCL_VBAT_ATTN3 (0x0308)
144 #define CDC_RX_BCL_VBAT_DECODE_CTL1 (0x030C)
145 #define CDC_RX_BCL_VBAT_DECODE_CTL2 (0x0310)
146 #define CDC_RX_BCL_VBAT_DECODE_CFG1 (0x0314)
147 #define CDC_RX_BCL_VBAT_DECODE_CFG2 (0x0318)
148 #define CDC_RX_BCL_VBAT_DECODE_CFG3 (0x031C)
149 #define CDC_RX_BCL_VBAT_DECODE_CFG4 (0x0320)
150 #define CDC_RX_BCL_VBAT_DECODE_ST (0x0324)
151 #define CDC_RX_INTR_CTRL_CFG (0x0340)
152 #define CDC_RX_INTR_CTRL_CLR_COMMIT (0x0344)
153 #define CDC_RX_INTR_CTRL_PIN1_MASK0 (0x0360)
154 #define CDC_RX_INTR_CTRL_PIN1_STATUS0 (0x0368)
155 #define CDC_RX_INTR_CTRL_PIN1_CLEAR0 (0x0370)
156 #define CDC_RX_INTR_CTRL_PIN2_MASK0 (0x0380)
157 #define CDC_RX_INTR_CTRL_PIN2_STATUS0 (0x0388)
158 #define CDC_RX_INTR_CTRL_PIN2_CLEAR0 (0x0390)
159 #define CDC_RX_INTR_CTRL_LEVEL0 (0x03C0)
160 #define CDC_RX_INTR_CTRL_BYPASS0 (0x03C8)
161 #define CDC_RX_INTR_CTRL_SET0 (0x03D0)
162 #define CDC_RX_RXn_RX_PATH_CTL(rx, n) (0x0400 + rx->rxn_reg_stride * n)
163 #define CDC_RX_RX0_RX_PATH_CTL (0x0400)
169 #define CDC_RX_PATH_PCM_RATE_MASK GENMASK(3, 0)
170 #define CDC_RX_RXn_RX_PATH_CFG0(rx, n) (0x0404 + rx->rxn_reg_stride * n)
172 #define CDC_RX_RX0_RX_PATH_CFG0 (0x0404)
177 #define CDC_RX_RXn_RX_PATH_CFG1(rx, n) (0x0408 + rx->rxn_reg_stride * n)
179 #define CDC_RX_RX0_RX_PATH_CFG1 (0x0408)
181 #define CDC_RX_RXn_RX_PATH_CFG2(rx, n) (0x040C + rx->rxn_reg_stride * n)
182 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK GENMASK(1, 0)
183 #define CDC_RX_RX0_RX_PATH_CFG2 (0x040C)
184 #define CDC_RX_RXn_RX_PATH_CFG3(rx, n) (0x0410 + rx->rxn_reg_stride * n)
185 #define CDC_RX_RX0_RX_PATH_CFG3 (0x0410)
186 #define CDC_RX_DC_COEFF_SEL_MASK GENMASK(1, 0)
187 #define CDC_RX_DC_COEFF_SEL_TWO 0x2
188 #define CDC_RX_RXn_RX_VOL_CTL(rx, n) (0x0414 + rx->rxn_reg_stride * n)
189 #define CDC_RX_RX0_RX_VOL_CTL (0x0414)
190 #define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n) (0x0418 + rx->rxn_reg_stride * n)
191 #define CDC_RX_RXn_MIX_PCM_RATE_MASK GENMASK(3, 0)
195 #define CDC_RX_RX0_RX_PATH_MIX_CTL (0x0418)
196 #define CDC_RX_RX0_RX_PATH_MIX_CFG (0x041C)
197 #define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n) (0x0420 + rx->rxn_reg_stride * n)
198 #define CDC_RX_RX0_RX_VOL_MIX_CTL (0x0420)
199 #define CDC_RX_RX0_RX_PATH_SEC1 (0x0424)
200 #define CDC_RX_RX0_RX_PATH_SEC2 (0x0428)
201 #define CDC_RX_RX0_RX_PATH_SEC3 (0x042C)
202 #define CDC_RX_RXn_RX_PATH_SEC3(rx, n) (0x042c + rx->rxn_reg_stride * n)
203 #define CDC_RX_RX0_RX_PATH_SEC4 (0x0430)
204 #define CDC_RX_RX0_RX_PATH_SEC7 (0x0434)
206 (0x0434 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
207 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK GENMASK(2, 0)
208 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE 0x2
209 #define CDC_RX_RX0_RX_PATH_MIX_SEC0 (0x0438)
210 #define CDC_RX_RX0_RX_PATH_MIX_SEC1 (0x043C)
212 (0x0440 + (rx->rxn_reg_stride * n) + ((n > 1) ? rx->rxn_reg_stride2 : 0))
213 #define CDC_RX_RXn_DSM_CLK_EN_MASK BIT(0)
214 #define CDC_RX_RX0_RX_PATH_DSM_CTL (0x0440)
215 #define CDC_RX_RX0_RX_PATH_DSM_DATA1 (0x0444)
216 #define CDC_RX_RX0_RX_PATH_DSM_DATA2 (0x0448)
217 #define CDC_RX_RX0_RX_PATH_DSM_DATA3 (0x044C)
218 #define CDC_RX_RX0_RX_PATH_DSM_DATA4 (0x0450)
219 #define CDC_RX_RX0_RX_PATH_DSM_DATA5 (0x0454)
220 #define CDC_RX_RX0_RX_PATH_DSM_DATA6 (0x0458)
222 #define CDC_RX_RX1_RX_PATH_CTL (0x0480)
223 #define CDC_RX_RX1_RX_PATH_CFG0 (0x0484)
224 #define CDC_RX_RX1_RX_PATH_CFG1 (0x0488)
225 #define CDC_RX_RX1_RX_PATH_CFG2 (0x048C)
226 #define CDC_RX_RX1_RX_PATH_CFG3 (0x0490)
227 #define CDC_RX_RX1_RX_VOL_CTL (0x0494)
228 #define CDC_RX_RX1_RX_PATH_MIX_CTL (0x0498)
229 #define CDC_RX_RX1_RX_PATH_MIX_CFG (0x049C)
230 #define CDC_RX_RX1_RX_VOL_MIX_CTL (0x04A0)
231 #define CDC_RX_RX1_RX_PATH_SEC1 (0x04A4)
232 #define CDC_RX_RX1_RX_PATH_SEC2 (0x04A8)
233 #define CDC_RX_RX1_RX_PATH_SEC3 (0x04AC)
235 #define CDC_RX_RX1_RX_PATH_SEC4 (0x04B0)
236 #define CDC_RX_RX1_RX_PATH_SEC7 (0x04B4)
237 #define CDC_RX_RX1_RX_PATH_MIX_SEC0 (0x04B8)
238 #define CDC_RX_RX1_RX_PATH_MIX_SEC1 (0x04BC)
239 #define CDC_RX_RX1_RX_PATH_DSM_CTL (0x04C0)
240 #define CDC_RX_RX1_RX_PATH_DSM_DATA1 (0x04C4)
241 #define CDC_RX_RX1_RX_PATH_DSM_DATA2 (0x04C8)
242 #define CDC_RX_RX1_RX_PATH_DSM_DATA3 (0x04CC)
243 #define CDC_RX_RX1_RX_PATH_DSM_DATA4 (0x04D0)
244 #define CDC_RX_RX1_RX_PATH_DSM_DATA5 (0x04D4)
245 #define CDC_RX_RX1_RX_PATH_DSM_DATA6 (0x04D8)
246 #define CDC_RX_RX2_RX_PATH_CTL (0x0500)
247 #define CDC_RX_RX2_RX_PATH_CFG0 (0x0504)
250 #define CDC_RX_RX2_RX_PATH_CFG1 (0x0508)
251 #define CDC_RX_RX2_RX_PATH_CFG2 (0x050C)
252 #define CDC_RX_RX2_RX_PATH_CFG3 (0x0510)
253 #define CDC_RX_RX2_RX_VOL_CTL (0x0514)
254 #define CDC_RX_RX2_RX_PATH_MIX_CTL (0x0518)
255 #define CDC_RX_RX2_RX_PATH_MIX_CFG (0x051C)
256 #define CDC_RX_RX2_RX_VOL_MIX_CTL (0x0520)
257 #define CDC_RX_RX2_RX_PATH_SEC0 (0x0524)
258 #define CDC_RX_RX2_RX_PATH_SEC1 (0x0528)
259 #define CDC_RX_RX2_RX_PATH_SEC2 (0x052C)
260 #define CDC_RX_RX2_RX_PATH_SEC3 (0x0530)
261 #define CDC_RX_RX2_RX_PATH_SEC4 (0x0534)
262 #define CDC_RX_RX2_RX_PATH_SEC5 (0x0538)
263 #define CDC_RX_RX2_RX_PATH_SEC6 (0x053C)
264 #define CDC_RX_RX2_RX_PATH_SEC7 (0x0540)
265 #define CDC_RX_RX2_RX_PATH_MIX_SEC0 (0x0544)
266 #define CDC_RX_RX2_RX_PATH_MIX_SEC1 (0x0548)
267 #define CDC_RX_RX2_RX_PATH_DSM_CTL (0x054C)
270 #define CDC_2_5_RX_RX1_RX_PATH_CTL (0x04c0)
271 #define CDC_2_5_RX_RX1_RX_PATH_CFG0 (0x04c4)
272 #define CDC_2_5_RX_RX1_RX_PATH_CFG1 (0x04c8)
273 #define CDC_2_5_RX_RX1_RX_PATH_CFG2 (0x04cC)
274 #define CDC_2_5_RX_RX1_RX_PATH_CFG3 (0x04d0)
275 #define CDC_2_5_RX_RX1_RX_VOL_CTL (0x04d4)
276 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CTL (0x04d8)
277 #define CDC_2_5_RX_RX1_RX_PATH_MIX_CFG (0x04dC)
278 #define CDC_2_5_RX_RX1_RX_VOL_MIX_CTL (0x04e0)
279 #define CDC_2_5_RX_RX1_RX_PATH_SEC1 (0x04e4)
280 #define CDC_2_5_RX_RX1_RX_PATH_SEC2 (0x04e8)
281 #define CDC_2_5_RX_RX1_RX_PATH_SEC3 (0x04eC)
282 #define CDC_2_5_RX_RX1_RX_PATH_SEC4 (0x04f0)
283 #define CDC_2_5_RX_RX1_RX_PATH_SEC7 (0x04f4)
284 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0 (0x04f8)
285 #define CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1 (0x04fC)
286 #define CDC_2_5_RX_RX1_RX_PATH_DSM_CTL (0x0500)
287 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1 (0x0504)
288 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2 (0x0508)
289 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3 (0x050C)
290 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4 (0x0510)
291 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5 (0x0514)
292 #define CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6 (0x0518)
294 #define CDC_2_5_RX_RX2_RX_PATH_CTL (0x0580)
295 #define CDC_2_5_RX_RX2_RX_PATH_CFG0 (0x0584)
296 #define CDC_2_5_RX_RX2_RX_PATH_CFG1 (0x0588)
297 #define CDC_2_5_RX_RX2_RX_PATH_CFG2 (0x058C)
298 #define CDC_2_5_RX_RX2_RX_PATH_CFG3 (0x0590)
299 #define CDC_2_5_RX_RX2_RX_VOL_CTL (0x0594)
300 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CTL (0x0598)
301 #define CDC_2_5_RX_RX2_RX_PATH_MIX_CFG (0x059C)
302 #define CDC_2_5_RX_RX2_RX_VOL_MIX_CTL (0x05a0)
303 #define CDC_2_5_RX_RX2_RX_PATH_SEC0 (0x05a4)
304 #define CDC_2_5_RX_RX2_RX_PATH_SEC1 (0x05a8)
305 #define CDC_2_5_RX_RX2_RX_PATH_SEC2 (0x05aC)
306 #define CDC_2_5_RX_RX2_RX_PATH_SEC3 (0x05b0)
307 #define CDC_2_5_RX_RX2_RX_PATH_SEC4 (0x05b4)
308 #define CDC_2_5_RX_RX2_RX_PATH_SEC5 (0x05b8)
309 #define CDC_2_5_RX_RX2_RX_PATH_SEC6 (0x05bC)
310 #define CDC_2_5_RX_RX2_RX_PATH_SEC7 (0x05c0)
311 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0 (0x05c4)
312 #define CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1 (0x05c8)
313 #define CDC_2_5_RX_RX2_RX_PATH_DSM_CTL (0x05cC)
315 #define CDC_RX_IDLE_DETECT_PATH_CTL (0x0780)
316 #define CDC_RX_IDLE_DETECT_CFG0 (0x0784)
317 #define CDC_RX_IDLE_DETECT_CFG1 (0x0788)
318 #define CDC_RX_IDLE_DETECT_CFG2 (0x078C)
319 #define CDC_RX_IDLE_DETECT_CFG3 (0x0790)
320 #define CDC_RX_COMPANDERn_CTL0(n) (0x0800 + 0x40 * n)
321 #define CDC_RX_COMPANDERn_CLK_EN_MASK BIT(0)
324 #define CDC_RX_COMPANDER0_CTL0 (0x0800)
325 #define CDC_RX_COMPANDER0_CTL1 (0x0804)
326 #define CDC_RX_COMPANDER0_CTL2 (0x0808)
327 #define CDC_RX_COMPANDER0_CTL3 (0x080C)
328 #define CDC_RX_COMPANDER0_CTL4 (0x0810)
329 #define CDC_RX_COMPANDER0_CTL5 (0x0814)
330 #define CDC_RX_COMPANDER0_CTL6 (0x0818)
331 #define CDC_RX_COMPANDER0_CTL7 (0x081C)
332 #define CDC_RX_COMPANDER1_CTL0 (0x0840)
333 #define CDC_RX_COMPANDER1_CTL1 (0x0844)
334 #define CDC_RX_COMPANDER1_CTL2 (0x0848)
335 #define CDC_RX_COMPANDER1_CTL3 (0x084C)
336 #define CDC_RX_COMPANDER1_CTL4 (0x0850)
337 #define CDC_RX_COMPANDER1_CTL5 (0x0854)
338 #define CDC_RX_COMPANDER1_CTL6 (0x0858)
339 #define CDC_RX_COMPANDER1_CTL7 (0x085C)
341 #define CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL (0x0A00)
342 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL (0x0A04)
343 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL (0x0A08)
344 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL (0x0A0C)
345 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL (0x0A10)
346 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL (0x0A14)
347 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL (0x0A18)
348 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL (0x0A1C)
349 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL (0x0A20)
350 #define CDC_RX_SIDETONE_IIR0_IIR_CTL (0x0A24)
351 #define CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL (0x0A28)
352 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL (0x0A2C)
353 #define CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL (0x0A30)
354 #define CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL (0x0A80)
355 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL (0x0A84)
356 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL (0x0A88)
357 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL (0x0A8C)
358 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL (0x0A90)
359 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL (0x0A94)
360 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL (0x0A98)
361 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL (0x0A9C)
362 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL (0x0AA0)
363 #define CDC_RX_SIDETONE_IIR1_IIR_CTL (0x0AA4)
364 #define CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL (0x0AA8)
365 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL (0x0AAC)
366 #define CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL (0x0AB0)
367 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0 (0x0B00)
368 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1 (0x0B04)
369 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2 (0x0B08)
370 #define CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3 (0x0B0C)
371 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0 (0x0B10)
372 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1 (0x0B14)
373 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2 (0x0B18)
374 #define CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3 (0x0B1C)
375 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL (0x0B40)
376 #define CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1 (0x0B44)
377 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL (0x0B50)
378 #define CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1 (0x0B54)
379 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL (0x0C00)
380 #define CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0 (0x0C04)
381 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL (0x0C40)
382 #define CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0 (0x0C44)
383 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL (0x0C80)
384 #define CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0 (0x0C84)
385 #define CDC_RX_EC_ASRC0_CLK_RST_CTL (0x0D00)
386 #define CDC_RX_EC_ASRC0_CTL0 (0x0D04)
387 #define CDC_RX_EC_ASRC0_CTL1 (0x0D08)
388 #define CDC_RX_EC_ASRC0_FIFO_CTL (0x0D0C)
389 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB (0x0D10)
390 #define CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB (0x0D14)
391 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB (0x0D18)
392 #define CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB (0x0D1C)
393 #define CDC_RX_EC_ASRC0_STATUS_FIFO (0x0D20)
394 #define CDC_RX_EC_ASRC1_CLK_RST_CTL (0x0D40)
395 #define CDC_RX_EC_ASRC1_CTL0 (0x0D44)
396 #define CDC_RX_EC_ASRC1_CTL1 (0x0D48)
397 #define CDC_RX_EC_ASRC1_FIFO_CTL (0x0D4C)
398 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB (0x0D50)
399 #define CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB (0x0D54)
400 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB (0x0D58)
401 #define CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB (0x0D5C)
402 #define CDC_RX_EC_ASRC1_STATUS_FIFO (0x0D60)
403 #define CDC_RX_EC_ASRC2_CLK_RST_CTL (0x0D80)
404 #define CDC_RX_EC_ASRC2_CTL0 (0x0D84)
405 #define CDC_RX_EC_ASRC2_CTL1 (0x0D88)
406 #define CDC_RX_EC_ASRC2_FIFO_CTL (0x0D8C)
407 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB (0x0D90)
408 #define CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB (0x0D94)
409 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB (0x0D98)
410 #define CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB (0x0D9C)
411 #define CDC_RX_EC_ASRC2_STATUS_FIFO (0x0DA0)
412 #define CDC_RX_DSD0_PATH_CTL (0x0F00)
413 #define CDC_RX_DSD0_CFG0 (0x0F04)
414 #define CDC_RX_DSD0_CFG1 (0x0F08)
415 #define CDC_RX_DSD0_CFG2 (0x0F0C)
416 #define CDC_RX_DSD1_PATH_CTL (0x0F80)
417 #define CDC_RX_DSD1_CFG0 (0x0F84)
418 #define CDC_RX_DSD1_CFG1 (0x0F88)
419 #define CDC_RX_DSD1_CFG2 (0x0F8C)
420 #define RX_MAX_OFFSET (0x0F8C)
444 #define RX_MACRO_EC_MIX_TX0_MASK 0xf0
445 #define RX_MACRO_EC_MIX_TX1_MASK 0x0f
446 #define RX_MACRO_EC_MIX_TX2_MASK 0x0f
464 {0x40, 0x00},
465 {0x4C, 0x00},
466 {0x5A, 0x00},
467 {0x6B, 0x00},
468 {0x7F, 0x00},
469 {0x97, 0x00},
470 {0xB3, 0x00},
471 {0xD5, 0x00},
472 {0xFD, 0x00},
473 {0x2D, 0x01},
474 {0x66, 0x01},
475 {0xA7, 0x01},
476 {0xF8, 0x01},
477 {0x57, 0x02},
478 {0xC7, 0x02},
479 {0x4B, 0x03},
480 {0xE9, 0x03},
481 {0xA3, 0x04},
482 {0x7D, 0x05},
483 {0x90, 0x06},
484 {0xD1, 0x07},
485 {0x49, 0x09},
486 {0x00, 0x0B},
487 {0x01, 0x0D},
488 {0x59, 0x0F},
491 {0x40, 0x00},
492 {0x4C, 0x00},
493 {0x5A, 0x00},
494 {0x6B, 0x00},
495 {0x80, 0x00},
496 {0x98, 0x00},
497 {0xB4, 0x00},
498 {0xD5, 0x00},
499 {0xFE, 0x00},
500 {0x2E, 0x01},
501 {0x66, 0x01},
502 {0xA9, 0x01},
503 {0xF8, 0x01},
504 {0x56, 0x02},
505 {0xC4, 0x02},
506 {0x4F, 0x03},
507 {0xF0, 0x03},
508 {0xAE, 0x04},
509 {0x8B, 0x05},
510 {0x8E, 0x06},
511 {0xBC, 0x07},
512 {0x56, 0x09},
513 {0x0F, 0x0B},
514 {0x13, 0x0D},
515 {0x6F, 0x0F},
543 RX_MACRO_EC0_MUX = 0,
550 INTn_1_INP_SEL_ZERO = 0,
564 INTn_2_INP_SEL_ZERO = 0,
580 IIR0 = 0,
587 BAND1 = 0,
616 {8000, 0x0}, {16000, 0x1}, {32000, 0x3}, {48000, 0x4}, {96000, 0x5},
617 {192000, 0x6}, {384000, 0x7}, {44100, 0x9}, {88200, 0xA},
618 {176400, 0xB}, {352800, 0xC},
632 RX_MACRO_AIF1_CAP = 0,
742 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG5, 0, 4, rx_echo_mux_text);
744 SOC_ENUM_SINGLE(CDC_RX_INP_MUX_RX_MIX_CFG4, 0, 4, rx_echo_mux_text);
748 static SOC_ENUM_SINGLE_DECL(rx_int0_2_enum, CDC_RX_INP_MUX_RX_INT0_CFG1, 0,
750 static SOC_ENUM_SINGLE_DECL(rx_int1_2_enum, CDC_RX_INP_MUX_RX_INT1_CFG1, 0,
752 static SOC_ENUM_SINGLE_DECL(rx_int2_2_enum, CDC_RX_INP_MUX_RX_INT2_CFG1, 0,
755 static SOC_ENUM_SINGLE_DECL(rx_int0_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT0_CFG0, 0,
761 static SOC_ENUM_SINGLE_DECL(rx_int1_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT1_CFG0, 0,
767 static SOC_ENUM_SINGLE_DECL(rx_int2_1_mix_inp0_enum, CDC_RX_INP_MUX_RX_INT2_CFG0, 0,
780 static SOC_ENUM_SINGLE_DECL(iir0_inp0_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0,
782 static SOC_ENUM_SINGLE_DECL(iir0_inp1_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0,
784 static SOC_ENUM_SINGLE_DECL(iir0_inp2_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0,
786 static SOC_ENUM_SINGLE_DECL(iir0_inp3_enum, CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0,
788 static SOC_ENUM_SINGLE_DECL(iir1_inp0_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0,
790 static SOC_ENUM_SINGLE_DECL(iir1_inp1_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0,
792 static SOC_ENUM_SINGLE_DECL(iir1_inp2_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0,
794 static SOC_ENUM_SINGLE_DECL(iir1_inp3_enum, CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0,
797 static SOC_ENUM_SINGLE_DECL(rx_int0_1_interp_enum, SND_SOC_NOPM, 0,
799 static SOC_ENUM_SINGLE_DECL(rx_int1_1_interp_enum, SND_SOC_NOPM, 0,
801 static SOC_ENUM_SINGLE_DECL(rx_int2_1_interp_enum, SND_SOC_NOPM, 0,
803 static SOC_ENUM_SINGLE_DECL(rx_int0_2_interp_enum, SND_SOC_NOPM, 0,
805 static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
807 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
809 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
811 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
813 static SOC_ENUM_SINGLE_DECL(rx_2_5_int1_dem_inp_enum, CDC_2_5_RX_RX1_RX_PATH_CFG1, 0,
816 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
817 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
818 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
819 static SOC_ENUM_SINGLE_DECL(rx_macro_rx3_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
820 static SOC_ENUM_SINGLE_DECL(rx_macro_rx4_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
821 static SOC_ENUM_SINGLE_DECL(rx_macro_rx5_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
890 { CDC_RX_TOP_TOP_CFG0, 0x00 },
891 { CDC_RX_TOP_SWR_CTRL, 0x00 },
892 { CDC_RX_TOP_DEBUG, 0x00 },
893 { CDC_RX_TOP_DEBUG_BUS, 0x00 },
894 { CDC_RX_TOP_DEBUG_EN0, 0x00 },
895 { CDC_RX_TOP_DEBUG_EN1, 0x00 },
896 { CDC_RX_TOP_DEBUG_EN2, 0x00 },
897 { CDC_RX_TOP_HPHL_COMP_WR_LSB, 0x00 },
898 { CDC_RX_TOP_HPHL_COMP_WR_MSB, 0x00 },
899 { CDC_RX_TOP_HPHL_COMP_LUT, 0x00 },
900 { CDC_RX_TOP_HPHL_COMP_RD_LSB, 0x00 },
901 { CDC_RX_TOP_HPHL_COMP_RD_MSB, 0x00 },
902 { CDC_RX_TOP_HPHR_COMP_WR_LSB, 0x00 },
903 { CDC_RX_TOP_HPHR_COMP_WR_MSB, 0x00 },
904 { CDC_RX_TOP_HPHR_COMP_LUT, 0x00 },
905 { CDC_RX_TOP_HPHR_COMP_RD_LSB, 0x00 },
906 { CDC_RX_TOP_HPHR_COMP_RD_MSB, 0x00 },
907 { CDC_RX_TOP_DSD0_DEBUG_CFG0, 0x11 },
908 { CDC_RX_TOP_DSD0_DEBUG_CFG1, 0x20 },
909 { CDC_RX_TOP_DSD0_DEBUG_CFG2, 0x00 },
910 { CDC_RX_TOP_DSD0_DEBUG_CFG3, 0x00 },
911 { CDC_RX_TOP_DSD1_DEBUG_CFG0, 0x11 },
912 { CDC_RX_TOP_DSD1_DEBUG_CFG1, 0x20 },
913 { CDC_RX_TOP_DSD1_DEBUG_CFG2, 0x00 },
914 { CDC_RX_TOP_DSD1_DEBUG_CFG3, 0x00 },
915 { CDC_RX_TOP_RX_I2S_CTL, 0x0C },
916 { CDC_RX_TOP_TX_I2S2_CTL, 0x0C },
917 { CDC_RX_TOP_I2S_CLK, 0x0C },
918 { CDC_RX_TOP_I2S_RESET, 0x00 },
919 { CDC_RX_TOP_I2S_MUX, 0x00 },
920 { CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
921 { CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
922 { CDC_RX_CLK_RST_CTRL_SWR_CONTROL, 0x00 },
923 { CDC_RX_CLK_RST_CTRL_DSD_CONTROL, 0x00 },
924 { CDC_RX_CLK_RST_CTRL_ASRC_SHARE_CONTROL, 0x08 },
925 { CDC_RX_SOFTCLIP_CRC, 0x00 },
926 { CDC_RX_SOFTCLIP_SOFTCLIP_CTRL, 0x38 },
927 { CDC_RX_INP_MUX_RX_INT0_CFG0, 0x00 },
928 { CDC_RX_INP_MUX_RX_INT0_CFG1, 0x00 },
929 { CDC_RX_INP_MUX_RX_INT1_CFG0, 0x00 },
930 { CDC_RX_INP_MUX_RX_INT1_CFG1, 0x00 },
931 { CDC_RX_INP_MUX_RX_INT2_CFG0, 0x00 },
932 { CDC_RX_INP_MUX_RX_INT2_CFG1, 0x00 },
933 { CDC_RX_INP_MUX_RX_MIX_CFG4, 0x00 },
934 { CDC_RX_INP_MUX_RX_MIX_CFG5, 0x00 },
935 { CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0x00 },
936 { CDC_RX_CLSH_CRC, 0x00 },
937 { CDC_RX_CLSH_DLY_CTRL, 0x03 },
938 { CDC_RX_CLSH_DECAY_CTRL, 0x02 },
939 { CDC_RX_CLSH_HPH_V_PA, 0x1C },
940 { CDC_RX_CLSH_EAR_V_PA, 0x39 },
941 { CDC_RX_CLSH_HPH_V_HD, 0x0C },
942 { CDC_RX_CLSH_EAR_V_HD, 0x0C },
943 { CDC_RX_CLSH_K1_MSB, 0x01 },
944 { CDC_RX_CLSH_K1_LSB, 0x00 },
945 { CDC_RX_CLSH_K2_MSB, 0x00 },
946 { CDC_RX_CLSH_K2_LSB, 0x80 },
947 { CDC_RX_CLSH_IDLE_CTRL, 0x00 },
948 { CDC_RX_CLSH_IDLE_HPH, 0x00 },
949 { CDC_RX_CLSH_IDLE_EAR, 0x00 },
950 { CDC_RX_CLSH_TEST0, 0x07 },
951 { CDC_RX_CLSH_TEST1, 0x00 },
952 { CDC_RX_CLSH_OVR_VREF, 0x00 },
953 { CDC_RX_CLSH_CLSG_CTL, 0x02 },
954 { CDC_RX_CLSH_CLSG_CFG1, 0x9A },
955 { CDC_RX_CLSH_CLSG_CFG2, 0x10 },
956 { CDC_RX_BCL_VBAT_PATH_CTL, 0x00 },
957 { CDC_RX_BCL_VBAT_CFG, 0x10 },
958 { CDC_RX_BCL_VBAT_ADC_CAL1, 0x00 },
959 { CDC_RX_BCL_VBAT_ADC_CAL2, 0x00 },
960 { CDC_RX_BCL_VBAT_ADC_CAL3, 0x04 },
961 { CDC_RX_BCL_VBAT_PK_EST1, 0xE0 },
962 { CDC_RX_BCL_VBAT_PK_EST2, 0x01 },
963 { CDC_RX_BCL_VBAT_PK_EST3, 0x40 },
964 { CDC_RX_BCL_VBAT_RF_PROC1, 0x2A },
965 { CDC_RX_BCL_VBAT_RF_PROC2, 0x00 },
966 { CDC_RX_BCL_VBAT_TAC1, 0x00 },
967 { CDC_RX_BCL_VBAT_TAC2, 0x18 },
968 { CDC_RX_BCL_VBAT_TAC3, 0x18 },
969 { CDC_RX_BCL_VBAT_TAC4, 0x03 },
970 { CDC_RX_BCL_VBAT_GAIN_UPD1, 0x01 },
971 { CDC_RX_BCL_VBAT_GAIN_UPD2, 0x00 },
972 { CDC_RX_BCL_VBAT_GAIN_UPD3, 0x00 },
973 { CDC_RX_BCL_VBAT_GAIN_UPD4, 0x64 },
974 { CDC_RX_BCL_VBAT_GAIN_UPD5, 0x01 },
975 { CDC_RX_BCL_VBAT_DEBUG1, 0x00 },
976 { CDC_RX_BCL_VBAT_GAIN_UPD_MON, 0x00 },
977 { CDC_RX_BCL_VBAT_GAIN_MON_VAL, 0x00 },
978 { CDC_RX_BCL_VBAT_BAN, 0x0C },
979 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD1, 0x00 },
980 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD2, 0x77 },
981 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD3, 0x01 },
982 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD4, 0x00 },
983 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD5, 0x4B },
984 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD6, 0x00 },
985 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD7, 0x01 },
986 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD8, 0x00 },
987 { CDC_RX_BCL_VBAT_BCL_GAIN_UPD9, 0x00 },
988 { CDC_RX_BCL_VBAT_ATTN1, 0x04 },
989 { CDC_RX_BCL_VBAT_ATTN2, 0x08 },
990 { CDC_RX_BCL_VBAT_ATTN3, 0x0C },
991 { CDC_RX_BCL_VBAT_DECODE_CTL1, 0xE0 },
992 { CDC_RX_BCL_VBAT_DECODE_CTL2, 0x00 },
993 { CDC_RX_BCL_VBAT_DECODE_CFG1, 0x00 },
994 { CDC_RX_BCL_VBAT_DECODE_CFG2, 0x00 },
995 { CDC_RX_BCL_VBAT_DECODE_CFG3, 0x00 },
996 { CDC_RX_BCL_VBAT_DECODE_CFG4, 0x00 },
997 { CDC_RX_BCL_VBAT_DECODE_ST, 0x00 },
998 { CDC_RX_INTR_CTRL_CFG, 0x00 },
999 { CDC_RX_INTR_CTRL_CLR_COMMIT, 0x00 },
1000 { CDC_RX_INTR_CTRL_PIN1_MASK0, 0xFF },
1001 { CDC_RX_INTR_CTRL_PIN1_STATUS0, 0x00 },
1002 { CDC_RX_INTR_CTRL_PIN1_CLEAR0, 0x00 },
1003 { CDC_RX_INTR_CTRL_PIN2_MASK0, 0xFF },
1004 { CDC_RX_INTR_CTRL_PIN2_STATUS0, 0x00 },
1005 { CDC_RX_INTR_CTRL_PIN2_CLEAR0, 0x00 },
1006 { CDC_RX_INTR_CTRL_LEVEL0, 0x00 },
1007 { CDC_RX_INTR_CTRL_BYPASS0, 0x00 },
1008 { CDC_RX_INTR_CTRL_SET0, 0x00 },
1009 { CDC_RX_RX0_RX_PATH_CTL, 0x04 },
1010 { CDC_RX_RX0_RX_PATH_CFG0, 0x00 },
1011 { CDC_RX_RX0_RX_PATH_CFG1, 0x64 },
1012 { CDC_RX_RX0_RX_PATH_CFG2, 0x8F },
1013 { CDC_RX_RX0_RX_PATH_CFG3, 0x00 },
1014 { CDC_RX_RX0_RX_VOL_CTL, 0x00 },
1015 { CDC_RX_RX0_RX_PATH_MIX_CTL, 0x04 },
1016 { CDC_RX_RX0_RX_PATH_MIX_CFG, 0x7E },
1017 { CDC_RX_RX0_RX_VOL_MIX_CTL, 0x00 },
1018 { CDC_RX_RX0_RX_PATH_SEC1, 0x08 },
1019 { CDC_RX_RX0_RX_PATH_SEC2, 0x00 },
1020 { CDC_RX_RX0_RX_PATH_SEC3, 0x00 },
1021 { CDC_RX_RX0_RX_PATH_SEC4, 0x00 },
1022 { CDC_RX_RX0_RX_PATH_SEC7, 0x00 },
1023 { CDC_RX_RX0_RX_PATH_MIX_SEC0, 0x08 },
1024 { CDC_RX_RX0_RX_PATH_MIX_SEC1, 0x00 },
1025 { CDC_RX_RX0_RX_PATH_DSM_CTL, 0x08 },
1026 { CDC_RX_RX0_RX_PATH_DSM_DATA1, 0x00 },
1027 { CDC_RX_RX0_RX_PATH_DSM_DATA2, 0x00 },
1028 { CDC_RX_RX0_RX_PATH_DSM_DATA3, 0x00 },
1029 { CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
1030 { CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
1031 { CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
1032 { CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
1033 { CDC_RX_IDLE_DETECT_CFG0, 0x07 },
1034 { CDC_RX_IDLE_DETECT_CFG1, 0x3C },
1035 { CDC_RX_IDLE_DETECT_CFG2, 0x00 },
1036 { CDC_RX_IDLE_DETECT_CFG3, 0x00 },
1037 { CDC_RX_COMPANDER0_CTL0, 0x60 },
1038 { CDC_RX_COMPANDER0_CTL1, 0xDB },
1039 { CDC_RX_COMPANDER0_CTL2, 0xFF },
1040 { CDC_RX_COMPANDER0_CTL3, 0x35 },
1041 { CDC_RX_COMPANDER0_CTL4, 0xFF },
1042 { CDC_RX_COMPANDER0_CTL5, 0x00 },
1043 { CDC_RX_COMPANDER0_CTL6, 0x01 },
1044 { CDC_RX_COMPANDER0_CTL7, 0x28 },
1045 { CDC_RX_COMPANDER1_CTL0, 0x60 },
1046 { CDC_RX_COMPANDER1_CTL1, 0xDB },
1047 { CDC_RX_COMPANDER1_CTL2, 0xFF },
1048 { CDC_RX_COMPANDER1_CTL3, 0x35 },
1049 { CDC_RX_COMPANDER1_CTL4, 0xFF },
1050 { CDC_RX_COMPANDER1_CTL5, 0x00 },
1051 { CDC_RX_COMPANDER1_CTL6, 0x01 },
1052 { CDC_RX_COMPANDER1_CTL7, 0x28 },
1053 { CDC_RX_SIDETONE_IIR0_IIR_PATH_CTL, 0x00 },
1054 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B1_CTL, 0x00 },
1055 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B2_CTL, 0x00 },
1056 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B3_CTL, 0x00 },
1057 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B4_CTL, 0x00 },
1058 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B5_CTL, 0x00 },
1059 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B6_CTL, 0x00 },
1060 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B7_CTL, 0x00 },
1061 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_B8_CTL, 0x00 },
1062 { CDC_RX_SIDETONE_IIR0_IIR_CTL, 0x40 },
1063 { CDC_RX_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL, 0x00 },
1064 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL, 0x00 },
1065 { CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL, 0x00 },
1066 { CDC_RX_SIDETONE_IIR1_IIR_PATH_CTL, 0x00 },
1067 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B1_CTL, 0x00 },
1068 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B2_CTL, 0x00 },
1069 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B3_CTL, 0x00 },
1070 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B4_CTL, 0x00 },
1071 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B5_CTL, 0x00 },
1072 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B6_CTL, 0x00 },
1073 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B7_CTL, 0x00 },
1074 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_B8_CTL, 0x00 },
1075 { CDC_RX_SIDETONE_IIR1_IIR_CTL, 0x40 },
1076 { CDC_RX_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL, 0x00 },
1077 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B1_CTL, 0x00 },
1078 { CDC_RX_SIDETONE_IIR1_IIR_COEF_B2_CTL, 0x00 },
1079 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG0, 0x00 },
1080 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG1, 0x00 },
1081 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG2, 0x00 },
1082 { CDC_RX_IIR_INP_MUX_IIR0_MIX_CFG3, 0x00 },
1083 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG0, 0x00 },
1084 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG1, 0x00 },
1085 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG2, 0x00 },
1086 { CDC_RX_IIR_INP_MUX_IIR1_MIX_CFG3, 0x00 },
1087 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CTL, 0x04 },
1088 { CDC_RX_SIDETONE_SRC0_ST_SRC_PATH_CFG1, 0x00 },
1089 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL, 0x04 },
1090 { CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CFG1, 0x00 },
1091 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_PATH_CTL, 0x00 },
1092 { CDC_RX_EC_REF_HQ0_EC_REF_HQ_CFG0, 0x01 },
1093 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_PATH_CTL, 0x00 },
1094 { CDC_RX_EC_REF_HQ1_EC_REF_HQ_CFG0, 0x01 },
1095 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_PATH_CTL, 0x00 },
1096 { CDC_RX_EC_REF_HQ2_EC_REF_HQ_CFG0, 0x01 },
1097 { CDC_RX_EC_ASRC0_CLK_RST_CTL, 0x00 },
1098 { CDC_RX_EC_ASRC0_CTL0, 0x00 },
1099 { CDC_RX_EC_ASRC0_CTL1, 0x00 },
1100 { CDC_RX_EC_ASRC0_FIFO_CTL, 0xA8 },
1101 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_LSB, 0x00 },
1102 { CDC_RX_EC_ASRC0_STATUS_FMIN_CNTR_MSB, 0x00 },
1103 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_LSB, 0x00 },
1104 { CDC_RX_EC_ASRC0_STATUS_FMAX_CNTR_MSB, 0x00 },
1105 { CDC_RX_EC_ASRC0_STATUS_FIFO, 0x00 },
1106 { CDC_RX_EC_ASRC1_CLK_RST_CTL, 0x00 },
1107 { CDC_RX_EC_ASRC1_CTL0, 0x00 },
1108 { CDC_RX_EC_ASRC1_CTL1, 0x00 },
1109 { CDC_RX_EC_ASRC1_FIFO_CTL, 0xA8 },
1110 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_LSB, 0x00 },
1111 { CDC_RX_EC_ASRC1_STATUS_FMIN_CNTR_MSB, 0x00 },
1112 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_LSB, 0x00 },
1113 { CDC_RX_EC_ASRC1_STATUS_FMAX_CNTR_MSB, 0x00 },
1114 { CDC_RX_EC_ASRC1_STATUS_FIFO, 0x00 },
1115 { CDC_RX_EC_ASRC2_CLK_RST_CTL, 0x00 },
1116 { CDC_RX_EC_ASRC2_CTL0, 0x00 },
1117 { CDC_RX_EC_ASRC2_CTL1, 0x00 },
1118 { CDC_RX_EC_ASRC2_FIFO_CTL, 0xA8 },
1119 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_LSB, 0x00 },
1120 { CDC_RX_EC_ASRC2_STATUS_FMIN_CNTR_MSB, 0x00 },
1121 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_LSB, 0x00 },
1122 { CDC_RX_EC_ASRC2_STATUS_FMAX_CNTR_MSB, 0x00 },
1123 { CDC_RX_EC_ASRC2_STATUS_FIFO, 0x00 },
1124 { CDC_RX_DSD0_PATH_CTL, 0x00 },
1125 { CDC_RX_DSD0_CFG0, 0x00 },
1126 { CDC_RX_DSD0_CFG1, 0x62 },
1127 { CDC_RX_DSD0_CFG2, 0x96 },
1128 { CDC_RX_DSD1_PATH_CTL, 0x00 },
1129 { CDC_RX_DSD1_CFG0, 0x00 },
1130 { CDC_RX_DSD1_CFG1, 0x62 },
1131 { CDC_RX_DSD1_CFG2, 0x96 },
1135 { CDC_2_5_RX_RX1_RX_PATH_CTL, 0x04 },
1136 { CDC_2_5_RX_RX1_RX_PATH_CFG0, 0x00 },
1137 { CDC_2_5_RX_RX1_RX_PATH_CFG1, 0x64 },
1138 { CDC_2_5_RX_RX1_RX_PATH_CFG2, 0x8F },
1139 { CDC_2_5_RX_RX1_RX_PATH_CFG3, 0x00 },
1140 { CDC_2_5_RX_RX1_RX_VOL_CTL, 0x00 },
1141 { CDC_2_5_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
1142 { CDC_2_5_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
1143 { CDC_2_5_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
1144 { CDC_2_5_RX_RX1_RX_PATH_SEC1, 0x08 },
1145 { CDC_2_5_RX_RX1_RX_PATH_SEC2, 0x00 },
1146 { CDC_2_5_RX_RX1_RX_PATH_SEC3, 0x00 },
1147 { CDC_2_5_RX_RX1_RX_PATH_SEC4, 0x00 },
1148 { CDC_2_5_RX_RX1_RX_PATH_SEC7, 0x00 },
1149 { CDC_2_5_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
1150 { CDC_2_5_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
1151 { CDC_2_5_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
1152 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
1153 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
1154 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
1155 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
1156 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
1157 { CDC_2_5_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1158 { CDC_2_5_RX_RX2_RX_PATH_CTL, 0x04 },
1159 { CDC_2_5_RX_RX2_RX_PATH_CFG0, 0x00 },
1160 { CDC_2_5_RX_RX2_RX_PATH_CFG1, 0x64 },
1161 { CDC_2_5_RX_RX2_RX_PATH_CFG2, 0x8F },
1162 { CDC_2_5_RX_RX2_RX_PATH_CFG3, 0x00 },
1163 { CDC_2_5_RX_RX2_RX_VOL_CTL, 0x00 },
1164 { CDC_2_5_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1165 { CDC_2_5_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1166 { CDC_2_5_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1167 { CDC_2_5_RX_RX2_RX_PATH_SEC0, 0x04 },
1168 { CDC_2_5_RX_RX2_RX_PATH_SEC1, 0x08 },
1169 { CDC_2_5_RX_RX2_RX_PATH_SEC2, 0x00 },
1170 { CDC_2_5_RX_RX2_RX_PATH_SEC3, 0x00 },
1171 { CDC_2_5_RX_RX2_RX_PATH_SEC4, 0x00 },
1172 { CDC_2_5_RX_RX2_RX_PATH_SEC5, 0x00 },
1173 { CDC_2_5_RX_RX2_RX_PATH_SEC6, 0x00 },
1174 { CDC_2_5_RX_RX2_RX_PATH_SEC7, 0x00 },
1175 { CDC_2_5_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1176 { CDC_2_5_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1177 { CDC_2_5_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1181 { CDC_RX_RX1_RX_PATH_CTL, 0x04 },
1182 { CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
1183 { CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
1184 { CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
1185 { CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
1186 { CDC_RX_RX1_RX_VOL_CTL, 0x00 },
1187 { CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
1188 { CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
1189 { CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
1190 { CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
1191 { CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
1192 { CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
1193 { CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
1194 { CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
1195 { CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
1196 { CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
1197 { CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
1198 { CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
1199 { CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
1200 { CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
1201 { CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
1202 { CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
1203 { CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
1204 { CDC_RX_RX2_RX_PATH_CTL, 0x04 },
1205 { CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
1206 { CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
1207 { CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
1208 { CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
1209 { CDC_RX_RX2_RX_VOL_CTL, 0x00 },
1210 { CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
1211 { CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
1212 { CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
1213 { CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
1214 { CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
1215 { CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
1216 { CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
1217 { CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
1218 { CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
1219 { CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
1220 { CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
1221 { CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
1222 { CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
1223 { CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
1692 val = ucontrol->value.enumerated.item[0]; in rx_macro_int_dem_inp_mux_put()
1694 if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0)) in rx_macro_int_dem_inp_mux_put()
1695 look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); in rx_macro_int_dem_inp_mux_put()
1706 CDC_RX_DLY_ZN_EN_MASK, 0); in rx_macro_int_dem_inp_mux_put()
1742 for (j = 0; j < INTERP_MAX; j++) { in rx_macro_set_prim_interpolator_rate()
1765 return 0; in rx_macro_set_prim_interpolator_rate()
1783 for (j = 0; j < INTERP_MAX; j++) { in rx_macro_set_mix_interpolator_rate()
1796 return 0; in rx_macro_set_mix_interpolator_rate()
1802 int rate_val = 0; in rx_macro_set_interpolator_rate()
1805 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) in rx_macro_set_interpolator_rate()
1839 return 0; in rx_macro_hw_params()
1848 u16 val, mask = 0, cnt = 0, temp; in rx_macro_get_channel_map()
1862 * CDC_DMA_RX_0 port drives RX0/RX1 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1863 * CDC_DMA_RX_1 port drives RX2/RX3 -- ch_mask 0x1/0x2/0x3 in rx_macro_get_channel_map()
1864 * CDC_DMA_RX_2 port drives RX4 -- ch_mask 0x1 in rx_macro_get_channel_map()
1865 * CDC_DMA_RX_3 port drives RX5 -- ch_mask 0x1 in rx_macro_get_channel_map()
1871 if (mask & 0x0C) in rx_macro_get_channel_map()
1873 if ((mask & 0x10) || (mask & 0x20)) in rx_macro_get_channel_map()
1874 mask = 0x1; in rx_macro_get_channel_map()
1881 mask |= 0x1; in rx_macro_get_channel_map()
1885 mask |= 0x2; in rx_macro_get_channel_map()
1891 mask |= 0x4; in rx_macro_get_channel_map()
1901 return 0; in rx_macro_get_channel_map()
1917 for (j = 0; j < INTERP_MAX; j++) { in rx_macro_digital_mute()
1931 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); in rx_macro_digital_mute()
1933 CDC_RX_PATH_PGA_MUTE_MASK, 0x0); in rx_macro_digital_mute()
1941 if (snd_soc_component_read(component, dsm_reg) & 0x01) { in rx_macro_digital_mute()
1942 if (int_mux_cfg0_val || (int_mux_cfg1_val & 0xF0)) in rx_macro_digital_mute()
1943 snd_soc_component_update_bits(component, reg, 0x20, 0x20); in rx_macro_digital_mute()
1944 if (int_mux_cfg1_val & 0x0F) { in rx_macro_digital_mute()
1945 snd_soc_component_update_bits(component, reg, 0x20, 0x20); in rx_macro_digital_mute()
1946 snd_soc_component_update_bits(component, mix_reg, 0x20, in rx_macro_digital_mute()
1947 0x20); in rx_macro_digital_mute()
1955 return 0; in rx_macro_digital_mute()
2042 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2049 CDC_RX_FS_MCLK_CNT_CLR_MASK, 0x00); in rx_macro_mclk_enable()
2058 if (rx->rx_mclk_users <= 0) { in rx_macro_mclk_enable()
2060 rx->rx_mclk_users = 0; in rx_macro_mclk_enable()
2064 if (rx->rx_mclk_users == 0) { in rx_macro_mclk_enable()
2066 CDC_RX_FS_MCLK_CNT_EN_MASK, 0x0); in rx_macro_mclk_enable()
2072 CDC_RX_CLK_MCLK2_EN_MASK, 0x0); in rx_macro_mclk_enable()
2082 int ret = 0; in rx_macro_mclk_event()
2165 return 0; in rx_macro_enable_main_path()
2176 return 0; in rx_macro_config_compander()
2178 pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F; in rx_macro_config_compander()
2179 if (pcm_rate < 0x06) in rx_macro_config_compander()
2180 val = 0x03; in rx_macro_config_compander()
2181 else if (pcm_rate < 0x08) in rx_macro_config_compander()
2182 val = 0x01; in rx_macro_config_compander()
2183 else if (pcm_rate < 0x0B) in rx_macro_config_compander()
2184 val = 0x02; in rx_macro_config_compander()
2186 val = 0x00; in rx_macro_config_compander()
2194 CDC_RX_DC_COEFF_SEL_MASK, 0x3); in rx_macro_config_compander()
2196 return 0; in rx_macro_config_compander()
2201 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x1); in rx_macro_config_compander()
2203 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1); in rx_macro_config_compander()
2205 CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0); in rx_macro_config_compander()
2207 CDC_RX_RXn_COMP_EN_MASK, 0x1); in rx_macro_config_compander()
2212 CDC_RX_COMPANDERn_HALT_MASK, 0x1); in rx_macro_config_compander()
2214 CDC_RX_RXn_COMP_EN_MASK, 0x0); in rx_macro_config_compander()
2216 CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0); in rx_macro_config_compander()
2218 CDC_RX_COMPANDERn_HALT_MASK, 0x0); in rx_macro_config_compander()
2221 return 0; in rx_macro_config_compander()
2234 return 0; in rx_macro_load_compander_coeff()
2237 return 0; in rx_macro_load_compander_coeff()
2247 return 0; in rx_macro_load_compander_coeff()
2254 for (i = 0; i < COMP_MAX_COEFF; i++) { in rx_macro_load_compander_coeff()
2262 return 0; in rx_macro_load_compander_coeff()
2269 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2275 if (rx->softclip_clk_users == 0) in rx_macro_enable_softclip_clk()
2277 CDC_RX_SOFTCLIP_CLK_EN_MASK, 0); in rx_macro_enable_softclip_clk()
2286 return 0; in rx_macro_config_softclip()
2293 CDC_RX_SOFTCLIP_EN_MASK, 0x01); in rx_macro_config_softclip()
2298 CDC_RX_SOFTCLIP_EN_MASK, 0x0); in rx_macro_config_softclip()
2302 return 0; in rx_macro_config_softclip()
2312 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00); in rx_macro_config_aux_hpf()
2318 CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04); in rx_macro_config_aux_hpf()
2321 return 0; in rx_macro_config_aux_hpf()
2326 if ((enable && ++rx->clsh_users == 1) || (!enable && --rx->clsh_users == 0)) in rx_macro_enable_clsh_block()
2329 if (rx->clsh_users < 0) in rx_macro_enable_clsh_block()
2330 rx->clsh_users = 0; in rx_macro_enable_clsh_block()
2339 return 0; in rx_macro_config_classh()
2343 return 0; in rx_macro_config_classh()
2352 snd_soc_component_write(component, CDC_RX_CLSH_K1_LSB, 0xc0); in rx_macro_config_classh()
2354 CDC_RX_CLSH_K1_MSB_COEFF_MASK, 0); in rx_macro_config_classh()
2361 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); in rx_macro_config_classh()
2365 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); in rx_macro_config_classh()
2368 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); in rx_macro_config_classh()
2370 CDC_RX_RXn_RX_PATH_CFG0(rx, 0), in rx_macro_config_classh()
2371 CDC_RX_RXn_CLSH_EN_MASK, 0x1); in rx_macro_config_classh()
2377 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x39); in rx_macro_config_classh()
2381 CDC_RX_CLSH_HPH_V_PA_MIN_MASK, 0x1c); in rx_macro_config_classh()
2384 CDC_RX_CLSH_DECAY_RATE_MASK, 0x0); in rx_macro_config_classh()
2387 CDC_RX_RXn_CLSH_EN_MASK, 0x1); in rx_macro_config_classh()
2399 return 0; in rx_macro_config_classh()
2410 hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0); in rx_macro_hd2_control()
2411 hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0); in rx_macro_hd2_control()
2421 CDC_RX_RXn_HD2_ALPHA_MASK, 0x14); in rx_macro_hd2_control()
2428 CDC_RX_RXn_HD2_EN_MASK, 0); in rx_macro_hd2_control()
2430 CDC_RX_RXn_HD2_ALPHA_MASK, 0x0); in rx_macro_hd2_control()
2442 ucontrol->value.integer.value[0] = rx->comp_enabled[comp]; in rx_macro_get_compander()
2443 return 0; in rx_macro_get_compander()
2451 int value = ucontrol->value.integer.value[0]; in rx_macro_set_compander()
2456 return 0; in rx_macro_set_compander()
2466 ucontrol->value.enumerated.item[0] = in rx_macro_mux_get()
2468 return 0; in rx_macro_mux_get()
2478 u32 rx_port_value = ucontrol->value.enumerated.item[0]; in rx_macro_mux_put()
2485 if (aif_rst == 0) in rx_macro_mux_put()
2486 return 0; in rx_macro_mux_put()
2489 return 0; in rx_macro_mux_put()
2495 case 0: in rx_macro_mux_put()
2498 * active_ch_cnt == 0 was tested in if() above. in rx_macro_mux_put()
2524 return 0; in rx_macro_mux_put()
2554 ucontrol->value.integer.value[0] = rx->is_ear_mode_on; in rx_macro_get_ear_mode()
2555 return 0; in rx_macro_get_ear_mode()
2564 rx->is_ear_mode_on = (!ucontrol->value.integer.value[0] ? false : true); in rx_macro_put_ear_mode()
2565 return 0; in rx_macro_put_ear_mode()
2574 ucontrol->value.integer.value[0] = rx->hph_hd2_mode; in rx_macro_get_hph_hd2_mode()
2575 return 0; in rx_macro_get_hph_hd2_mode()
2584 rx->hph_hd2_mode = ucontrol->value.integer.value[0]; in rx_macro_put_hph_hd2_mode()
2585 return 0; in rx_macro_put_hph_hd2_mode()
2594 ucontrol->value.enumerated.item[0] = rx->hph_pwr_mode; in rx_macro_get_hph_pwr_mode()
2595 return 0; in rx_macro_get_hph_pwr_mode()
2604 rx->hph_pwr_mode = ucontrol->value.enumerated.item[0]; in rx_macro_put_hph_pwr_mode()
2605 return 0; in rx_macro_put_hph_pwr_mode()
2614 ucontrol->value.integer.value[0] = rx->is_softclip_on; in rx_macro_soft_clip_enable_get()
2616 return 0; in rx_macro_soft_clip_enable_get()
2625 rx->is_softclip_on = ucontrol->value.integer.value[0]; in rx_macro_soft_clip_enable_put()
2627 return 0; in rx_macro_soft_clip_enable_put()
2636 ucontrol->value.integer.value[0] = rx->is_aux_hpf_on; in rx_macro_aux_hpf_mode_get()
2638 return 0; in rx_macro_aux_hpf_mode_get()
2647 rx->is_aux_hpf_on = ucontrol->value.integer.value[0]; in rx_macro_aux_hpf_mode_put()
2649 return 0; in rx_macro_aux_hpf_mode_put()
2676 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), in rx_macro_hphdelay_lutbypass()
2677 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1); in rx_macro_hphdelay_lutbypass()
2688 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x0); in rx_macro_hphdelay_lutbypass()
2693 CDC_RX_RXn_RX_PATH_CFG1(rx, 0), in rx_macro_hphdelay_lutbypass()
2694 CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0); in rx_macro_hphdelay_lutbypass()
2696 CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0); in rx_macro_hphdelay_lutbypass()
2698 CDC_RX_COMPANDER1_HPH_LOW_PWR_MODE_MASK, 0x1); in rx_macro_hphdelay_lutbypass()
2701 return 0; in rx_macro_hphdelay_lutbypass()
2715 if (rx->main_clk_users[interp_idx] == 0) { in rx_macro_enable_interp_clk()
2718 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); in rx_macro_enable_interp_clk()
2720 CDC_RX_RXn_DSM_CLK_EN_MASK, 0x1); in rx_macro_enable_interp_clk()
2722 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x03); in rx_macro_enable_interp_clk()
2739 if (rx->main_clk_users[interp_idx] <= 0) { in rx_macro_enable_interp_clk()
2740 rx->main_clk_users[interp_idx] = 0; in rx_macro_enable_interp_clk()
2743 CDC_RX_PATH_PGA_MUTE_MASK, 0x1); in rx_macro_enable_interp_clk()
2746 CDC_RX_RXn_DSM_CLK_EN_MASK, 0); in rx_macro_enable_interp_clk()
2748 CDC_RX_PATH_CLK_EN_MASK, 0); in rx_macro_enable_interp_clk()
2753 CDC_RX_PATH_RESET_EN_MASK, 0); in rx_macro_enable_interp_clk()
2757 0x04); in rx_macro_enable_interp_clk()
2759 CDC_RX_RXn_HPF_CUT_FREQ_MASK, 0x00); in rx_macro_enable_interp_clk()
2796 CDC_RX_RXn_MIX_CLK_EN_MASK, 0x00); in rx_macro_enable_mix_path()
2803 CDC_RX_RXn_MIX_RESET_MASK, 0x00); in rx_macro_enable_mix_path()
2807 return 0; in rx_macro_enable_mix_path()
2826 CDC_RX_RXn_SIDETONE_EN_MASK, 0); in rx_macro_enable_rx_path_clk()
2832 return 0; in rx_macro_enable_rx_path_clk()
2880 return 0; in rx_macro_set_iir_gain()
2890 reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; in get_iir_band_coeff()
2891 b2_reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; in get_iir_band_coeff()
2895 sizeof(uint32_t)) & 0x7F); in get_iir_band_coeff()
2900 * sizeof(uint32_t) + 1) & 0x7F); in get_iir_band_coeff()
2905 * sizeof(uint32_t) + 2) & 0x7F); in get_iir_band_coeff()
2910 * sizeof(uint32_t) + 3) & 0x7F); in get_iir_band_coeff()
2920 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B2_CTL + 0x80 * iir_idx; in set_iir_band_coeff()
2922 snd_soc_component_write(component, reg, (value & 0xFF)); in set_iir_band_coeff()
2923 snd_soc_component_write(component, reg, (value >> 8) & 0xFF); in set_iir_band_coeff()
2924 snd_soc_component_write(component, reg, (value >> 16) & 0xFF); in set_iir_band_coeff()
2926 snd_soc_component_write(component, reg, (value >> 24) & 0x3F); in set_iir_band_coeff()
2941 int reg = CDC_RX_SIDETONE_IIR0_IIR_COEF_B1_CTL + 0x80 * iir_idx; in rx_macro_put_iir_band_audio_mixer()
2943 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max); in rx_macro_put_iir_band_audio_mixer()
2948 sizeof(uint32_t)) & 0x7F); in rx_macro_put_iir_band_audio_mixer()
2950 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]); in rx_macro_put_iir_band_audio_mixer()
2956 return 0; in rx_macro_put_iir_band_audio_mixer()
2971 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0); in rx_macro_get_iir_band_audio_mixer()
2977 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max); in rx_macro_get_iir_band_audio_mixer()
2979 return 0; in rx_macro_get_iir_band_audio_mixer()
2992 return 0; in rx_macro_iir_filter_info()
3023 SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
3025 SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
3028 SOC_SINGLE_EXT("RX_EAR Mode Switch", SND_SOC_NOPM, 0, 1, 0,
3031 SOC_SINGLE_EXT("RX_HPH HD2 Mode Switch", SND_SOC_NOPM, 0, 1, 0,
3037 SOC_SINGLE_EXT("RX_Softclip Switch", SND_SOC_NOPM, 0, 1, 0,
3040 SOC_SINGLE_EXT("AUX_HPF Switch", SND_SOC_NOPM, 0, 1, 0,
3070 0, 1, 0),
3072 1, 1, 0),
3074 2, 1, 0),
3076 3, 1, 0),
3078 4, 1, 0),
3080 0, 1, 0),
3082 1, 1, 0),
3084 2, 1, 0),
3086 3, 1, 0),
3088 4, 1, 0),
3115 ec_tx = ((val & 0xf0) >> 0x4) - 1; in rx_macro_enable_echo()
3117 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3122 ec_tx = (val & 0x0f) - 1; in rx_macro_enable_echo()
3124 if (ec_tx < 0 || (ec_tx >= RX_MACRO_EC_MUX_MAX)) { in rx_macro_enable_echo()
3130 0x40 * ec_tx; in rx_macro_enable_echo()
3131 snd_soc_component_update_bits(component, ec_hq_reg, 0x01, 0x01); in rx_macro_enable_echo()
3133 0x40 * ec_tx; in rx_macro_enable_echo()
3135 snd_soc_component_update_bits(component, ec_hq_reg, 0x1E, 0x08); in rx_macro_enable_echo()
3137 return 0; in rx_macro_enable_echo()
3141 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3146 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
3151 SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
3152 SND_SOC_NOPM, 0, 0),
3154 SND_SOC_DAPM_AIF_IN("RX AIF2 PB", "RX_MACRO_AIF2 Playback", 0,
3155 SND_SOC_NOPM, 0, 0),
3157 SND_SOC_DAPM_AIF_IN("RX AIF3 PB", "RX_MACRO_AIF3 Playback", 0,
3158 SND_SOC_NOPM, 0, 0),
3160 SND_SOC_DAPM_AIF_IN("RX AIF4 PB", "RX_MACRO_AIF4 Playback", 0,
3161 SND_SOC_NOPM, 0, 0),
3163 SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
3164 SND_SOC_NOPM, 0, 0),
3166 SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
3168 SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
3170 SND_SOC_DAPM_MUX("RX_MACRO RX2 MUX", SND_SOC_NOPM, RX_MACRO_RX2, 0,
3172 SND_SOC_DAPM_MUX("RX_MACRO RX3 MUX", SND_SOC_NOPM, RX_MACRO_RX3, 0,
3174 SND_SOC_DAPM_MUX("RX_MACRO RX4 MUX", SND_SOC_NOPM, RX_MACRO_RX4, 0,
3176 SND_SOC_DAPM_MUX("RX_MACRO RX5 MUX", SND_SOC_NOPM, RX_MACRO_RX5, 0,
3179 SND_SOC_DAPM_MIXER("RX_RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
3180 SND_SOC_DAPM_MIXER("RX_RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3181 SND_SOC_DAPM_MIXER("RX_RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3182 SND_SOC_DAPM_MIXER("RX_RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
3183 SND_SOC_DAPM_MIXER("RX_RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
3184 SND_SOC_DAPM_MIXER("RX_RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
3186 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
3187 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
3188 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
3189 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
3190 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
3191 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
3192 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
3193 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
3196 RX_MACRO_EC0_MUX, 0,
3200 RX_MACRO_EC1_MUX, 0,
3204 RX_MACRO_EC2_MUX, 0,
3209 4, 0, NULL, 0, rx_macro_set_iir_gain,
3212 4, 0, NULL, 0, rx_macro_set_iir_gain,
3215 4, 0, NULL, 0),
3217 4, 0, NULL, 0),
3219 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
3222 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
3226 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
3230 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_AUX, 0,
3235 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp0_mux),
3236 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp1_mux),
3237 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int0_1_mix_inp2_mux),
3238 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp0_mux),
3239 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp1_mux),
3240 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int1_1_mix_inp2_mux),
3241 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp0_mux),
3242 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp1_mux),
3243 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0, &rx_int2_1_mix_inp2_mux),
3245 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
3249 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
3253 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_AUX, 0,
3258 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
3260 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
3262 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
3265 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3266 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3267 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3268 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3269 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
3270 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3273 0, &rx_int0_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3276 0, &rx_int1_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3279 0, &rx_int2_mix2_inp_mux, rx_macro_enable_rx_path_clk,
3282 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3283 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3284 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
3295 SND_SOC_DAPM_SUPPLY_S("RX_MCLK", 0, SND_SOC_NOPM, 0, 0,
3624 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0), in rx_macro_component_probe()
3633 snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0), in rx_macro_component_probe()
3692 return 0; in swclk_gate_enable()
3700 CDC_RX_SWR_CLK_EN_MASK, 0); in swclk_gate_disable()
3712 ret = val & BIT(0); in swclk_gate_is_enabled()
3747 init.flags = 0; in rx_macro_register_mclk_output()
3814 base = devm_platform_ioremap_resource(pdev, 0); in rx_macro_probe()
3827 rx->rxn_reg_stride = 0x80; in rx_macro_probe()
3828 rx->rxn_reg_stride2 = 0xc; in rx_macro_probe()
3833 memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults)); in rx_macro_probe()
3841 rx->rxn_reg_stride = 0xc0; in rx_macro_probe()
3842 rx->rxn_reg_stride2 = 0x0; in rx_macro_probe()
3847 memcpy(®_defaults[0], rx_defaults, sizeof(rx_defaults)); in rx_macro_probe()
3906 CDC_RX_SWR_RESET_MASK, 0); in rx_macro_probe()
3925 return 0; in rx_macro_probe()
3984 return 0; in rx_macro_runtime_suspend()
4012 return 0; in rx_macro_runtime_resume()