1 // SPDX-License-Identifier: GPL-2.0-only
3  * es8328.c  --  ES8328 ALSA SoC Audio driver
5  * Copyright 2014 Sutajio Ko-Usagi PTE LTD
10 #include <linux/clk.h>
80 	struct clk *clk;  member
99 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
100 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
101 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
123 	if (es8328->deemph) {  in es8328_set_deemph()
126 			if (abs(deemph_settings[i].rate - es8328->playback_fs) <  in es8328_set_deemph()
127 			    abs(deemph_settings[best].rate - es8328->playback_fs))  in es8328_set_deemph()
136 	dev_dbg(component->dev, "Set deemphasis %d\n", val);  in es8328_set_deemph()
148 	ucontrol->value.integer.value[0] = es8328->deemph;  in es8328_get_deemph()
157 	unsigned int deemph = ucontrol->value.integer.value[0];  in es8328_put_deemph()
161 		return -EINVAL;  in es8328_put_deemph()
163 	if (es8328->deemph == deemph)  in es8328_put_deemph()
170 	es8328->deemph = deemph;  in es8328_put_deemph()
276 /* Mono ADC Mux */
287 	SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
289 	SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
304 	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8328_ADCPOWER,
306 	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
316 	SND_SOC_DAPM_SUPPLY("ADC STM", ES8328_CHIPPOWER,
321 	SND_SOC_DAPM_SUPPLY("ADC DIG", ES8328_CHIPPOWER,
326 	SND_SOC_DAPM_SUPPLY("ADC DLL", ES8328_CHIPPOWER,
329 	SND_SOC_DAPM_SUPPLY("ADC Vref", ES8328_CHIPPOWER,
391 	{ "Left ADC Mux", "Stereo", "Left PGA Mux" },
392 	{ "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
393 	{ "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
395 	{ "Right ADC Mux", "Stereo", "Right PGA Mux" },
396 	{ "Right ADC Mux", "Mono (Right)", "Right PGA Mux" },
397 	{ "Right ADC Mux", "Digital Mono", "Right PGA Mux" },
399 	{ "Left ADC", NULL, "Left ADC Mux" },
400 	{ "Right ADC", NULL, "Right ADC Mux" },
402 	{ "ADC DIG", NULL, "ADC STM" },
403 	{ "ADC DIG", NULL, "ADC Vref" },
404 	{ "ADC DIG", NULL, "ADC DLL" },
406 	{ "Left ADC", NULL, "ADC DIG" },
407 	{ "Right ADC", NULL, "ADC DIG" },
456 	return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3,  in es8328_mute()
464 	struct snd_soc_component *component = dai->component;  in es8328_startup()
467 	if (es8328->provider && es8328->sysclk_constraints)  in es8328_startup()
468 		snd_pcm_hw_constraint_list(substream->runtime, 0,  in es8328_startup()
470 				es8328->sysclk_constraints);  in es8328_startup()
479 	struct snd_soc_component *component = dai->component;  in es8328_hw_params()
486 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)  in es8328_hw_params()
491 	if (es8328->provider) {  in es8328_hw_params()
492 		if (!es8328->sysclk_constraints) {  in es8328_hw_params()
493 			dev_err(component->dev, "No MCLK configured\n");  in es8328_hw_params()
494 			return -EINVAL;  in es8328_hw_params()
497 		for (i = 0; i < es8328->sysclk_constraints->count; i++)  in es8328_hw_params()
498 			if (es8328->sysclk_constraints->list[i] ==  in es8328_hw_params()
502 		if (i == es8328->sysclk_constraints->count) {  in es8328_hw_params()
503 			dev_err(component->dev,  in es8328_hw_params()
506 			return -EINVAL;  in es8328_hw_params()
508 		ratio = es8328->mclk_ratios[i];  in es8328_hw_params()
511 		es8328->mclkdiv2 = 0;  in es8328_hw_params()
516 			es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0);  in es8328_hw_params()
535 		return -EINVAL;  in es8328_hw_params()
538 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {  in es8328_hw_params()
543 		es8328->playback_fs = params_rate(params);  in es8328_hw_params()
556 	struct snd_soc_component *component = codec_dai->component;  in es8328_set_sysclk()
569 		es8328->sysclk_constraints = NULL;  in es8328_set_sysclk()
570 		es8328->mclk_ratios = NULL;  in es8328_set_sysclk()
576 		es8328->sysclk_constraints = &constraints_11289;  in es8328_set_sysclk()
577 		es8328->mclk_ratios = ratios_11289;  in es8328_set_sysclk()
583 		es8328->sysclk_constraints = &constraints_12288;  in es8328_set_sysclk()
584 		es8328->mclk_ratios = ratios_12288;  in es8328_set_sysclk()
587 		return -EINVAL;  in es8328_set_sysclk()
590 	es8328->mclkdiv2 = mclkdiv2;  in es8328_set_sysclk()
597 	struct snd_soc_component *component = codec_dai->component;  in es8328_set_dai_fmt()
608 		es8328->provider = true;  in es8328_set_dai_fmt()
614 		es8328->provider = false;  in es8328_set_dai_fmt()
617 		return -EINVAL;  in es8328_set_dai_fmt()
635 		return -EINVAL;  in es8328_set_dai_fmt()
640 		return -EINVAL;  in es8328_set_dai_fmt()
711 	.name = "es8328-hifi-analog",
737 	clk_disable_unprepare(es8328->clk);  in es8328_suspend()
739 	ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),  in es8328_suspend()
740 			es8328->supplies);  in es8328_suspend()
742 		dev_err(component->dev, "unable to disable regulators\n");  in es8328_suspend()
750 	struct regmap *regmap = dev_get_regmap(component->dev, NULL);  in es8328_resume()
756 	ret = clk_prepare_enable(es8328->clk);  in es8328_resume()
758 		dev_err(component->dev, "unable to enable clock\n");  in es8328_resume()
762 	ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),  in es8328_resume()
763 					es8328->supplies);  in es8328_resume()
765 		dev_err(component->dev, "unable to enable regulators\n");  in es8328_resume()
772 		dev_err(component->dev, "unable to sync regcache\n");  in es8328_resume()
786 	ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies),  in es8328_component_probe()
787 					es8328->supplies);  in es8328_component_probe()
789 		dev_err(component->dev, "unable to enable regulators\n");  in es8328_component_probe()
794 	es8328->clk = devm_clk_get(component->dev, NULL);  in es8328_component_probe()
795 	if (IS_ERR(es8328->clk)) {  in es8328_component_probe()
796 		dev_err(component->dev, "codec clock missing or invalid\n");  in es8328_component_probe()
797 		ret = PTR_ERR(es8328->clk);  in es8328_component_probe()
801 	ret = clk_prepare_enable(es8328->clk);  in es8328_component_probe()
803 		dev_err(component->dev, "unable to prepare codec clk\n");  in es8328_component_probe()
810 	regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),  in es8328_component_probe()
811 			       es8328->supplies);  in es8328_component_probe()
821 	clk_disable_unprepare(es8328->clk);  in es8328_remove()
823 	regulator_bulk_disable(ARRAY_SIZE(es8328->supplies),  in es8328_remove()
824 			       es8328->supplies);  in es8328_remove()
866 		return -ENOMEM;  in es8328_probe()
868 	es8328->regmap = regmap;  in es8328_probe()
870 	for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++)  in es8328_probe()
871 		es8328->supplies[i].supply = supply_names[i];  in es8328_probe()
873 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies),  in es8328_probe()
874 				es8328->supplies);  in es8328_probe()