Lines Matching +full:left +full:-
1 // SPDX-License-Identifier: GPL-2.0-only
3 * es8328.c -- ES8328 ALSA SoC Audio driver
5 * Copyright 2014 Sutajio Ko-Usagi PTE LTD
99 static const DECLARE_TLV_DB_SCALE(play_tlv, -3000, 100, 0);
100 static const DECLARE_TLV_DB_SCALE(dac_adc_tlv, -9600, 50, 0);
101 static const DECLARE_TLV_DB_SCALE(bypass_tlv, -1500, 300, 0);
123 if (es8328->deemph) { in es8328_set_deemph()
126 if (abs(deemph_settings[i].rate - es8328->playback_fs) < in es8328_set_deemph()
127 abs(deemph_settings[best].rate - es8328->playback_fs)) in es8328_set_deemph()
136 dev_dbg(component->dev, "Set deemphasis %d\n", val); in es8328_set_deemph()
148 ucontrol->value.integer.value[0] = es8328->deemph; in es8328_get_deemph()
157 unsigned int deemph = ucontrol->value.integer.value[0]; in es8328_put_deemph()
161 return -EINVAL; in es8328_put_deemph()
163 if (es8328->deemph == deemph) in es8328_put_deemph()
170 es8328->deemph = deemph; in es8328_put_deemph()
188 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume",
190 SOC_SINGLE_TLV("Left Mixer Right Bypass Volume",
192 SOC_SINGLE_TLV("Right Mixer Left Bypass Volume",
234 /* Left Mixer */
236 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL17, 6, 1, 0),
243 SOC_DAPM_SINGLE("Left Playback Switch", ES8328_DACCONTROL19, 7, 1, 0),
244 SOC_DAPM_SINGLE("Left Bypass Switch", ES8328_DACCONTROL19, 6, 1, 0),
251 /* Left PGA Mux */
275 static const char * const es8328_mono_mux[] = {"Stereo", "Mono (Left)",
285 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
290 SND_SOC_DAPM_MUX("Left PGA Mux", ES8328_ADCPOWER,
297 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
304 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8328_ADCPOWER,
334 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8328_DACPOWER,
337 SND_SOC_DAPM_MIXER("Left Mixer", ES8328_DACCONTROL17, 7, 0,
346 SND_SOC_DAPM_PGA("Left Out 2", ES8328_DACPOWER,
350 SND_SOC_DAPM_PGA("Left Out 1", ES8328_DACPOWER,
366 { "Left Line Mux", "Line 1", "LINPUT1" },
367 { "Left Line Mux", "Line 2", "LINPUT2" },
368 { "Left Line Mux", "PGA", "Left PGA Mux" },
369 { "Left Line Mux", "Differential", "Differential Mux" },
376 { "Left PGA Mux", "Line 1", "LINPUT1" },
377 { "Left PGA Mux", "Line 2", "LINPUT2" },
378 { "Left PGA Mux", "Differential", "Differential Mux" },
389 { "Left ADC Mux", "Stereo", "Left PGA Mux" },
390 { "Left ADC Mux", "Mono (Left)", "Left PGA Mux" },
391 { "Left ADC Mux", "Digital Mono", "Left PGA Mux" },
397 { "Left ADC", NULL, "Left ADC Mux" },
404 { "Left ADC", NULL, "ADC DIG" },
409 { "Left Line Mux", "Line 1", "LINPUT1" },
410 { "Left Line Mux", "Line 2", "LINPUT2" },
411 { "Left Line Mux", "PGA", "Left PGA Mux" },
412 { "Left Line Mux", "Differential", "Differential Mux" },
419 { "Left Mixer", NULL, "Left DAC" },
420 { "Left Mixer", "Left Bypass Switch", "Left Line Mux" },
421 { "Left Mixer", "Right Playback Switch", "Right DAC" },
422 { "Left Mixer", "Right Bypass Switch", "Right Line Mux" },
424 { "Right Mixer", "Left Playback Switch", "Left DAC" },
425 { "Right Mixer", "Left Bypass Switch", "Left Line Mux" },
433 { "Left DAC", NULL, "DAC DIG" },
436 { "Left Out 1", NULL, "Left Mixer" },
437 { "LOUT1", NULL, "Left Out 1" },
441 { "Left Out 2", NULL, "Left Mixer" },
442 { "LOUT2", NULL, "Left Out 2" },
449 return snd_soc_component_update_bits(dai->component, ES8328_DACCONTROL3, in es8328_mute()
457 struct snd_soc_component *component = dai->component; in es8328_startup()
460 if (es8328->provider && es8328->sysclk_constraints) in es8328_startup()
461 snd_pcm_hw_constraint_list(substream->runtime, 0, in es8328_startup()
463 es8328->sysclk_constraints); in es8328_startup()
472 struct snd_soc_component *component = dai->component; in es8328_hw_params()
479 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) in es8328_hw_params()
484 if (es8328->provider) { in es8328_hw_params()
485 if (!es8328->sysclk_constraints) { in es8328_hw_params()
486 dev_err(component->dev, "No MCLK configured\n"); in es8328_hw_params()
487 return -EINVAL; in es8328_hw_params()
490 for (i = 0; i < es8328->sysclk_constraints->count; i++) in es8328_hw_params()
491 if (es8328->sysclk_constraints->list[i] == in es8328_hw_params()
495 if (i == es8328->sysclk_constraints->count) { in es8328_hw_params()
496 dev_err(component->dev, in es8328_hw_params()
499 return -EINVAL; in es8328_hw_params()
501 ratio = es8328->mclk_ratios[i]; in es8328_hw_params()
504 es8328->mclkdiv2 = 0; in es8328_hw_params()
509 es8328->mclkdiv2 ? ES8328_MASTERMODE_MCLKDIV2 : 0); in es8328_hw_params()
528 return -EINVAL; in es8328_hw_params()
531 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { in es8328_hw_params()
536 es8328->playback_fs = params_rate(params); in es8328_hw_params()
549 struct snd_soc_component *component = codec_dai->component; in es8328_set_sysclk()
562 es8328->sysclk_constraints = NULL; in es8328_set_sysclk()
563 es8328->mclk_ratios = NULL; in es8328_set_sysclk()
569 es8328->sysclk_constraints = &constraints_11289; in es8328_set_sysclk()
570 es8328->mclk_ratios = ratios_11289; in es8328_set_sysclk()
576 es8328->sysclk_constraints = &constraints_12288; in es8328_set_sysclk()
577 es8328->mclk_ratios = ratios_12288; in es8328_set_sysclk()
580 return -EINVAL; in es8328_set_sysclk()
583 es8328->mclkdiv2 = mclkdiv2; in es8328_set_sysclk()
590 struct snd_soc_component *component = codec_dai->component; in es8328_set_dai_fmt()
601 es8328->provider = true; in es8328_set_dai_fmt()
607 es8328->provider = false; in es8328_set_dai_fmt()
610 return -EINVAL; in es8328_set_dai_fmt()
628 return -EINVAL; in es8328_set_dai_fmt()
633 return -EINVAL; in es8328_set_dai_fmt()
704 .name = "es8328-hifi-analog",
730 clk_disable_unprepare(es8328->clk); in es8328_suspend()
732 ret = regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_suspend()
733 es8328->supplies); in es8328_suspend()
735 dev_err(component->dev, "unable to disable regulators\n"); in es8328_suspend()
743 struct regmap *regmap = dev_get_regmap(component->dev, NULL); in es8328_resume()
749 ret = clk_prepare_enable(es8328->clk); in es8328_resume()
751 dev_err(component->dev, "unable to enable clock\n"); in es8328_resume()
755 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_resume()
756 es8328->supplies); in es8328_resume()
758 dev_err(component->dev, "unable to enable regulators\n"); in es8328_resume()
765 dev_err(component->dev, "unable to sync regcache\n"); in es8328_resume()
779 ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
780 es8328->supplies); in es8328_component_probe()
782 dev_err(component->dev, "unable to enable regulators\n"); in es8328_component_probe()
787 es8328->clk = devm_clk_get(component->dev, NULL); in es8328_component_probe()
788 if (IS_ERR(es8328->clk)) { in es8328_component_probe()
789 dev_err(component->dev, "codec clock missing or invalid\n"); in es8328_component_probe()
790 ret = PTR_ERR(es8328->clk); in es8328_component_probe()
794 ret = clk_prepare_enable(es8328->clk); in es8328_component_probe()
796 dev_err(component->dev, "unable to prepare codec clk\n"); in es8328_component_probe()
803 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_component_probe()
804 es8328->supplies); in es8328_component_probe()
814 clk_disable_unprepare(es8328->clk); in es8328_remove()
816 regulator_bulk_disable(ARRAY_SIZE(es8328->supplies), in es8328_remove()
817 es8328->supplies); in es8328_remove()
859 return -ENOMEM; in es8328_probe()
861 es8328->regmap = regmap; in es8328_probe()
863 for (i = 0; i < ARRAY_SIZE(es8328->supplies); i++) in es8328_probe()
864 es8328->supplies[i].supply = supply_names[i]; in es8328_probe()
866 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(es8328->supplies), in es8328_probe()
867 es8328->supplies); in es8328_probe()