1 // SPDX-License-Identifier: GPL-2.0-or-later
58 /* Input - Gain, Select and Filter Registers */
71 /* Output - Gain, Select and Filter Registers */
244 	u8 mode;	/* 0 = slave, 1 = master */
247 /* PLL divisor table */
249 	/* for MASTER mode, fs = 44.1Khz and its harmonics */
259 	/* for MASTER mode, fs = 48Khz and its harmonics */
288 	0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
289 	/* -54dB to 15dB */
290 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
295 	/* -78dB to 12dB */
296 	0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
305 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
306 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
307 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
308 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
309 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
310 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
483 	if (ucontrol->value.integer.value[0]) {  in da9055_put_alc_sw()
518 		offset_l = -avg_left_data;  in da9055_put_alc_sw()
519 		offset_r = -avg_right_data;  in da9055_put_alc_sw()
939 	int master;  member
1050 	struct snd_soc_component *component = dai->component;  in da9055_hw_params()
1069 		return -EINVAL;  in da9055_hw_params()
1118 		return -EINVAL;  in da9055_hw_params()
1121 	if (da9055->mclk_rate) {  in da9055_hw_params()
1122 		/* PLL Mode, Write actual FS */  in da9055_hw_params()
1126 		 * Non-PLL Mode  in da9055_hw_params()
1127 		 * When PLL is bypassed, chip assumes constant MCLK of  in da9055_hw_params()
1135 	if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) {  in da9055_hw_params()
1136 		/* PLL Mode */  in da9055_hw_params()
1137 		if (!da9055->master) {  in da9055_hw_params()
1138 			/* PLL slave mode, enable PLL and also SRM */  in da9055_hw_params()
1143 			/* PLL master mode, only enable PLL */  in da9055_hw_params()
1148 		/* Non PLL Mode, disable PLL */  in da9055_hw_params()
1158 	struct snd_soc_component *component = codec_dai->component;  in da9055_set_dai_fmt()
1164 		/* DA9055 in I2S Master Mode */  in da9055_set_dai_fmt()
1174 		return -EINVAL;  in da9055_set_dai_fmt()
1177 	/* Don't allow change of mode if PLL is enabled */  in da9055_set_dai_fmt()
1179 	    (da9055->master != mode))  in da9055_set_dai_fmt()
1180 		return -EINVAL;  in da9055_set_dai_fmt()
1182 	da9055->master = mode;  in da9055_set_dai_fmt()
1199 		return -EINVAL;  in da9055_set_dai_fmt()
1215 	struct snd_soc_component *component = dai->component;  in da9055_mute()
1238 	struct snd_soc_component *component = codec_dai->component;  in da9055_set_dai_sysclk()
1253 			da9055->mclk_rate = freq;  in da9055_set_dai_sysclk()
1256 			dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",  in da9055_set_dai_sysclk()
1258 			return -EINVAL;  in da9055_set_dai_sysclk()
1262 		dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);  in da9055_set_dai_sysclk()
1263 		return -EINVAL;  in da9055_set_dai_sysclk()
1268  * da9055_set_dai_pll	: Configure the codec PLL
1270  * @param pll_id	: da9055 has only one pll, so pll_id is always zero
1275  * Note: Supported PLL input frequencies are 11.2896MHz, 12MHz, 12.288MHz,
1281 	struct snd_soc_component *component = codec_dai->component;  in da9055_set_dai_pll()
1286 	/* Disable PLL before setting the divisors */  in da9055_set_dai_pll()
1290 	if (!da9055->master && (fout != 2822400))  in da9055_set_dai_pll()
1293 	/* Search pll div array for correct divisors */  in da9055_set_dai_pll()
1297 		    (da9055->master ==  da9055_pll_div[cnt].mode) &&  in da9055_set_dai_pll()
1309 	/* Write PLL dividers */  in da9055_set_dai_pll()
1316 	dev_err(codec_dai->dev, "Error in setting up PLL\n");  in da9055_set_dai_pll()
1317 	return -EINVAL;  in da9055_set_dai_pll()
1331 	.name = "da9055-hifi",
1361 			/* Enable VMID reference & master bias */  in da9055_set_bias_level()
1368 		/* Disable VMID reference & master bias */  in da9055_set_bias_level()
1425 	if (da9055->pdata) {  in da9055_probe()
1427 		if (da9055->pdata->micbias_source) {  in da9055_probe()
1436 		switch (da9055->pdata->micbias) {  in da9055_probe()
1443 					    (da9055->pdata->micbias) << 4);  in da9055_probe()
1477 	struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev);  in da9055_i2c_probe()
1480 	da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv),  in da9055_i2c_probe()
1483 		return -ENOMEM;  in da9055_i2c_probe()
1486 		da9055->pdata = pdata;  in da9055_i2c_probe()
1490 	da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config);  in da9055_i2c_probe()
1491 	if (IS_ERR(da9055->regmap)) {  in da9055_i2c_probe()
1492 		ret = PTR_ERR(da9055->regmap);  in da9055_i2c_probe()
1493 		dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);  in da9055_i2c_probe()
1497 	ret = devm_snd_soc_register_component(&i2c->dev,  in da9055_i2c_probe()
1500 		dev_err(&i2c->dev, "Failed to register da9055 component: %d\n",  in da9055_i2c_probe()
1514 	{ "da9055-codec" },
1521 	{ .compatible = "dlg,da9055-codec", },
1530 		.name = "da9055-codec",