Lines Matching +full:alc +full:- +full:enable
1 // SPDX-License-Identifier: GPL-2.0-or-later
58 /* Input - Gain, Select and Filter Registers */
71 /* Output - Gain, Select and Filter Registers */
288 0x0, 0x10, TLV_DB_SCALE_ITEM(-5400, 0, 0),
289 /* -54dB to 15dB */
290 0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
295 /* -78dB to 12dB */
296 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
305 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
306 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
307 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
308 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -5700, 100, 0);
309 static const DECLARE_TLV_DB_SCALE(lineout_vol_tlv, -4800, 100, 0);
310 static const DECLARE_TLV_DB_SCALE(alc_threshold_tlv, -9450, 150, 0);
408 /* ALC Input Signal Tracking rate select */
421 /* ALC Attack Rate select */
430 /* ALC Release Rate select */
439 /* ALC Hold Time select */
483 if (ucontrol->value.integer.value[0]) { in da9055_put_alc_sw()
485 * While enabling ALC (or ALC sync mode), calibration of the DC in da9055_put_alc_sw()
503 /* Enable ADC Left and Right */ in da9055_put_alc_sw()
518 offset_l = -avg_left_data; in da9055_put_alc_sw()
519 offset_r = -avg_right_data; in da9055_put_alc_sw()
648 /* ALC Controls */
649 SOC_DOUBLE_EXT("ALC Switch", DA9055_ALC_CTRL1, 3, 7, 1, 0,
651 SOC_SINGLE_EXT("ALC Sync Mode Switch", DA9055_ALC_CTRL1, 1, 1, 0,
653 SOC_SINGLE("ALC Offset Switch", DA9055_ALC_CTRL1, 0, 1, 0),
654 SOC_SINGLE("ALC Anticlip Mode Switch", DA9055_ALC_ANTICLIP_CTRL,
656 SOC_SINGLE("ALC Anticlip Level", DA9055_ALC_ANTICLIP_LEVEL,
658 SOC_SINGLE_TLV("ALC Min Threshold Volume", DA9055_ALC_TARGET_MIN,
660 SOC_SINGLE_TLV("ALC Max Threshold Volume", DA9055_ALC_TARGET_MAX,
662 SOC_SINGLE_TLV("ALC Noise Threshold Volume", DA9055_ALC_NOISE,
664 SOC_SINGLE_TLV("ALC Max Gain Volume", DA9055_ALC_GAIN_LIMITS,
666 SOC_SINGLE_TLV("ALC Max Attenuation Volume", DA9055_ALC_GAIN_LIMITS,
668 SOC_SINGLE_TLV("ALC Min Analog Gain Volume",
671 SOC_SINGLE_TLV("ALC Max Analog Gain Volume",
674 SOC_ENUM("ALC Attack Rate", da9055_attack_rate),
675 SOC_ENUM("ALC Release Rate", da9055_release_rate),
676 SOC_ENUM("ALC Hold Time", da9055_hold_time),
681 SOC_ENUM("ALC Integ Attack Rate", da9055_integ_attack_rate),
686 SOC_ENUM("ALC Integ Release Rate", da9055_integ_release_rate),
750 /* Headphone Output Enable */
757 /* Lineout Output Enable */
825 /* Output Enable Switches */
826 SND_SOC_DAPM_SWITCH("Headphone Left Enable", SND_SOC_NOPM, 0, 0,
828 SND_SOC_DAPM_SWITCH("Headphone Right Enable", SND_SOC_NOPM, 0, 0,
830 SND_SOC_DAPM_SWITCH("Lineout Enable", SND_SOC_NOPM, 0, 0,
918 {"Headphone Left Enable", "Switch", "MIXOUT Left"},
919 {"Headphone Left", NULL, "Headphone Left Enable"},
924 {"Headphone Right Enable", "Switch", "MIXOUT Right"},
925 {"Headphone Right", NULL, "Headphone Right Enable"},
930 {"Lineout Enable", "Switch", "MIXOUT Right"},
931 {"Lineout", NULL, "Lineout Enable"},
1050 struct snd_soc_component *component = dai->component; in da9055_hw_params()
1069 return -EINVAL; in da9055_hw_params()
1118 return -EINVAL; in da9055_hw_params()
1121 if (da9055->mclk_rate) { in da9055_hw_params()
1126 * Non-PLL Mode in da9055_hw_params()
1135 if (da9055->mclk_rate && (da9055->mclk_rate != sysclk)) { in da9055_hw_params()
1137 if (!da9055->master) { in da9055_hw_params()
1138 /* PLL slave mode, enable PLL and also SRM */ in da9055_hw_params()
1143 /* PLL master mode, only enable PLL */ in da9055_hw_params()
1158 struct snd_soc_component *component = codec_dai->component; in da9055_set_dai_fmt()
1174 return -EINVAL; in da9055_set_dai_fmt()
1179 (da9055->master != mode)) in da9055_set_dai_fmt()
1180 return -EINVAL; in da9055_set_dai_fmt()
1182 da9055->master = mode; in da9055_set_dai_fmt()
1199 return -EINVAL; in da9055_set_dai_fmt()
1215 struct snd_soc_component *component = dai->component; in da9055_mute()
1238 struct snd_soc_component *component = codec_dai->component; in da9055_set_dai_sysclk()
1253 da9055->mclk_rate = freq; in da9055_set_dai_sysclk()
1256 dev_err(codec_dai->dev, "Unsupported MCLK value %d\n", in da9055_set_dai_sysclk()
1258 return -EINVAL; in da9055_set_dai_sysclk()
1262 dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id); in da9055_set_dai_sysclk()
1263 return -EINVAL; in da9055_set_dai_sysclk()
1281 struct snd_soc_component *component = codec_dai->component; in da9055_set_dai_pll()
1290 if (!da9055->master && (fout != 2822400)) in da9055_set_dai_pll()
1297 (da9055->master == da9055_pll_div[cnt].mode) && in da9055_set_dai_pll()
1316 dev_err(codec_dai->dev, "Error in setting up PLL\n"); in da9055_set_dai_pll()
1317 return -EINVAL; in da9055_set_dai_pll()
1331 .name = "da9055-hifi",
1361 /* Enable VMID reference & master bias */ in da9055_set_bias_level()
1380 /* Enable all Gain Ramps */ in da9055_probe()
1406 * One to enable corresponding amplifier and other to enable its in da9055_probe()
1425 if (da9055->pdata) { in da9055_probe()
1427 if (da9055->pdata->micbias_source) { in da9055_probe()
1436 switch (da9055->pdata->micbias) { in da9055_probe()
1443 (da9055->pdata->micbias) << 4); in da9055_probe()
1477 struct da9055_platform_data *pdata = dev_get_platdata(&i2c->dev); in da9055_i2c_probe()
1480 da9055 = devm_kzalloc(&i2c->dev, sizeof(struct da9055_priv), in da9055_i2c_probe()
1483 return -ENOMEM; in da9055_i2c_probe()
1486 da9055->pdata = pdata; in da9055_i2c_probe()
1490 da9055->regmap = devm_regmap_init_i2c(i2c, &da9055_regmap_config); in da9055_i2c_probe()
1491 if (IS_ERR(da9055->regmap)) { in da9055_i2c_probe()
1492 ret = PTR_ERR(da9055->regmap); in da9055_i2c_probe()
1493 dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret); in da9055_i2c_probe()
1497 ret = devm_snd_soc_register_component(&i2c->dev, in da9055_i2c_probe()
1500 dev_err(&i2c->dev, "Failed to register da9055 component: %d\n", in da9055_i2c_probe()
1514 { "da9055-codec" },
1521 { .compatible = "dlg,da9055-codec", },
1530 .name = "da9055-codec",