1 // SPDX-License-Identifier: GPL-2.0+
150 /* PLL bit fields */
217 	u8 mode;	/* 0 = slave, 1 = master */
220 /* PLL dividers table */
222 	/* for MASTER mode, fs = 44.1Khz */
230 	/* for MASTER mode, fs = 48Khz */
259  * min		: 0x11 (-54.0 dB)
261  * reserved	: 0x00 - 0x0F
267 	/* -54 dB to +15 dB */
268 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
273 	/* -54dB to 15dB */
274 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-5400, 150, 0)
278 	0x0, 0x2, TLV_DB_SCALE_ITEM(-1800, 0, 1),
279 	/* -18dB to 6dB */
280 	0x3, 0x7, TLV_DB_SCALE_ITEM(-1800, 600, 0)
285 	/* -48dB to 21dB */
286 	0x11, 0x3f, TLV_DB_SCALE_ITEM(-4800, 150, 0)
289 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
290 static const DECLARE_TLV_DB_SCALE(adc_eq_master_gain_tlv, -1800, 600, 1);
291 static const DECLARE_TLV_DB_SCALE(dac_gain_tlv, -7725, 75, 0);
292 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
293 static const DECLARE_TLV_DB_SCALE(aux2_vol_tlv, -600, 600, 0);
294 static const DECLARE_TLV_DB_SCALE(inpga_gain_tlv, -450, 150, 0);
331 	if (ucontrol->value.integer.value[0]) {  in da7210_put_alc_sw()
334 			dev_dbg(component->dev,  in da7210_put_alc_sw()
336 			return -EINVAL;  in da7210_put_alc_sw()
355 	if (ucontrol->value.integer.value[0]) {  in da7210_put_noise_sup_sw()
385 	return -EINVAL;  in da7210_put_noise_sup_sw()
428 	SOC_SINGLE_TLV("ADC EQ Master Volume", DA7210_ADC_EQ5, 4, 0x3,
671 	int master;  member
758 	struct snd_soc_component *component = dai->component;  in da7210_hw_params()
786 		return -EINVAL;  in da7210_hw_params()
833 		return -EINVAL;  in da7210_hw_params()
841 	if (da7210->mclk_rate && (da7210->mclk_rate != sysclk)) {  in da7210_hw_params()
842 		/* PLL mode, disable PLL bypass */  in da7210_hw_params()
845 		if (!da7210->master) {  in da7210_hw_params()
846 			/* PLL slave mode, also enable SRM */  in da7210_hw_params()
854 		/* PLL bypass mode, enable PLL bypass and Auto Detection */  in da7210_hw_params()
872 	struct snd_soc_component *component = codec_dai->component;  in da7210_set_dai_fmt()
882 		return -EINVAL;  in da7210_set_dai_fmt()
886 		da7210->master = 1;  in da7210_set_dai_fmt()
890 		da7210->master = 0;  in da7210_set_dai_fmt()
894 		return -EINVAL;  in da7210_set_dai_fmt()
912 		return -EINVAL;  in da7210_set_dai_fmt()
929 	struct snd_soc_component *component = dai->component;  in da7210_mute()
945 	struct snd_soc_component *component = codec_dai->component;  in da7210_set_dai_sysclk()
958 			da7210->mclk_rate = freq;  in da7210_set_dai_sysclk()
961 			dev_err(codec_dai->dev, "Unsupported MCLK value %d\n",  in da7210_set_dai_sysclk()
963 			return -EINVAL;  in da7210_set_dai_sysclk()
967 		dev_err(codec_dai->dev, "Unknown clock source %d\n", clk_id);  in da7210_set_dai_sysclk()
968 		return -EINVAL;  in da7210_set_dai_sysclk()
973  * da7210_set_dai_pll	:Configure the codec PLL
975  * @pll_id: da7210 has only one pll, so pll_id is always zero
980  * Note: Supported PLL input frequencies are 12MHz, 13MHz, 13.5MHz, 14.4MHz,
988 	struct snd_soc_component *component = codec_dai->component;  in da7210_set_dai_pll()
994 	if (!da7210->master)  in da7210_set_dai_pll()
997 	/* Search pll div array for correct divisors */  in da7210_set_dai_pll()
1001 		    (da7210->master ==  da7210_pll_div[cnt].mode) &&  in da7210_set_dai_pll()
1015 	/* Write PLL dividers */  in da7210_set_dai_pll()
1021 	/* Enable PLL */  in da7210_set_dai_pll()
1029 	dev_err(codec_dai->dev, "Unsupported PLL input frequency %d\n", fref);  in da7210_set_dai_pll()
1030 	return -EINVAL;  in da7210_set_dai_pll()
1044 	.name = "da7210-hifi",
1069 	dev_info(component->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);  in da7210_probe()
1071 	da7210->mclk_rate       = 0;    /* This will be set from set_sysclk() */  in da7210_probe()
1072 	da7210->master          = 0;    /* This will be set from set_fmt() */  in da7210_probe()
1126 	 * up/down in a controlled, pop-free manner. Also, as per application  in da7210_probe()
1134 	 * - "Enable bit" of an IO or ADC/DAC is used to enable it in probe()  in da7210_probe()
1135 	 * - "STANDBY bit" is controlled by DAPM  in da7210_probe()
1150 	/* Set PLL Master clock range 10-20 MHz, enable PLL bypass */  in da7210_probe()
1154 	/* Diable PLL and bypass it */  in da7210_probe()
1160 	dev_info(component->dev, "DA7210 Audio Codec %s\n", DA7210_VERSION);  in da7210_probe()
1182 	/* System controller master disable */
1184 	/* Set PLL Master clock range 10-20 MHz */
1192 	/* to re-lock */
1213 	da7210 = devm_kzalloc(&i2c->dev, sizeof(struct da7210_priv),  in da7210_i2c_probe()
1216 		return -ENOMEM;  in da7210_i2c_probe()
1220 	da7210->regmap = devm_regmap_init_i2c(i2c, &da7210_regmap_config_i2c);  in da7210_i2c_probe()
1221 	if (IS_ERR(da7210->regmap)) {  in da7210_i2c_probe()
1222 		ret = PTR_ERR(da7210->regmap);  in da7210_i2c_probe()
1223 		dev_err(&i2c->dev, "regmap_init() failed: %d\n", ret);  in da7210_i2c_probe()
1227 	ret = regmap_register_patch(da7210->regmap, da7210_regmap_i2c_patch,  in da7210_i2c_probe()
1230 		dev_warn(&i2c->dev, "Failed to apply regmap patch: %d\n", ret);  in da7210_i2c_probe()
1232 	ret =  devm_snd_soc_register_component(&i2c->dev,  in da7210_i2c_probe()
1235 		dev_err(&i2c->dev, "Failed to register component: %d\n", ret);  in da7210_i2c_probe()
1263 	/* System controller master disable */
1265 	/* Set PLL Master clock range 10-20 MHz */
1275 	/* to re-lock */
1300 	da7210 = devm_kzalloc(&spi->dev, sizeof(struct da7210_priv),  in da7210_spi_probe()
1303 		return -ENOMEM;  in da7210_spi_probe()
1306 	da7210->regmap = devm_regmap_init_spi(spi, &da7210_regmap_config_spi);  in da7210_spi_probe()
1307 	if (IS_ERR(da7210->regmap)) {  in da7210_spi_probe()
1308 		ret = PTR_ERR(da7210->regmap);  in da7210_spi_probe()
1309 		dev_err(&spi->dev, "Failed to register regmap: %d\n", ret);  in da7210_spi_probe()
1313 	ret = regmap_register_patch(da7210->regmap, da7210_regmap_spi_patch,  in da7210_spi_probe()
1316 		dev_warn(&spi->dev, "Failed to apply regmap patch: %d\n", ret);  in da7210_spi_probe()
1318 	ret = devm_snd_soc_register_component(&spi->dev,  in da7210_spi_probe()