Lines Matching +full:rate +full:- +full:lp +full:- +full:ms
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright (C) 2016-2018, 2020, 2022, 2025 Cirrus Logic, Inc. and
8 #include <dt-bindings/sound/cs48l32.h>
32 #include <sound/soc-component.h>
33 #include <sound/soc-dai.h>
34 #include <sound/soc-dapm.h>
39 static const char * const cs48l32_core_supplies[] = { "vdd-a", "vdd-io" };
193 static const DECLARE_TLV_DB_SCALE(cs48l32_eq_tlv, -1200, 100, 0);
194 static const DECLARE_TLV_DB_SCALE(cs48l32_digital_tlv, -6400, 50, 0);
195 static const DECLARE_TLV_DB_SCALE(cs48l32_noise_tlv, -10800, 600, 0);
196 static const DECLARE_TLV_DB_SCALE(cs48l32_mixer_tlv, -3200, 100, 0);
201 struct cs48l32 *cs48l32 = &cs48l32_codec->core;
206 if (pm_runtime_suspended(cs48l32->dev))
214 ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &val);
216 dev_err(cs48l32_codec->core.dev, "%s Failed to read register: %d (%d)\n",
224 "Sample Rate 1", "Sample Rate 2", "Sample Rate 3", "Sample Rate 4",
239 mutex_lock(&cs48l32_codec->rate_lock);
246 mutex_unlock(&cs48l32_codec->rate_lock);
326 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value;
330 mux = ucontrol->value.enumerated.item[0];
332 return -EINVAL;
334 switch (e->reg) {
336 in_type = cs48l32_codec->in_type[0][mux];
339 in_type = cs48l32_codec->in_type[1][mux];
342 return -EINVAL;
345 src_val = mux << e->shift_l;
351 e->reg,
390 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value;
394 mode = ucontrol->value.enumerated.item[0];
402 dev_err(component->dev,
412 dev_err(component->dev,
418 e->reg,
422 dev_err(component->dev, "Failed to set input mode: %d\n", result);
433 dev_err(component->dev,
443 dev_err(component->dev,
455 return -EINVAL;
475 "16-24kHz", "20-28kHz",
522 "-6dB", "-9dB", "-12dB", "-15dB", "-18dB", "-21dB", "-24dB", "-27dB",
627 "0 ms", "0.79 ms", "1.58 ms", "3.16 ms", "6.33 ms", "12.67 ms", "25.34 ms", "50.69 ms",
647 "0ms/6dB", "0.5ms/6dB", "1ms/6dB", "2ms/6dB", "4ms/6dB", "8ms/6dB", "16ms/6dB", "32ms/6dB",
709 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
714 /* Cannot change rate on an active input */
715 if (cs48l32_is_input_enabled(component, e->reg)) {
716 ret = -EBUSY;
757 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
764 /* Cannot change rate on an active input */
765 if (cs48l32_is_input_enabled(component, mc->reg)) {
766 ret = -EBUSY;
898 "Low-pass", "High-pass"
917 __be32 *data = (__be32 *)ucontrol->value.bytes.data;
921 dev_err(cs48l32_codec->core.dev, "Rejecting unstable LHPF coefficients\n");
922 return -EINVAL;
929 "Low-pass", "High-pass",
952 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value;
955 item = snd_soc_enum_val_to_item(e, cs48l32_codec->eq_mode[e->shift_l]);
956 ucontrol->value.enumerated.item[0] = item;
967 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value;
968 unsigned int *item = ucontrol->value.enumerated.item;
972 if (item[0] >= e->items)
973 return -EINVAL;
978 if (cs48l32_codec->eq_mode[e->shift_l] != val) {
979 cs48l32_codec->eq_mode[e->shift_l] = val;
990 struct cs48l32_eq_control *ctl = (void *) kcontrol->private_value;
992 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
993 uinfo->count = 1;
994 uinfo->value.integer.min = 0;
995 uinfo->value.integer.max = ctl->max;
1005 struct cs48l32_eq_control *params = (void *)kcontrol->private_value;
1010 block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1);
1011 block_idx /= (CS48L32_EQ2_BAND1_COEFF1 - CS48L32_EQ1_BAND1_COEFF1);
1013 coeffs = &cs48l32_codec->eq_coefficients[block_idx][0];
1014 coeff_idx = (params->reg - params->block_base) / 2;
1017 if (params->shift == 0)
1020 ucontrol->value.integer.value[0] = be16_to_cpu(coeffs[coeff_idx]);
1031 struct cs48l32_eq_control *params = (void *)kcontrol->private_value;
1036 block_idx = ((int) params->block_base - (int) CS48L32_EQ1_BAND1_COEFF1);
1037 block_idx /= (CS48L32_EQ2_BAND1_COEFF1 - CS48L32_EQ1_BAND1_COEFF1);
1039 coeffs = &cs48l32_codec->eq_coefficients[block_idx][0];
1040 coeff_idx = (params->reg - params->block_base) / 2;
1043 if (params->shift == 0)
1047 coeffs[coeff_idx] = cpu_to_be16(ucontrol->value.integer.value[0]);
1067 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value;
1069 const unsigned int rate_num = e->mask;
1072 if (rate_num >= ARRAY_SIZE(cs48l32_codec->dsp_dma_rates))
1073 return -EINVAL;
1075 cached_rate = cs48l32_codec->dsp_dma_rates[rate_num];
1077 ucontrol->value.enumerated.item[0] = item;
1088 struct soc_enum *e = (struct soc_enum *) kcontrol->private_value;
1089 const unsigned int rate_num = e->mask;
1090 const unsigned int item = ucontrol->value.enumerated.item[0];
1094 if (item >= e->items)
1095 return -EINVAL;
1097 if (rate_num >= ARRAY_SIZE(cs48l32_codec->dsp_dma_rates))
1098 return -EINVAL;
1103 if (cs48l32_codec->dsp_dma_rates[rate_num] != val) {
1104 cs48l32_codec->dsp_dma_rates[rate_num] = val;
1185 const u8 *rate = cs48l32_codec->dsp_dma_rates;
1188 reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_RX1;
1190 regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate);
1192 rate++;
1195 reg = dsp->cs_dsp.base + CS48L32_HALO_SAMPLE_RATE_TX1;
1197 regmap_update_bits(dsp->cs_dsp.regmap, reg, CS48L32_HALO_DSP_RATE_MASK, *rate);
1199 rate++;
1210 struct regmap *regmap = cs48l32_codec->core.regmap;
1213 for (i = 0; i < regs->n_pwd; ++i) {
1214 ret = regmap_write(regmap, regs->pwd[i], 0);
1219 for (i = 0; i < regs->n_ext; ++i) {
1220 for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) {
1230 dev_warn(cs48l32_codec->core.dev, "Failed to write SRAM enables (%d)\n", ret);
1236 struct regmap *regmap = cs48l32_codec->core.regmap;
1239 /* disable power-off */
1240 for (i = 0; i < regs->n_ext; ++i) {
1241 for (j = regs->ext[i].start; j <= regs->ext[i].end; j += 4) {
1248 /* power-up the banks in sequence */
1249 for (i = 0; i < regs->n_pwd; ++i) {
1250 ret = regmap_write(regmap, regs->pwd[i], 0x1);
1254 udelay(1); /* allow bank to power-up */
1256 ret = regmap_write(regmap, regs->pwd[i], 0x3);
1260 udelay(1); /* allow bank to power-up */
1266 dev_err(cs48l32_codec->core.dev, "Failed to write SRAM enables (%d)\n", ret);
1275 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1277 struct regmap *regmap = cs48l32_codec->core.regmap;
1278 struct wm_adsp *dsp = &cs48l32_codec->dsp;
1283 return -EINVAL;
1287 dev_err(component->dev, "Failed to read #%x: %d\n", freq_reg, ret);
1296 dev_err(component->dev, "Failed to read #%x: %d\n", freqsel_reg, ret);
1302 dev_err(component->dev, "SYSCLK FREQ (#%x) != FREQ STS (#%x)\n",
1304 return -ETIMEDOUT;
1311 ret = regmap_write(dsp->cs_dsp.regmap,
1312 dsp->cs_dsp.base + CS48L32_DSP_CLOCK_FREQ_OFFS, freq);
1314 dev_err(component->dev, "Failed to set HALO clock freq: %d\n", ret);
1340 struct regmap *regmap = cs48l32_codec->core.regmap;
1347 ret = pm_runtime_resume_and_get(cs48l32_codec->core.dev);
1349 dev_warn(cs48l32_codec->core.dev, "irq could not get pm runtime: %d\n", ret);
1355 dev_warn(cs48l32_codec->core.dev, "Read IRQ1_STATUS failed: %d\n", ret);
1363 dev_warn(cs48l32_codec->core.dev, "Read IRQ regs failed: %d\n", ret);
1373 wm_adsp_compr_handle_irq(&cs48l32_codec->dsp);
1376 dev_warn(cs48l32_codec->core.dev, "MPU err IRQ\n");
1377 wm_halo_bus_error(irq, &cs48l32_codec->dsp);
1381 dev_warn(cs48l32_codec->core.dev, "WDT expire IRQ\n");
1382 wm_halo_wdt_expire(irq, &cs48l32_codec->dsp);
1388 pm_runtime_put_autosuspend(cs48l32_codec->core.dev);
1422 return -EINVAL;
1429 struct regmap *regmap = cs48l32_codec->core.regmap;
1442 dev_err(cs48l32_codec->core.dev, "Invalid PDM FLLCLK src %d\n", source);
1443 return -EINVAL;
1454 struct regmap *regmap = cs48l32_codec->core.regmap;
1465 clk = &cs48l32_codec->sysclk;
1472 clk = &cs48l32_codec->dspclk;
1479 return -EINVAL;
1483 dev_err(cs48l32_codec->core.dev, "Failed to get %s setting for %dHZ\n", name, freq);
1490 dev_dbg(cs48l32_codec->core.dev, "%s cleared\n", name);
1499 dev_dbg(cs48l32_codec->core.dev, "%s set to %uHz", name, freq);
1506 struct regmap *regmap = fll->codec->core.regmap;
1521 struct regmap *regmap = fll->codec->core.regmap;
1528 regmap_read(regmap, fll->sts_addr, &val);
1529 if (!!(val & fll->sts_mask) == requested)
1547 return -ETIMEDOUT;
1552 struct cs48l32 *cs48l32 = &fll->codec->core;
1560 * again due to a control clock being required, the lock won't re-assert
1564 regmap_set_bits(cs48l32->regmap,
1565 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1567 regmap_clear_bits(cs48l32->regmap,
1568 fll->base + CS48L32_FLL_CONTROL2_OFFS,
1570 regmap_set_bits(cs48l32->regmap,
1571 fll->base + CS48L32_FLL_CONTROL5_OFFS,
1573 regmap_update_bits_check(cs48l32->regmap,
1574 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1589 regmap_clear_bits(cs48l32->regmap,
1590 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1594 pm_runtime_put_autosuspend(cs48l32->dev);
1601 struct regmap *regmap = fll->codec->core.regmap;
1607 cs48l32_fll_dbg(fll, "fin=%d, fout=%d\n", fin, fll->fout);
1615 fout = fll->fout;
1662 return -EINVAL;
1669 return -EINVAL;
1687 cs48l32_fll_err(fll, "N not in valid %s mode range %d-%d: %d\n",
1689 return -EINVAL;
1694 return -EINVAL;
1699 fll->base + CS48L32_FLL_CONTROL2_OFFS,
1711 fll->base + CS48L32_FLL_CONTROL3_OFFS,
1718 fll->base + CS48L32_FLL_CONTROL4_OFFS,
1731 struct cs48l32 *cs48l32 = &fll->codec->core;
1732 int already_enabled = cs48l32_is_enabled_fll(fll, fll->base);
1739 pm_runtime_get_sync(cs48l32->dev);
1745 regmap_set_bits(cs48l32->regmap,
1746 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1750 ret = cs48l32_fllhj_apply(fll, fll->ref_freq);
1755 regmap_update_bits(cs48l32->regmap,
1756 fll->base + CS48L32_FLL_CONTROL2_OFFS,
1758 fll->ref_src << CS48L32_FLL_REFCLK_SRC_SHIFT);
1760 regmap_set_bits(cs48l32->regmap,
1761 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1765 regmap_set_bits(cs48l32->regmap,
1766 fll->base + CS48L32_FLL_CONTROL2_OFFS,
1769 regmap_set_bits(cs48l32->regmap,
1770 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1774 regmap_clear_bits(cs48l32->regmap,
1775 fll->base + CS48L32_FLL_CONTROL1_OFFS,
1790 return -EINVAL;
1793 if (fll->fout && fout != fll->fout) {
1795 return -EINVAL;
1800 return -EINVAL;
1806 return -EINVAL;
1817 if (fll->ref_src == source && fll->ref_freq == fin && fll->fout == fout)
1821 return -EINVAL;
1823 fll->ref_src = source;
1824 fll->ref_freq = fin;
1825 fll->fout = fout;
1837 fll->ref_src = CS48L32_FLL_SRC_NONE;
1851 return -EINVAL;
1854 return cs48l32_fllhj_set_refclk(&cs48l32_codec->fll, source, fref, fout);
1859 struct snd_soc_component *component = dai->component;
1861 struct regmap *regmap = cs48l32_codec->core.regmap;
1864 switch (dai->id) {
1874 return -EINVAL;
1880 /* DOUT high-impendance when not transmitting */
1888 struct snd_soc_component *component = dai->component;
1890 struct regmap *regmap = cs48l32_codec->core.regmap;
1892 unsigned int base = dai->driver->base;
1905 return -EINVAL;
1915 return -EINVAL;
1922 return -EINVAL;
1941 return -EINVAL;
1958 return -EINVAL;
2029 struct snd_soc_component *component = dai->component;
2031 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[dai->id - 1];
2034 if (!substream->runtime)
2037 switch (dai_priv->clk) {
2042 base_rate = cs48l32_codec->sysclk;
2049 dai_priv->constraint.mask = CS48L32_RATE_MASK;
2051 dai_priv->constraint.mask = CS48L32_44K1_RATE_MASK;
2053 dai_priv->constraint.mask = CS48L32_48K_RATE_MASK;
2055 return snd_pcm_hw_constraint_list(substream->runtime, 0,
2057 &dai_priv->constraint);
2064 struct snd_soc_component *component = dai->component;
2066 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[dai->id - 1];
2067 unsigned int sr_val, sr_reg, rate;
2069 rate = params_rate(params);
2071 if (cs48l32_sr_vals[sr_val] == rate)
2075 cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate);
2076 return -EINVAL;
2079 switch (dai_priv->clk) {
2093 return -EINVAL;
2130 struct snd_soc_component *component = dai->component;
2132 struct regmap *regmap = cs48l32_codec->core.regmap;
2133 int base = dai->driver->base;
2134 int dai_id = dai->id - 1;
2135 unsigned int rate = params_rate(params);
2142 cs48l32_asp_dbg(dai, "hwparams in: ch:%u dataw:%u rate:%u\n",
2143 params_channels(params), dataw, rate);
2148 if (cs48l32_codec->tdm_slots[dai_id]) {
2149 n_slots = cs48l32_codec->tdm_slots[dai_id];
2150 slotw = cs48l32_codec->tdm_width[dai_id];
2171 (cs48l32_sclk_rates[i].freq % rate == 0)) {
2177 cs48l32_asp_err(dai, "Unsupported sample rate %dHz\n", rate);
2178 return -EINVAL;
2240 struct snd_soc_component *component = dai->component;
2242 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[dai->id - 1];
2243 unsigned int base = dai->driver->base;
2248 if (clk_id == dai_priv->clk)
2253 return -EBUSY;
2270 return -EINVAL;
2273 dai_priv->clk = clk_id;
2277 ret = regmap_read(cs48l32_codec->core.regmap,
2281 cs48l32_asp_err(dai, "Failed to check rate: %d\n", ret);
2289 mutex_lock(&cs48l32_codec->rate_lock);
2290 /* Guard the rate change with SYSCLK cycles */
2299 mutex_unlock(&cs48l32_codec->rate_lock);
2310 struct snd_soc_component *component = dai->component;
2312 struct regmap *regmap = cs48l32_codec->core.regmap;
2317 slot = ffs(mask) - 1;
2321 if (i - (j * 4) >= 4) {
2327 shift = (8 * (i - j * 4));
2344 struct snd_soc_component *component = dai->component;
2346 int base = dai->driver->base;
2347 int rx_max_chan = dai->driver->playback.channels_max;
2348 int tx_max_chan = dai->driver->capture.channels_max;
2351 if (dai->id > CS48L32_MAX_ASP)
2352 return -EINVAL;
2355 tx_mask = (1 << tx_max_chan) - 1;
2356 rx_mask = (1 << rx_max_chan) - 1;
2364 cs48l32_codec->tdm_width[dai->id - 1] = slot_width;
2365 cs48l32_codec->tdm_slots[dai->id - 1] = slots;
2382 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2392 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2396 if (w->shift % 2)
2401 reg += (w->shift / 2) * (CS48L32_IN2L_CONTROL2 - CS48L32_IN1L_CONTROL2);
2405 switch (w->shift) {
2421 cs48l32_codec->in_up_pending++;
2426 switch (w->shift) {
2443 cs48l32_codec->in_up_pending--;
2446 /* Uncached write-only register, no need for update_bits */
2447 if (!cs48l32_codec->in_up_pending) {
2448 snd_soc_component_write(component, cs48l32_codec->in_vu_reg,
2455 snd_soc_component_write(component, cs48l32_codec->in_vu_reg,
2477 * Uncached write-only register, no need for update_bits.
2480 snd_soc_component_write(component, cs48l32_codec->in_vu_reg, CS48L32_IN_VU);
2496 if (abs((a << 16) / (CS48L32_EQ_MAX_COEFF + 1 - b)) >= ((CS48L32_EQ_MAX_COEFF + 1) << 4))
2505 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2507 struct regmap *regmap = cs48l32_codec->core.regmap;
2508 unsigned int mode = cs48l32_codec->eq_mode[w->shift];
2510 __be16 *data = &cs48l32_codec->eq_coefficients[w->shift][0];
2514 reg += w->shift * (CS48L32_EQ2_BAND1_COEFF1 - CS48L32_EQ1_BAND1_COEFF1);
2523 dev_err(cs48l32_codec->core.dev, "Rejecting unstable EQ coefficients.\n");
2524 ret = -EINVAL;
2528 dev_err(cs48l32_codec->core.dev,
2535 w->mask,
2536 mode << w->shift);
2538 dev_err(cs48l32_codec->core.dev,
2562 SOC_SINGLE_EXT("IN1L LP Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_LP_MODE_SHIFT,
2564 SOC_SINGLE_EXT("IN1R LP Switch", CS48L32_IN1R_CONTROL1, CS48L32_INx_LP_MODE_SHIFT,
2588 CS48L32_RATE_ENUM("Ultrasonic 1 Rate", cs48l32_us_output_rate[0]),
2589 CS48L32_RATE_ENUM("Ultrasonic 2 Rate", cs48l32_us_output_rate[1]),
2616 SOC_ENUM("Ultrasonic 1 Detect LPF Cut-off", cs48l32_us_det_lpf_cut[0]),
2617 SOC_ENUM("Ultrasonic 2 Detect LPF Cut-off", cs48l32_us_det_lpf_cut[1]),
2683 CS48L32_RATE_CONTROL("Sample Rate 1", 1),
2684 CS48L32_RATE_CONTROL("Sample Rate 2", 2),
2685 CS48L32_RATE_CONTROL("Sample Rate 3", 3),
2686 CS48L32_RATE_CONTROL("Sample Rate 4", 4),
2688 CS48L32_RATE_ENUM("FX Rate", cs48l32_fx_rate),
2697 SOC_ENUM("AUXPDM1 Rate", cs48l32_auxpdm1_freq),
2698 SOC_ENUM("AUXPDM2 Rate", cs48l32_auxpdm2_freq),
2700 SOC_ENUM_EXT("IN1L Rate", cs48l32_input_rate[0], snd_soc_get_enum_double, cs48l32_in_rate_put),
2701 SOC_ENUM_EXT("IN1R Rate", cs48l32_input_rate[1], snd_soc_get_enum_double, cs48l32_in_rate_put),
2702 SOC_ENUM_EXT("IN2L Rate", cs48l32_input_rate[2], snd_soc_get_enum_double, cs48l32_in_rate_put),
2703 SOC_ENUM_EXT("IN2R Rate", cs48l32_input_rate[3], snd_soc_get_enum_double, cs48l32_in_rate_put),
2705 CS48L32_RATE_ENUM("Noise Generator Rate", noise_gen_rate),
2818 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2836 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-cp", 20, 0),
3286 struct snd_soc_pcm_runtime *rtd = stream->private_data;
3289 if (strcmp(snd_soc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-trace") &&
3290 strcmp(snd_soc_rtd_to_codec(rtd, 0)->name, "cs48l32-dsp-voicectrl")) {
3291 dev_err(cs48l32_codec->core.dev, "No suitable compressed stream for DAI '%s'\n",
3292 snd_soc_rtd_to_codec(rtd, 0)->name);
3293 return -EINVAL;
3296 return wm_adsp_compr_open(&cs48l32_codec->dsp, stream);
3315 .name = "cs48l32-asp1",
3337 .name = "cs48l32-asp2",
3359 .name = "cs48l32-cpu-trace",
3371 .name = "cs48l32-dsp-trace",
3382 .name = "cs48l32-cpu-voicectrl",
3394 .name = "cs48l32-dsp-voicectrl",
3409 struct regmap *regmap = cs48l32_codec->core.regmap;
3417 switch (cs48l32_codec->in_type[0][0]) {
3427 switch (cs48l32_codec->in_type[1][0]) {
3437 dev_dbg(cs48l32_codec->core.dev, "IN1_1 Analogue mode=#%x,#%x\n",
3450 for (i = 0; i < ARRAY_SIZE(cs48l32_codec->pdm_sup); i++) {
3451 dig_mode = cs48l32_codec->pdm_sup[i] << CS48L32_IN1_PDM_SUP_SHIFT;
3453 dev_dbg(cs48l32_codec->core.dev, "IN%d PDM_SUP=#%x\n", i + 1, dig_mode);
3465 struct cs48l32_dai_priv *dai_priv = &cs48l32_codec->dai[id];
3467 dai_priv->clk = CS48L32_CLK_SYSCLK_1;
3468 dai_priv->constraint = cs48l32_constraint;
3475 struct regmap *regmap = cs48l32_codec->core.regmap;
3482 dev_err(cs48l32_codec->core.dev, "Error reading EQ mode: %d\n", ret);
3487 cs48l32_codec->eq_mode[i] = (mode >> i) & 0x1;
3489 data = &cs48l32_codec->eq_coefficients[i][0];
3493 dev_err(cs48l32_codec->core.dev,
3508 snd_soc_component_init_regmap(component, cs48l32_codec->core.regmap);
3521 wm_adsp2_component_probe(&cs48l32_codec->dsp, component);
3524 regmap_clear_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_7,
3526 regmap_clear_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_9,
3537 regmap_set_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_7,
3539 regmap_set_bits(cs48l32_codec->core.regmap, CS48L32_IRQ1_MASK_9,
3542 wm_adsp2_component_remove(&cs48l32_codec->dsp, component);
3550 .name = "cs48l32-codec",
3567 struct cs48l32 *cs48l32 = &cs48l32_codec->core;
3570 ret = device_property_read_u32_array(cs48l32->dev, propname, dest, n_max);
3571 if (ret == -EINVAL)
3572 return -ENOENT;
3575 return dev_err_probe(cs48l32->dev, ret, "%s malformed\n", propname);
3582 const char *propname = "cirrus,in-type";
3587 ARRAY_SIZE(cs48l32_codec->in_type) * ARRAY_SIZE(cs48l32_codec->in_type[0]));
3599 cs48l32_codec->in_type[in_idx][mux_way_idx] = tmp[i];
3602 dev_warn(cs48l32_codec->core.dev, "Illegal %s value %d ignored\n",
3611 if (++in_idx == ARRAY_SIZE(cs48l32_codec->in_type)) {
3620 const char *propname = "cirrus,pdm-sup";
3624 static_assert(ARRAY_SIZE(tmp) == ARRAY_SIZE(cs48l32_codec->pdm_sup));
3628 for (i = 0; i < ARRAY_SIZE(cs48l32_codec->pdm_sup); i++) {
3632 cs48l32_codec->pdm_sup[i] = tmp[i];
3635 dev_warn(cs48l32_codec->core.dev, "Illegal %s value %d ignored\n",
3636 propname, cs48l32_codec->pdm_sup[i]);
3650 int irq = cs48l32_codec->core.irq;
3664 return dev_err_probe(cs48l32_codec->core.dev, ret, "Failed to get IRQ\n");
3675 static_assert(ARRAY_SIZE(cs48l32_dai) == ARRAY_SIZE(cs48l32_codec->dai));
3679 dsp = &cs48l32_codec->dsp;
3680 dsp->part = "cs48l32";
3681 dsp->cs_dsp.num = 1;
3682 dsp->cs_dsp.type = WMFW_HALO;
3683 dsp->cs_dsp.rev = 0;
3684 dsp->cs_dsp.dev = cs48l32_codec->core.dev;
3685 dsp->cs_dsp.regmap = cs48l32_codec->core.regmap;
3686 dsp->cs_dsp.base = CS48L32_DSP1_CLOCK_FREQ;
3687 dsp->cs_dsp.base_sysinfo = CS48L32_DSP1_SYS_INFO_ID;
3688 dsp->cs_dsp.mem = cs48l32_dsp1_regions;
3689 dsp->cs_dsp.num_mems = ARRAY_SIZE(cs48l32_dsp1_regions);
3690 dsp->pre_run = cs48l32_dsp_pre_run;
3696 cs48l32_codec->fll.codec = cs48l32_codec;
3697 cs48l32_codec->fll.id = 1;
3698 cs48l32_codec->fll.base = CS48L32_FLL1_CONTROL1;
3699 cs48l32_codec->fll.sts_addr = CS48L32_IRQ1_STS_6;
3700 cs48l32_codec->fll.sts_mask = CS48L32_FLL1_LOCK_STS1_MASK;
3701 cs48l32_init_fll(&cs48l32_codec->fll);
3707 ret = devm_snd_soc_register_component(cs48l32_codec->core.dev,
3712 dev_err_probe(cs48l32_codec->core.dev, ret, "Failed to register component\n");
3719 wm_adsp2_remove(&cs48l32_codec->dsp);
3729 ret = regmap_read_poll_timeout(cs48l32->regmap, CS48L32_IRQ1_EINT_2, val,
3733 dev_err(cs48l32->dev, "BOOT_DONE timed out\n");
3734 return -ETIMEDOUT;
3737 ret = regmap_read(cs48l32->regmap, CS48L32_MCU_CTRL1, &val);
3739 dev_err(cs48l32->dev, "Failed to read MCU_CTRL1: %d\n", ret);
3744 dev_err(cs48l32->dev, "MCU boot failed\n");
3745 return -EIO;
3748 pm_runtime_mark_last_busy(cs48l32->dev);
3757 ret = regmap_write(cs48l32->regmap, CS48L32_SFT_RESET, CS48L32_SFT_RESET_MAGIC);
3759 dev_err(cs48l32->dev, "Failed to write soft reset: %d\n", ret);
3770 if (cs48l32->reset_gpio)
3771 gpiod_set_raw_value_cansleep(cs48l32->reset_gpio, 0);
3776 if (cs48l32->reset_gpio) {
3777 gpiod_set_raw_value_cansleep(cs48l32->reset_gpio, 1);
3785 struct cs48l32 *cs48l32 = &cs48l32_codec->core;
3789 ret = regulator_enable(cs48l32->vdd_d);
3791 dev_err(cs48l32->dev, "Failed to enable VDD_D: %d\n", ret);
3797 regcache_cache_only(cs48l32->regmap, false);
3804 regmap_read(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, &val);
3806 regcache_mark_dirty(cs48l32->regmap);
3808 dev_dbg(cs48l32->dev, "Did not reset during suspend\n");
3810 ret = regcache_sync(cs48l32->regmap);
3812 dev_err(cs48l32->dev, "Failed to restore register cache\n");
3819 regcache_cache_only(cs48l32->regmap, true);
3820 regulator_disable(cs48l32->vdd_d);
3828 struct cs48l32 *cs48l32 = &cs48l32_codec->core;
3831 regmap_write(cs48l32->regmap, CS48L32_CTRL_IF_DEBUG3, 1);
3833 regcache_cache_only(cs48l32->regmap, true);
3834 regulator_disable(cs48l32->vdd_d);
3847 ret = clk_prepare_enable(cs48l32->mclk1);
3849 return dev_err_probe(cs48l32->dev, ret, "Failed to enable 32k clock\n");
3851 ret = regmap_update_bits(cs48l32->regmap, CS48L32_CLOCK32K,
3855 clk_disable_unprepare(cs48l32->mclk1);
3856 return dev_err_probe(cs48l32->dev, ret, "Failed to init 32k clock\n");
3864 cs48l32->mclk1 = devm_clk_get_optional(cs48l32->dev, "mclk1");
3865 if (IS_ERR(cs48l32->mclk1))
3866 return dev_err_probe(cs48l32->dev, PTR_ERR(cs48l32->mclk1),
3876 reset = devm_gpiod_get_optional(cs48l32->dev, "reset", GPIOD_OUT_LOW);
3878 return dev_err_probe(cs48l32->dev, PTR_ERR(reset), "Failed to request /RESET\n");
3883 cs48l32->reset_gpio = reset;
3890 struct device *dev = &spi->dev;
3896 cs48l32_codec = devm_kzalloc(&spi->dev, sizeof(*cs48l32_codec), GFP_KERNEL);
3898 return -ENOMEM;
3900 cs48l32 = &cs48l32_codec->core;
3901 cs48l32->dev = dev;
3902 cs48l32->irq = spi->irq;
3903 mutex_init(&cs48l32_codec->rate_lock);
3904 cs48l32_codec->in_vu_reg = CS48L32_INPUT_CONTROL3;
3906 dev_set_drvdata(cs48l32->dev, cs48l32_codec);
3910 return dev_err_probe(&spi->dev, ret, "Failed to allocate regmap\n");
3912 regcache_cache_only(cs48l32->regmap, true);
3922 static_assert(ARRAY_SIZE(cs48l32_core_supplies) == ARRAY_SIZE(cs48l32->core_supplies));
3923 for (i = 0; i < ARRAY_SIZE(cs48l32->core_supplies); i++)
3924 cs48l32->core_supplies[i].supply = cs48l32_core_supplies[i];
3926 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(cs48l32->core_supplies),
3927 cs48l32->core_supplies);
3931 cs48l32->vdd_d = devm_regulator_get(cs48l32->dev, "vdd-d");
3932 if (IS_ERR(cs48l32->vdd_d))
3933 return dev_err_probe(dev, PTR_ERR(cs48l32->vdd_d), "Failed to request vdd-d\n");
3935 ret = regulator_bulk_enable(ARRAY_SIZE(cs48l32->core_supplies), cs48l32->core_supplies);
3939 ret = regulator_enable(cs48l32->vdd_d);
3941 dev_err(dev, "Failed to enable vdd-d: %d\n", ret);
3947 regcache_cache_only(cs48l32->regmap, false);
3950 if (!cs48l32->reset_gpio) {
3958 dev_err(cs48l32->dev, "Device failed initial boot: %d\n", ret);
3962 ret = regmap_read(cs48l32->regmap, CS48L32_DEVID, &hwid);
3973 ret = -ENODEV;
3974 dev_err_probe(cs48l32->dev, ret, "Unknown device ID: %#x\n", hwid);
3978 ret = regmap_read(cs48l32->regmap, CS48L32_REVID, &rev);
3985 ret = regmap_read(cs48l32->regmap, CS48L32_OTPID, &otp_rev);
3998 dev_err(cs48l32->dev, "Failed to apply patch %d\n", ret);
4003 ret = regmap_set_bits(cs48l32->regmap, CS48L32_IRQ1_MASK_2, CS48L32_BOOT_DONE_EINT1_MASK);
4009 pm_runtime_set_active(cs48l32->dev);
4010 pm_runtime_set_autosuspend_delay(cs48l32->dev, 100);
4011 pm_runtime_use_autosuspend(cs48l32->dev);
4012 pm_runtime_enable(cs48l32->dev);
4021 clk_disable_unprepare(cs48l32->mclk1);
4024 regulator_disable(cs48l32->vdd_d);
4026 regulator_bulk_disable(ARRAY_SIZE(cs48l32->core_supplies), cs48l32->core_supplies);
4034 struct cs48l32 *cs48l32 = &cs48l32_codec->core;
4037 if (cs48l32->irq >= 1)
4038 free_irq(cs48l32->irq, cs48l32_codec);
4040 pm_runtime_disable(cs48l32->dev);
4041 regulator_disable(cs48l32->vdd_d);
4042 clk_disable_unprepare(cs48l32->mclk1);
4044 regulator_bulk_disable(ARRAY_SIZE(cs48l32->core_supplies), cs48l32->core_supplies);
4046 mutex_destroy(&cs48l32_codec->rate_lock);