Lines Matching full:in1l
73 "IN1L",
134 0x010, /* IN1L signal path */
375 SOC_DAPM_ENUM_EXT("IN1L Mux", cs48l32_in1muxl_enum,
470 "IN1L", "IN1R", "IN2L", "IN2R",
2555 SOC_SINGLE_RANGE_TLV("IN1L Volume", CS48L32_IN1L_CONTROL2,
2562 SOC_SINGLE_EXT("IN1L LP Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_LP_MODE_SHIFT,
2567 SOC_SINGLE("IN1L HPF Switch", CS48L32_IN1L_CONTROL1, CS48L32_INx_HPF_SHIFT, 1, 0),
2572 SOC_SINGLE_EXT_TLV("IN1L Digital Volume", CS48L32_IN1L_CONTROL2,
2700 SOC_ENUM_EXT("IN1L Rate", cs48l32_input_rate[0], snd_soc_get_enum_double, cs48l32_in_rate_put),
2876 SND_SOC_DAPM_MUX("IN1L Mux", SND_SOC_NOPM, 0, 0, &cs48l32_inmux[0]),
2879 SND_SOC_DAPM_MUX("IN1L Mode", SND_SOC_NOPM, 0, 0, &cs48l32_dmode_mux[0]),
2922 SND_SOC_DAPM_PGA_E("IN1L PGA", CS48L32_INPUT_CONTROL, CS48L32_IN1L_EN_SHIFT,
3140 { "IN1L Mux", "Analog 1", "IN1LN_1" },
3141 { "IN1L Mux", "Analog 2", "IN1LN_2" },
3142 { "IN1L Mux", "Analog 1", "IN1LP_1" },
3143 { "IN1L Mux", "Analog 2", "IN1LP_2" },
3149 { "IN1L PGA", NULL, "IN1L Mode" },
3152 { "IN1L Mode", "Analog", "IN1L Mux" },
3155 { "IN1L Mode", "Digital", "IN1_PDMCLK" },
3156 { "IN1L Mode", "Digital", "IN1_PDMDATA" },
3160 { "IN1L PGA", NULL, "VOUT_MIC" },
3174 { "Ultrasonic 1 Input", "IN1L", "IN1L PGA" },
3179 { "Ultrasonic 2 Input", "IN1L", "IN1L PGA" },
3247 { "AUXPDM1 Analog Input", "IN1L", "IN1L PGA" },
3250 { "AUXPDM2 Analog Input", "IN1L", "IN1L PGA" },
3254 { "AUXPDM1 Input", "IN1 Digital", "IN1L PGA" },
3260 { "AUXPDM2 Input", "IN1 Digital", "IN1L PGA" },