Lines Matching +full:system +full:- +full:ctl
1 /* SPDX-License-Identifier: GPL-2.0-only */
29 #define CS43130_SYS_CLK_CTL_1 0x010006 /* System Clocking Ctl 1 */
40 #define CS43130_PWDN_CTL 0x020000 /* Power Down Ctl */
53 #define CS43130_CLKOUT_CTL 0x040004 /* CLKOUT Ctl */
84 #define CS43130_DSD_PATH_CTL_1 0x070002 /* DSD Proc Path Sig Ctl 1 */
86 #define CS43130_DSD_PATH_CTL_2 0x070004 /* DSD Proc Path Sig Ctl 2 */
87 #define CS43130_DSD_PCM_MIX_CTL 0x070005 /* DSD and PCM Mixing Ctl */
88 #define CS43130_DSD_PATH_CTL_3 0x070006 /* DSD Proc Path Sig Ctl 3 */
89 #define CS43130_HP_OUT_CTL_1 0x080000 /* HP Output Ctl 1 */
95 #define CS43130_PCM_PATH_CTL_1 0x090003 /* PCM Path Signal Ctl 1 */
96 #define CS43130_PCM_PATH_CTL_2 0x090004 /* PCM Path Signal Ctl 2 */
98 #define CS43130_CLASS_H_CTL 0x0B0000 /* Class H Ctl */
362 CS43130_XTAL_UNUSED = -1,