Lines Matching +full:vd +full:- +full:supply
28 "VD",
52 /* -127.5dB to 0dB with step of 0.5dB */
53 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
54 /* -64dB to 24dB with step of 0.5dB */
55 static const DECLARE_TLV_DB_SCALE(adc_tlv, -6400, 50, 0);
57 static const char *const cs42xx8_adc_single[] = { "Differential", "Single-Ended" };
82 CS42XX8_VOLAIN2, 0, -0x80, 0x30, 7, 0, adc_tlv),
84 CS42XX8_VOLAIN4, 0, -0x80, 0x30, 7, 0, adc_tlv),
91 SOC_SINGLE("ADC High-Pass Filter Switch", CS42XX8_ADCCTL, 7, 1, 1),
92 SOC_SINGLE("DAC De-emphasis Switch", CS42XX8_ADCCTL, 5, 1, 0),
105 CS42XX8_VOLAIN6, 0, -0x80, 0x30, 7, 0, adc_tlv),
205 struct snd_soc_component *component = codec_dai->component;
208 cs42xx8->sysclk = freq;
216 struct snd_soc_component *component = codec_dai->component;
235 dev_err(component->dev, "unsupported dai format\n");
236 return -EINVAL;
239 regmap_update_bits(cs42xx8->regmap, CS42XX8_INTF,
246 cs42xx8->slave_mode = true;
249 cs42xx8->slave_mode = false;
252 dev_err(component->dev, "unsupported master/slave mode\n");
253 return -EINVAL;
263 struct snd_soc_component *component = dai->component;
265 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
273 cs42xx8->tx_channels = params_channels(params);
276 rate[!tx] = cs42xx8->rate[!tx];
278 ratio[tx] = rate[tx] > 0 ? cs42xx8->sysclk / rate[tx] : 0;
279 ratio[!tx] = rate[!tx] > 0 ? cs42xx8->sysclk / rate[!tx] : 0;
283 if (cs42xx8->slave_mode) {
293 dev_err(component->dev,
295 return -EINVAL;
307 cs42xx8->sysclk >= cs42xx8_ratios[i].min_mclk &&
308 cs42xx8->sysclk <= cs42xx8_ratios[i].max_mclk;
332 dev_err(component->dev, "unsupported sysclk ratio\n");
333 return -EINVAL;
336 cs42xx8->rate[tx] = params_rate(params);
341 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
351 struct snd_soc_component *component = dai->component;
353 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
356 cs42xx8->rate[tx] = 0;
358 regmap_update_bits(cs42xx8->regmap, CS42XX8_FUNCMOD,
366 struct snd_soc_component *component = dai->component;
368 u8 dac_unmute = cs42xx8->tx_channels ?
369 ~((0x1 << cs42xx8->tx_channels) - 1) : 0;
371 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE,
407 { 0x05, 0x00 }, /* ADC Control & DAC De-Emphasis */
470 switch (cs42xx8->drvdata->num_adcs) {
484 regmap_write(cs42xx8->regmap, CS42XX8_DACMUTE, CS42XX8_DACMUTE_ALL);
526 return -ENOMEM;
530 cs42xx8->regmap = regmap;
532 cs42xx8->drvdata = drvdata;
534 cs42xx8->gpiod_reset = devm_gpiod_get_optional(dev, "reset",
536 if (IS_ERR(cs42xx8->gpiod_reset))
537 return PTR_ERR(cs42xx8->gpiod_reset);
539 gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 0);
541 cs42xx8->clk = devm_clk_get(dev, "mclk");
542 if (IS_ERR(cs42xx8->clk)) {
544 PTR_ERR(cs42xx8->clk));
545 return -EINVAL;
548 cs42xx8->sysclk = clk_get_rate(cs42xx8->clk);
550 for (i = 0; i < ARRAY_SIZE(cs42xx8->supplies); i++)
551 cs42xx8->supplies[i].supply = cs42xx8_supply_names[i];
554 ARRAY_SIZE(cs42xx8->supplies), cs42xx8->supplies);
560 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
561 cs42xx8->supplies);
571 ret = regmap_read(cs42xx8->regmap, CS42XX8_CHIPID, &val);
581 ret = -EINVAL;
588 cs42xx8_dai.name = cs42xx8->drvdata->name;
591 cs42xx8_dai.capture.channels_max = cs42xx8->drvdata->num_adcs * 2;
599 regcache_cache_only(cs42xx8->regmap, true);
602 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
603 cs42xx8->supplies);
614 ret = clk_prepare_enable(cs42xx8->clk);
620 gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 0);
622 ret = regulator_bulk_enable(ARRAY_SIZE(cs42xx8->supplies),
623 cs42xx8->supplies);
632 regcache_cache_only(cs42xx8->regmap, false);
633 regcache_mark_dirty(cs42xx8->regmap);
635 ret = regcache_sync(cs42xx8->regmap);
644 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
645 cs42xx8->supplies);
647 clk_disable_unprepare(cs42xx8->clk);
656 regcache_cache_only(cs42xx8->regmap, true);
658 regulator_bulk_disable(ARRAY_SIZE(cs42xx8->supplies),
659 cs42xx8->supplies);
661 gpiod_set_value_cansleep(cs42xx8->gpiod_reset, 1);
663 clk_disable_unprepare(cs42xx8->clk);