Lines Matching +full:current +full:- +full:limiter
1 // SPDX-License-Identifier: GPL-2.0-only
3 * cs42l52.c -- CS42L52 ALSA SoC audio driver
29 #include <sound/soc-dapm.h>
43 /* MICA mode selection Differential or Single-ended */
46 /* MICB mode selection Differential or Single-ended */
110 { CS42L52_LIMITER_AT_RATE, 0xC0 }, /* r29 Limiter Attack Rate */
147 static DECLARE_TLV_DB_SCALE(hl_tlv, -10200, 50, 0);
149 static DECLARE_TLV_DB_SCALE(hpd_tlv, -9600, 50, 1);
151 static DECLARE_TLV_DB_SCALE(ipd_tlv, -9600, 100, 0);
155 static DECLARE_TLV_DB_SCALE(pga_tlv, -600, 50, 0);
157 static DECLARE_TLV_DB_SCALE(pass_tlv, -6000, 50, 0);
159 static DECLARE_TLV_DB_SCALE(mix_tlv, -5150, 50, 0);
161 static DECLARE_TLV_DB_SCALE(beep_tlv, -56, 200, 0);
164 0, 2, TLV_DB_SCALE_ITEM(-3000, 600, 0),
165 3, 7, TLV_DB_SCALE_ITEM(-1200, 300, 0)
273 "-34dB", "-37dB", "-40dB", "-43dB",
274 "-46dB", "-52dB", "-58dB", "-64dB"
418 /* Limiter */
419 SOC_SINGLE_TLV("Limiter Max Threshold Volume",
421 SOC_SINGLE_TLV("Limiter Cushion Threshold Volume",
423 SOC_SINGLE_TLV("Limiter Release Rate Volume",
425 SOC_SINGLE_TLV("Limiter Attack Rate Volume",
428 SOC_SINGLE("Limiter SR Switch", CS42L52_LIMITER_CTL1, 1, 1, 0),
429 SOC_SINGLE("Limiter ZC Switch", CS42L52_LIMITER_CTL1, 0, 1, 0),
430 SOC_SINGLE("Limiter Switch", CS42L52_LIMITER_CTL2, 7, 1, 0),
494 struct cs42l52_platform_data *pdata = &cs42l52->pdata;
496 if (!pdata->mica_diff_cfg)
500 if (!pdata->micb_diff_cfg)
716 int i, ret = -EINVAL;
722 if (abs(mclk - mclk1) < abs(mclk - mclk2)) {
734 struct snd_soc_component *component = codec_dai->component;
738 cs42l52->sysclk = freq;
740 dev_err(component->dev, "Invalid freq parameter\n");
741 return -EINVAL;
748 struct snd_soc_component *component = codec_dai->component;
760 return -EINVAL;
782 return -EINVAL;
798 return -EINVAL;
800 cs42l52->config.format = iface;
801 snd_soc_component_write(component, CS42L52_IFACE_CTL1, cs42l52->config.format);
808 struct snd_soc_component *component = dai->component;
826 struct snd_soc_component *component = dai->component;
831 index = cs42l52_get_clk(cs42l52->sysclk, params_rate(params));
833 cs42l52->sysclk = clk_map_table[index].mclk;
843 dev_err(component->dev, "can't get correct mclk\n");
844 return -EINVAL;
865 regcache_cache_only(cs42l52->regmap, false);
866 regcache_sync(cs42l52->regmap);
872 regcache_cache_only(cs42l52->regmap, true);
922 struct snd_soc_component *component = cs42l52->component;
928 if (cs42l52->beep_rate) {
930 if (abs(cs42l52->beep_rate - beep_rates[i]) <
931 abs(cs42l52->beep_rate - beep_rates[best]))
935 dev_dbg(component->dev, "Set beep rate %dHz for requested %dHz\n",
936 beep_rates[best], cs42l52->beep_rate);
942 dev_dbg(component->dev, "Disabling beep\n");
952 /* For usability define a way of injecting beep events for the device -
961 dev_dbg(component->dev, "Beep event %x %x\n", code, hz);
971 return -1;
975 cs42l52->beep_rate = hz;
976 schedule_work(&cs42l52->beep_work);
991 input_event(cs42l52->beep, EV_SND, SND_TONE, time);
1003 cs42l52->beep = devm_input_allocate_device(component->dev);
1004 if (!cs42l52->beep) {
1005 dev_err(component->dev, "Failed to allocate beep device\n");
1009 INIT_WORK(&cs42l52->beep_work, cs42l52_beep_work);
1010 cs42l52->beep_rate = 0;
1012 cs42l52->beep->name = "CS42L52 Beep Generator";
1013 cs42l52->beep->phys = dev_name(component->dev);
1014 cs42l52->beep->id.bustype = BUS_I2C;
1016 cs42l52->beep->evbit[0] = BIT_MASK(EV_SND);
1017 cs42l52->beep->sndbit[0] = BIT_MASK(SND_BELL) | BIT_MASK(SND_TONE);
1018 cs42l52->beep->event = cs42l52_beep_event;
1019 cs42l52->beep->dev.parent = component->dev;
1020 input_set_drvdata(cs42l52->beep, component);
1022 ret = input_register_device(cs42l52->beep);
1024 cs42l52->beep = NULL;
1025 dev_err(component->dev, "Failed to register beep device\n");
1028 ret = device_create_file(component->dev, &dev_attr_beep);
1030 dev_err(component->dev, "Failed to create keyclick file: %d\n",
1039 device_remove_file(component->dev, &dev_attr_beep);
1040 cancel_work_sync(&cs42l52->beep_work);
1041 cs42l52->beep = NULL;
1051 regcache_cache_only(cs42l52->regmap, true);
1057 cs42l52->sysclk = CS42L52_DEFAULT_CLK;
1058 cs42l52->config.format = CS42L52_DEFAULT_FORMAT;
1084 /* Current and threshold powerup sequence Pg37 */
1117 cs42l52 = devm_kzalloc(&i2c_client->dev, sizeof(*cs42l52), GFP_KERNEL);
1119 return -ENOMEM;
1120 cs42l52->dev = &i2c_client->dev;
1122 cs42l52->regmap = devm_regmap_init_i2c(i2c_client, &cs42l52_regmap);
1123 if (IS_ERR(cs42l52->regmap)) {
1124 ret = PTR_ERR(cs42l52->regmap);
1125 dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
1129 pdata = devm_kzalloc(&i2c_client->dev, sizeof(*pdata), GFP_KERNEL);
1131 return -ENOMEM;
1133 if (i2c_client->dev.of_node) {
1134 if (of_property_read_bool(i2c_client->dev.of_node,
1135 "cirrus,mica-differential-cfg"))
1136 pdata->mica_diff_cfg = true;
1138 if (of_property_read_bool(i2c_client->dev.of_node,
1139 "cirrus,micb-differential-cfg"))
1140 pdata->micb_diff_cfg = true;
1142 if (of_property_read_u32(i2c_client->dev.of_node,
1143 "cirrus,micbias-lvl", &val32) >= 0)
1144 pdata->micbias_lvl = val32;
1146 if (of_property_read_u32(i2c_client->dev.of_node,
1147 "cirrus,chgfreq-divisor", &val32) >= 0)
1148 pdata->chgfreq = val32;
1150 pdata->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
1154 if (IS_ERR(pdata->reset_gpio))
1155 return PTR_ERR(pdata->reset_gpio);
1157 gpiod_set_consumer_name(pdata->reset_gpio, "CS42L52 /RST");
1160 cs42l52->pdata = *pdata;
1162 if (cs42l52->pdata.reset_gpio) {
1163 gpiod_set_value_cansleep(cs42l52->pdata.reset_gpio, 1);
1164 gpiod_set_value_cansleep(cs42l52->pdata.reset_gpio, 0);
1169 ret = regmap_register_patch(cs42l52->regmap, cs42l52_threshold_patch,
1172 dev_warn(cs42l52->dev, "Failed to apply regmap patch: %d\n",
1175 ret = regmap_read(cs42l52->regmap, CS42L52_CHIP, ®);
1177 dev_err(&i2c_client->dev, "Failed to read chip ID: %d\n", ret);
1183 ret = -ENODEV;
1184 dev_err(&i2c_client->dev,
1190 dev_info(&i2c_client->dev, "Cirrus Logic CS42L52, Revision: %02X\n",
1194 if (cs42l52->pdata.mica_diff_cfg)
1195 regmap_update_bits(cs42l52->regmap, CS42L52_MICA_CTL,
1197 cs42l52->pdata.mica_diff_cfg <<
1200 if (cs42l52->pdata.micb_diff_cfg)
1201 regmap_update_bits(cs42l52->regmap, CS42L52_MICB_CTL,
1203 cs42l52->pdata.micb_diff_cfg <<
1206 if (cs42l52->pdata.chgfreq)
1207 regmap_update_bits(cs42l52->regmap, CS42L52_CHARGE_PUMP,
1209 cs42l52->pdata.chgfreq <<
1212 if (cs42l52->pdata.micbias_lvl)
1213 regmap_update_bits(cs42l52->regmap, CS42L52_IFACE_CTL2,
1215 cs42l52->pdata.micbias_lvl);
1217 return devm_snd_soc_register_component(&i2c_client->dev,