Lines Matching +full:sound +full:- +full:spdif +full:- +full:asrc
1 // SPDX-License-Identifier: GPL-2.0
5 // Copyright (C) 2022-2023 Cirrus Logic, Inc. and
21 #include <linux/mfd/cs42l43-regs.h>
29 #include <sound/control.h>
30 #include <sound/cs42l43.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/soc-component.h>
34 #include <sound/soc-dapm.h>
35 #include <sound/soc-dai.h>
36 #include <sound/soc.h>
37 #include <sound/tlv.h>
83 { name_str, "ASRC INT1", "ASRC_INT1" }, \
84 { name_str, "ASRC INT2", "ASRC_INT2" }, \
85 { name_str, "ASRC INT3", "ASRC_INT3" }, \
86 { name_str, "ASRC INT4", "ASRC_INT4" }, \
87 { name_str, "ASRC DEC1", "ASRC_DEC1" }, \
88 { name_str, "ASRC DEC2", "ASRC_DEC2" }, \
89 { name_str, "ASRC DEC3", "ASRC_DEC3" }, \
90 { name_str, "ASRC DEC4", "ASRC_DEC4" }, \
137 dev_err(priv->dev, "Error " #name " IRQ\n"); \
157 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component);
161 priv->hp_ilimit_count--;
163 if (priv->hp_ilimit_count)
164 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work,
173 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(priv->component);
174 struct cs42l43 *cs42l43 = priv->core;
176 dev_dbg(priv->dev, "headphone ilimit IRQ\n");
180 if (priv->hp_ilimit_count < CS42L43_HP_ILIMIT_MAX_COUNT) {
181 if (!priv->hp_ilimit_count)
182 queue_delayed_work(system_wq, &priv->hp_ilimit_clear_work,
185 priv->hp_ilimit_count++;
190 dev_err(priv->dev, "Disabling headphone for %dmS, due to frequent current limit\n",
193 priv->hp_ilimited = true;
196 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
205 if (priv->hp_ena && !priv->load_detect_running) {
208 reinit_completion(&priv->hp_startup);
210 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
211 CS42L43_HP_EN_MASK, priv->hp_ena);
213 time_left = wait_for_completion_timeout(&priv->hp_startup,
216 dev_err(priv->dev, "ilimit HP restore timed out\n");
219 priv->hp_ilimited = false;
230 dev_dbg(priv->dev, #name " completed\n"); \
231 complete(&priv->name); \
248 struct snd_soc_component *component = priv->component;
251 dev_dbg(priv->dev, "Microphone shutter changed\n");
256 for (i = 1; i < ARRAY_SIZE(priv->kctl); i++) {
257 if (!priv->kctl[i])
260 snd_ctl_notify(component->card->snd_card,
261 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[i]->id);
270 struct snd_soc_component *component = priv->component;
272 dev_dbg(priv->dev, "Speaker shutter changed\n");
277 if (!priv->kctl[0])
280 snd_ctl_notify(component->card->snd_card,
281 SNDRV_CTL_EVENT_MASK_VALUE, &priv->kctl[0]->id);
300 struct snd_soc_component *component = dai->component;
302 struct cs42l43 *cs42l43 = priv->core;
303 int provider = !dai->id || !!regmap_test_bits(cs42l43->regmap,
308 priv->constraint.mask = CS42L43_PROVIDER_RATE_MASK;
310 priv->constraint.mask = CS42L43_CONSUMER_RATE_MASK;
312 return snd_pcm_hw_constraint_list(substream->runtime, 0,
314 &priv->constraint);
337 return -EINVAL;
345 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
346 struct cs42l43 *cs42l43 = priv->core;
351 dev_err(priv->dev, "Failed to convert sample rate: %d\n", ret);
356 regmap_update_bits(cs42l43->regmap, CS42L43_SAMPLE_RATE1,
366 struct cs42l43_codec *priv = snd_soc_component_get_drvdata(dai->component);
367 struct cs42l43 *cs42l43 = priv->core;
368 int dsp_mode = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
370 int provider = !!regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
380 if (priv->n_slots) {
381 n_slots = priv->n_slots;
382 slot_width = priv->slot_width;
386 dev_dbg(priv->dev, "Forcing balanced channels on ASP\n");
400 dev_err(priv->dev, "Can't produce %dHz bclk\n", bclk_target);
401 return -EINVAL;
404 dev_dbg(priv->dev, "bclk %d/%d = %dHz, with %dx%d frame\n",
407 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG1,
411 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL1,
415 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL4,
419 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
421 slots = priv->tx_slots;
424 slots = priv->rx_slots;
436 dev_dbg(priv->dev, "Configure channel %d at slot %d (%d,%d)\n",
439 regmap_update_bits(cs42l43->regmap, reg,
443 ((data_width - 1) << CS42L43_ASP_CH_WIDTH_SHIFT) |
453 struct snd_soc_component *component = dai->component;
456 struct cs42l43 *cs42l43 = priv->core;
457 int provider = regmap_test_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
482 dev_err(priv->dev, "Unsupported DAI format 0x%x\n",
484 return -EINVAL;
498 dev_err(priv->dev, "Unsupported ASP mode 0x%x\n",
500 return -EINVAL;
519 dev_err(priv->dev, "Unsupported invert mode 0x%x\n",
521 return -EINVAL;
524 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CTRL,
527 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_DATA_CTRL,
531 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_CLK_CONFIG2,
535 regmap_update_bits(cs42l43->regmap, CS42L43_ASP_FSYNC_CTRL3,
551 dev_warn(priv->dev, "Too many channels in TDM mask: %lx\n",
564 struct snd_soc_component *component = dai->component;
567 priv->n_slots = slots;
568 priv->slot_width = slot_width;
575 cs42l43_mask_to_slots(priv, tx_mask, priv->tx_slots,
576 ARRAY_SIZE(priv->tx_slots));
577 cs42l43_mask_to_slots(priv, rx_mask, priv->rx_slots,
578 ARRAY_SIZE(priv->rx_slots));
585 struct snd_soc_component *component = dai->component;
596 static_assert(ARRAY_SIZE(controls) == ARRAY_SIZE(priv->kctl));
599 if (priv->kctl[i])
602 priv->kctl[i] = snd_soc_component_get_kcontrol(component, controls[i]);
610 struct snd_soc_component *component = dai->component;
614 for (i = 0; i < ARRAY_SIZE(priv->kctl); i++)
615 priv->kctl[i] = NULL;
657 .name = "cs42l43-asp",
676 .name = "cs42l43-dp1",
688 .name = "cs42l43-dp2",
700 .name = "cs42l43-dp3",
712 .name = "cs42l43-dp4",
724 .name = "cs42l43-dp5",
736 .name = "cs42l43-dp6",
748 .name = "cs42l43-dp7",
761 static const DECLARE_TLV_DB_SCALE(cs42l43_mixer_tlv, -3200, 100, 0);
796 static DECLARE_TLV_DB_SCALE(cs42l43_adc_tlv, -600, 600, 0);
797 static DECLARE_TLV_DB_SCALE(cs42l43_dec_tlv, -6400, 50, 0);
842 static DECLARE_TLV_DB_SCALE(cs42l43_speaker_tlv, -6400, 50, 0);
850 static DECLARE_TLV_DB_SCALE(cs42l43_headphone_tlv, -11450, 50, 1);
877 "ASRC INT1", "ASRC INT2", "ASRC INT3", "ASRC INT4",
878 "ASRC DEC1", "ASRC DEC2", "ASRC DEC3", "ASRC DEC4",
892 0x40, 0x41, 0x42, 0x43, // ASRC INT1, 2, 3, 4
893 0x44, 0x45, 0x46, 0x47, // ASRC DEC1, 2, 3, 4
1011 memcpy(ucontrol->value.integer.value, priv->eq_coeffs, sizeof(priv->eq_coeffs));
1025 memcpy(priv->eq_coeffs, ucontrol->value.integer.value, sizeof(priv->eq_coeffs));
1034 struct cs42l43 *cs42l43 = priv->core;
1036 mutex_lock(&priv->spk_vu_lock);
1038 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1040 regmap_update_bits(cs42l43->regmap, CS42L43_INTP_VOLUME_CTRL1,
1043 mutex_unlock(&priv->spk_vu_lock);
1048 struct cs42l43 *cs42l43 = priv->core;
1052 ret = pm_runtime_resume_and_get(priv->dev);
1054 dev_err(priv->dev, "Failed to resume for shutters: %d\n", ret);
1059 * SHUTTER_CONTROL is a mix of volatile and non-volatile bits, so must
1060 * be cached for the non-volatiles, so drop it from the cache here so
1063 ret = regcache_drop_region(cs42l43->regmap, CS42L43_SHUTTER_CONTROL,
1066 dev_err(priv->dev, "Failed to drop shutter from cache: %d\n", ret);
1070 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
1072 dev_err(priv->dev, "Failed to check shutter status: %d\n", ret);
1078 dev_dbg(priv->dev, "%s shutter is %s\n",
1083 pm_runtime_put_autosuspend(priv->dev);
1099 ucontrol->value.integer.value[0] = ret;
1115 ucontrol->value.integer.value[0] = ret;
1266 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1268 struct cs42l43 *cs42l43 = priv->core;
1274 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1278 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1282 regmap_write(cs42l43->regmap, CS42L43_COEFF_DATA_IN0,
1283 priv->eq_coeffs[i]);
1285 regmap_update_bits(cs42l43->regmap, CS42L43_COEFF_RD_WR0,
1290 ret = regmap_read_poll_timeout(cs42l43->regmap, CS42L43_INIT_DONE0,
1294 dev_err(priv->dev, "Failed to start EQs: %d\n", ret);
1296 regmap_update_bits(cs42l43->regmap, CS42L43_MUTE_EQ_IN0,
1321 struct cs42l43 *cs42l43 = priv->core;
1323 lockdep_assert_held(&cs42l43->pll_lock);
1325 if (priv->refclk_src == src && priv->refclk_freq == freq)
1328 if (regmap_test_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK)) {
1329 dev_err(priv->dev, "PLL active, can't change configuration\n");
1330 return -EBUSY;
1336 dev_dbg(priv->dev, "Source PLL from %s at %uHz\n",
1339 priv->refclk_src = src;
1340 priv->refclk_freq = freq;
1344 dev_err(priv->dev, "Invalid PLL source: 0x%x\n", src);
1345 return -EINVAL;
1355 struct cs42l43 *cs42l43 = priv->core;
1358 unsigned int freq = priv->refclk_freq;
1361 lockdep_assert_held(&cs42l43->pll_lock);
1363 if (priv->refclk_src == CS42L43_SYSCLK_SDW) {
1365 freq = cs42l43->sdw_freq;
1366 else if (!cs42l43->sdw_freq)
1367 cs42l43->sdw_freq = freq;
1370 dev_dbg(priv->dev, "Enabling PLL at %uHz\n", freq);
1372 div = fls(freq) -
1373 fls(cs42l43_pll_configs[ARRAY_SIZE(cs42l43_pll_configs) - 1].freq);
1388 dev_err(priv->dev, "No suitable PLL config: 0x%x, %uHz\n", div, freq);
1389 return -EINVAL;
1392 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1395 priv->refclk_src << CS42L43_PLL_REFCLK_SRC_SHIFT);
1396 regmap_write(cs42l43->regmap, CS42L43_FDIV_FRAC, config->div);
1397 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1400 config->mode << CS42L43_PLL_MODE_BYPASS_1029_SHIFT);
1401 regmap_update_bits(cs42l43->regmap, CS42L43_CAL_RATIO,
1402 CS42L43_PLL_CAL_RATIO_MASK, config->cal);
1403 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1406 reinit_completion(&priv->pll_ready);
1408 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1411 time_left = wait_for_completion_timeout(&priv->pll_ready,
1414 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG,
1416 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1419 dev_err(priv->dev, "Timeout out waiting for PLL\n");
1420 return -ETIMEDOUT;
1423 if (priv->refclk_src == CS42L43_SYSCLK_SDW)
1424 cs42l43->sdw_pll_active = true;
1426 dev_dbg(priv->dev, "PLL locked in %ums\n", 200 - jiffies_to_msecs(time_left));
1433 regmap_multi_reg_write(cs42l43->regmap, enable_seq, ARRAY_SIZE(enable_seq));
1444 struct cs42l43 *cs42l43 = priv->core;
1446 dev_dbg(priv->dev, "Disabling PLL\n");
1448 lockdep_assert_held(&cs42l43->pll_lock);
1450 regmap_multi_reg_write(cs42l43->regmap, disable_seq, ARRAY_SIZE(disable_seq));
1451 regmap_update_bits(cs42l43->regmap, CS42L43_CTRL_REG, CS42L43_PLL_EN_MASK, 0);
1452 regmap_update_bits(cs42l43->regmap, CS42L43_PLL_CONTROL,
1455 cs42l43->sdw_pll_active = false;
1463 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1465 struct cs42l43 *cs42l43 = priv->core;
1468 mutex_lock(&cs42l43->pll_lock);
1472 if (priv->refclk_src == CS42L43_SYSCLK_MCLK) {
1473 ret = clk_prepare_enable(priv->mclk);
1475 dev_err(priv->dev, "Failed to enable MCLK: %d\n", ret);
1485 if (priv->refclk_src == CS42L43_SYSCLK_MCLK)
1486 clk_disable_unprepare(priv->mclk);
1493 mutex_unlock(&cs42l43->pll_lock);
1521 return -ETIMEDOUT;
1529 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1532 return cs42l43_dapm_wait_completion(&priv->spkr_startup,
1533 &priv->spkr_shutdown, event,
1540 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1543 return cs42l43_dapm_wait_completion(&priv->spkl_startup,
1544 &priv->spkl_shutdown, event,
1551 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1553 struct cs42l43 *cs42l43 = priv->core;
1554 unsigned int mask = 1 << w->shift;
1563 priv->hp_ena &= ~mask;
1564 priv->hp_ena |= val;
1566 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1567 &priv->hp_shutdown, event,
1572 if (!priv->load_detect_running && !priv->hp_ilimited)
1573 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN8,
1578 if (priv->load_detect_running || priv->hp_ilimited)
1581 ret = cs42l43_dapm_wait_completion(&priv->hp_startup,
1582 &priv->hp_shutdown, event,
1597 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1599 struct cs42l43 *cs42l43 = priv->core;
1604 switch (w->shift) {
1610 val = &priv->decim_cache[0];
1617 val = &priv->decim_cache[1];
1623 val = &priv->decim_cache[2];
1629 val = &priv->decim_cache[3];
1632 dev_err(priv->dev, "Invalid microphone shift: %d\n", w->shift);
1633 return -EINVAL;
1638 ret = regmap_read(cs42l43->regmap, reg, val);
1640 dev_err(priv->dev,
1646 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, mute);
1649 regmap_update_bits(cs42l43->regmap, reg, mute | ramp, *val);
1661 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1663 struct cs42l43 *cs42l43 = priv->core;
1664 unsigned int mask = 1 << w->shift;
1677 priv->adc_ena &= ~mask;
1678 priv->adc_ena |= val;
1680 if (!priv->load_detect_running)
1681 regmap_update_bits(cs42l43->regmap, CS42L43_BLOCK_EN3,
1789 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-amp", 0, 0),
1803 SND_SOC_DAPM_PGA("SPDIF", CS42L43_BLOCK_EN11, CS42L43_SPDIF_EN_SHIFT,
1892 CS42L43_DAPM_MUX("ASRC INT1", asrcint1),
1893 CS42L43_DAPM_MUX("ASRC INT2", asrcint2),
1894 CS42L43_DAPM_MUX("ASRC INT3", asrcint3),
1895 CS42L43_DAPM_MUX("ASRC INT4", asrcint4),
1896 CS42L43_DAPM_MUX("ASRC DEC1", asrcdec1),
1897 CS42L43_DAPM_MUX("ASRC DEC2", asrcdec2),
1898 CS42L43_DAPM_MUX("ASRC DEC3", asrcdec3),
1899 CS42L43_DAPM_MUX("ASRC DEC4", asrcdec4),
2025 { "AMP1", NULL, "vdd-amp" },
2026 { "AMP2", NULL, "vdd-amp" },
2033 { "SPDIF_TX", NULL, "SPDIF" },
2082 CS42L43_MUX_ROUTES("ASRC INT1", "ASRC_INT1"),
2083 CS42L43_MUX_ROUTES("ASRC INT2", "ASRC_INT2"),
2084 CS42L43_MUX_ROUTES("ASRC INT3", "ASRC_INT3"),
2085 CS42L43_MUX_ROUTES("ASRC INT4", "ASRC_INT4"),
2086 CS42L43_MUX_ROUTES("ASRC DEC1", "ASRC_DEC1"),
2087 CS42L43_MUX_ROUTES("ASRC DEC2", "ASRC_DEC2"),
2088 CS42L43_MUX_ROUTES("ASRC DEC3", "ASRC_DEC3"),
2089 CS42L43_MUX_ROUTES("ASRC DEC4", "ASRC_DEC4"),
2100 CS42L43_MUX_ROUTES("SPDIF1", "SPDIF"),
2101 CS42L43_MUX_ROUTES("SPDIF2", "SPDIF"),
2117 struct cs42l43 *cs42l43 = priv->core;
2120 mutex_lock(&cs42l43->pll_lock);
2122 mutex_unlock(&cs42l43->pll_lock);
2130 struct cs42l43 *cs42l43 = priv->core;
2132 snd_soc_component_init_regmap(component, cs42l43->regmap);
2134 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->tx_slots,
2135 ARRAY_SIZE(priv->tx_slots));
2136 cs42l43_mask_to_slots(priv, CS42L43_DEFAULT_SLOTS, priv->rx_slots,
2137 ARRAY_SIZE(priv->rx_slots));
2139 priv->component = component;
2140 priv->constraint = cs42l43_constraint;
2149 cs42l43_set_jack(priv->component, NULL, NULL);
2151 cancel_delayed_work_sync(&priv->bias_sense_timeout);
2152 cancel_delayed_work_sync(&priv->tip_sense_work);
2154 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work);
2156 priv->component = NULL;
2160 .name = "cs42l43-codec",
2218 ret = irq_create_mapping(priv->dom, irq);
2220 return dev_err_probe(priv->dev, ret, "Failed to map IRQ %s\n", name);
2222 dev_dbg(priv->dev, "Request IRQ %d for %s\n", ret, name);
2224 ret = devm_request_threaded_irq(priv->dev, ret, NULL, handler,
2227 return dev_err_probe(priv->dev, ret, "Failed to request IRQ %s\n", name);
2236 ret = irq_find_mapping(priv->dom, irq);
2245 ret = irq_find_mapping(priv->dom, irq);
2259 dev_warn(priv->dev, "Manual shutters, notifications not available\n");
2286 struct cs42l43 *cs42l43 = dev_get_drvdata(pdev->dev.parent);
2291 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
2293 return -ENOMEM;
2295 priv->dev = &pdev->dev;
2296 priv->core = cs42l43;
2298 priv->dom = irq_find_matching_fwnode(dev_fwnode(cs42l43->dev), DOMAIN_BUS_ANY);
2299 if (!priv->dom)
2300 return -EPROBE_DEFER;
2304 mutex_init(&priv->jack_lock);
2305 mutex_init(&priv->spk_vu_lock);
2307 init_completion(&priv->hp_startup);
2308 init_completion(&priv->hp_shutdown);
2309 init_completion(&priv->spkr_shutdown);
2310 init_completion(&priv->spkl_shutdown);
2311 init_completion(&priv->spkr_startup);
2312 init_completion(&priv->spkl_startup);
2313 init_completion(&priv->pll_ready);
2314 init_completion(&priv->type_detect);
2315 init_completion(&priv->load_detect);
2317 INIT_DELAYED_WORK(&priv->tip_sense_work, cs42l43_tip_sense_work);
2318 INIT_DELAYED_WORK(&priv->bias_sense_timeout, cs42l43_bias_sense_timeout);
2319 INIT_DELAYED_WORK(&priv->hp_ilimit_clear_work, cs42l43_hp_ilimit_clear_work);
2321 pm_runtime_set_autosuspend_delay(priv->dev, 100);
2322 pm_runtime_use_autosuspend(priv->dev);
2323 pm_runtime_set_active(priv->dev);
2324 pm_runtime_get_noresume(priv->dev);
2326 ret = devm_pm_runtime_enable(priv->dev);
2338 ret = regmap_read(cs42l43->regmap, CS42L43_SHUTTER_CONTROL, &val);
2340 dev_err(priv->dev, "Failed to check shutter source: %d\n", ret);
2345 "mic shutter open", &priv->shutter_irqs[0],
2346 "mic shutter close", &priv->shutter_irqs[1],
2353 "spk shutter open", &priv->shutter_irqs[2],
2354 "spk shutter close", &priv->shutter_irqs[3],
2360 priv->mclk = clk_get_optional(cs42l43->dev, "mclk");
2361 if (IS_ERR(priv->mclk)) {
2362 ret = PTR_ERR(priv->mclk);
2363 dev_err_probe(priv->dev, ret, "Failed to get mclk\n");
2367 ret = devm_snd_soc_register_component(priv->dev, &cs42l43_component_drv,
2370 dev_err_probe(priv->dev, ret, "Failed to register component\n");
2374 pm_runtime_put_autosuspend(priv->dev);
2379 clk_put(priv->mclk);
2381 pm_runtime_put_sync(priv->dev);
2390 clk_put(priv->mclk);
2397 dev_dbg(priv->dev, "Runtime resume\n");
2410 dev_dbg(priv->dev, "System suspend\n");
2412 priv->suspend_jack_debounce = true;
2417 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++)
2418 if (priv->shutter_irqs[i])
2419 cs42l43_disable_irq(priv, priv->shutter_irqs[i]);
2421 cancel_delayed_work_sync(&priv->bias_sense_timeout);
2422 cancel_delayed_work_sync(&priv->tip_sense_work);
2423 cancel_delayed_work_sync(&priv->hp_ilimit_clear_work);
2442 for (i = 0; i < ARRAY_SIZE(priv->shutter_irqs); i++)
2443 if (priv->shutter_irqs[i])
2444 cs42l43_enable_irq(priv, priv->shutter_irqs[i]);
2455 { "cs42l43-codec", },
2462 .name = "cs42l43-codec",