Lines Matching +full:8 +full:dev
71 static bool cs35l41_readable_reg(struct device *dev, unsigned int reg) in cs35l41_readable_reg() argument
360 static bool cs35l41_precious_reg(struct device *dev, unsigned int reg) in cs35l41_precious_reg() argument
376 static bool cs35l41_volatile_reg(struct device *dev, unsigned int reg) in cs35l41_volatile_reg() argument
439 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
440 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
441 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
443 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
444 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
445 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
447 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
448 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
449 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
451 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
452 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
453 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
454 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
456 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
462 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
467 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
468 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
469 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
470 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
473 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
477 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
481 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
485 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
489 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
525 { 0x00017040, 0, 8 }, /*X_COORDINATE*/
526 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
527 { 0x00017040, 16, 8 }, /*WAFER_ID*/
528 { 0x00017040, 24, 8 }, /*DVS*/
542 { 0x00003950, 8, 7 }, /*BST_ATRIM_IADC_GAIN1*/
543 { 0x00003950, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
544 { 0x00003950, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
546 { 0x00003954, 8, 7 }, /*BST_ATRIM_IADC_GAIN2*/
547 { 0x00003954, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
548 { 0x00003954, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
550 { 0x00003958, 8, 7 }, /*BST_ATRIM_IADC_GAIN3*/
551 { 0x00003958, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
552 { 0x00003958, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
554 { 0x0000395C, 8, 7 }, /*BST_ATRIM_IADC_GAIN4*/
555 { 0x0000395C, 16, 8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
556 { 0x0000395C, 24, 8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
557 { 0x0000416C, 0, 8 }, /*VMON_GAIN_OTP_VAL*/
559 { 0x0000416C, 8, 8 }, /*IMON_GAIN_OTP_VAL*/
565 { 0x00004170, 8, 6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
570 { 0x00004448, 0, 8 }, /*VP_SARADC_OFFSET*/
571 { 0x00004448, 8, 8 }, /*VP_GAIN_INDEX*/
572 { 0x00004448, 16, 8 }, /*VBST_SARADC_OFFSET*/
573 { 0x00004448, 24, 8 }, /*VBST_GAIN_INDEX*/
576 { 0x00006E30, 8, 5 }, /*GAIN_ERR_COEFF_1*/
580 { 0x00006E34, 8, 5 }, /*GAIN_ERR_COEFF_5*/
584 { 0x00006E38, 8, 5 }, /*GAIN_ERR_COEFF_9*/
588 { 0x00006E3C, 8, 5 }, /*GAIN_ERR_COEFF_13*/
592 { 0x00006E40, 8, 5 }, /*GAIN_ERR_COEFF_17*/
628 { 0x00017040, 0, 8 }, /*X_COORDINATE*/
629 { 0x00017040, 8, 8 }, /*Y_COORDINATE*/
630 { 0x00017040, 16, 8 }, /*WAFER_ID*/
631 { 0x00017040, 24, 8 }, /*DVS*/
782 int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap) in cs35l41_test_key_unlock() argument
792 dev_err(dev, "Failed to unlock test key: %d\n", ret); in cs35l41_test_key_unlock()
798 int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap) in cs35l41_test_key_lock() argument
808 dev_err(dev, "Failed to lock test key: %d\n", ret); in cs35l41_test_key_lock()
815 int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap) in cs35l41_otp_unpack() argument
820 unsigned int bit_sum = 8; in cs35l41_otp_unpack()
830 dev_err(dev, "Read OTP ID failed: %d\n", ret); in cs35l41_otp_unpack()
837 dev_err(dev, "OTP Map matching ID %d not found\n", otp_id_reg); in cs35l41_otp_unpack()
844 dev_err(dev, "Read OTP Mem failed: %d\n", ret); in cs35l41_otp_unpack()
854 dev_dbg(dev, "bitoffset= %d, word_offset=%d, bit_sum mod 32=%d, otp_map[i].size = %u\n", in cs35l41_otp_unpack()
884 dev_err(dev, "Write OTP val failed: %d\n", ret); in cs35l41_otp_unpack()
900 int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid) in cs35l41_register_errata_patch() argument
928 dev_err(dev, "Failed to apply %s errata patch: %d\n", rev, ret); in cs35l41_register_errata_patch()
932 dev_err(dev, "Write CCM_CORE_CTRL failed: %d\n", ret); in cs35l41_register_errata_patch()
938 int cs35l41_set_channels(struct device *dev, struct regmap *reg, in cs35l41_set_channels() argument
951 dev_dbg(dev, "rx slot %d position = %d\n", i, rx_slot[i]); in cs35l41_set_channels()
952 val |= rx_slot[i] << (i * 8); in cs35l41_set_channels()
953 mask |= 0x3F << (i * 8); in cs35l41_set_channels()
960 dev_dbg(dev, "tx slot %d position = %d\n", i, tx_slot[i]); in cs35l41_set_channels()
961 val |= tx_slot[i] << (i * 8); in cs35l41_set_channels()
962 mask |= 0x3F << (i * 8); in cs35l41_set_channels()
988 static int cs35l41_boost_config(struct device *dev, struct regmap *regmap, int boost_ind, in cs35l41_boost_config() argument
1008 dev_err(dev, "Invalid boost inductor value: %d nH\n", boost_ind); in cs35l41_boost_config()
1027 dev_err(dev, "Invalid boost capacitor value: %d nH\n", boost_cap); in cs35l41_boost_config()
1035 dev_err(dev, "Invalid boost inductor peak current: %d mA\n", boost_ipk); in cs35l41_boost_config()
1046 dev_err(dev, "Failed to write boost coefficients: %d\n", ret); in cs35l41_boost_config()
1056 dev_err(dev, "Failed to write boost slope/inductor value: %d\n", ret); in cs35l41_boost_config()
1065 dev_err(dev, "Failed to write boost inductor peak current: %d\n", ret); in cs35l41_boost_config()
1140 int cs35l41_init_boost(struct device *dev, struct regmap *regmap, in cs35l41_init_boost() argument
1150 ret = cs35l41_boost_config(dev, regmap, hw_cfg->bst_ind, in cs35l41_init_boost()
1153 dev_err(dev, "Error in Boost DT config: %d\n", ret); in cs35l41_init_boost()
1172 dev_err(dev, "Boost type %d not supported\n", hw_cfg->bst_type); in cs35l41_init_boost()
1218 int cs35l41_global_enable(struct device *dev, struct regmap *regmap, enum cs35l41_boost_type b_type, in cs35l41_global_enable() argument
1237 dev_dbg(dev, "Cannot set Global Enable - already set.\n"); in cs35l41_global_enable()
1240 dev_dbg(dev, "Cannot unset Global Enable - not set.\n"); in cs35l41_global_enable()
1273 dev_err(dev, "Enable(%d) failed: %d\n", enable, ret); in cs35l41_global_enable()
1282 dev_err(dev, "CS35L41_PWR_CTRL1 set failed: %d\n", ret); in cs35l41_global_enable()
1290 dev_err(dev, "Enable(%d) failed: %d\n", enable, ret); in cs35l41_global_enable()
1307 dev_err(dev, "Failed waiting for CS35L41_PUP_DONE_MASK: %d\n", ret); in cs35l41_global_enable()
1309 cs35l41_test_key_lock(dev, regmap); in cs35l41_global_enable()
1315 ret = cs35l41_set_cspl_mbox_cmd(dev, regmap, in cs35l41_global_enable()
1322 cs35l41_test_key_lock(dev, regmap); in cs35l41_global_enable()
1329 cs35l41_test_key_lock(dev, regmap); in cs35l41_global_enable()
1336 dev_err(dev, "Failed waiting for CS35L41_PDN_DONE_MASK: %d\n", ret); in cs35l41_global_enable()
1338 cs35l41_test_key_lock(dev, regmap); in cs35l41_global_enable()
1417 void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp) in cs35l41_configure_cs_dsp() argument
1422 dsp->dev = dev; in cs35l41_configure_cs_dsp()
1455 int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap, in cs35l41_set_cspl_mbox_cmd() argument
1465 dev_err(dev, "Failed to write MBOX: %d\n", ret); in cs35l41_set_cspl_mbox_cmd()
1475 dev_err(dev, "Failed to read MBOX STS: %d\n", ret); in cs35l41_set_cspl_mbox_cmd()
1480 dev_err(dev, "CSPL Error Detected\n"); in cs35l41_set_cspl_mbox_cmd()
1485 dev_dbg(dev, "[%u] cmd %u returned invalid sts %u", i, cmd, sts); in cs35l41_set_cspl_mbox_cmd()
1491 dev_err(dev, "Failed to set mailbox cmd %u (status %u)\n", cmd, sts); in cs35l41_set_cspl_mbox_cmd()
1497 int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap) in cs35l41_write_fs_errata() argument
1504 dev_err(dev, "Failed to write fs errata: %d\n", ret); in cs35l41_write_fs_errata()
1510 int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap, in cs35l41_enter_hibernate() argument
1514 dev_dbg(dev, "System does not support Suspend\n"); in cs35l41_enter_hibernate()
1518 dev_dbg(dev, "Enter hibernate\n"); in cs35l41_enter_hibernate()
1529 static void cs35l41_wait_for_pwrmgt_sts(struct device *dev, struct regmap *regmap) in cs35l41_wait_for_pwrmgt_sts() argument
1538 dev_err(dev, "Failed to read PWRMGT_STS: %d\n", ret); in cs35l41_wait_for_pwrmgt_sts()
1545 dev_err(dev, "Timed out reading PWRMGT_STS\n"); in cs35l41_wait_for_pwrmgt_sts()
1548 int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap) in cs35l41_exit_hibernate() argument
1555 dev_dbg(dev, "Exit hibernate\n"); in cs35l41_exit_hibernate()
1558 ret = cs35l41_set_cspl_mbox_cmd(dev, regmap, in cs35l41_exit_hibernate()
1567 dev_dbg(dev, "Wake success at cycle: %d\n", j); in cs35l41_exit_hibernate()
1571 dev_err(dev, "Wake failed, re-enter hibernate: %d\n", ret); in cs35l41_exit_hibernate()
1573 cs35l41_wait_for_pwrmgt_sts(dev, regmap); in cs35l41_exit_hibernate()
1576 cs35l41_wait_for_pwrmgt_sts(dev, regmap); in cs35l41_exit_hibernate()
1579 cs35l41_wait_for_pwrmgt_sts(dev, regmap); in cs35l41_exit_hibernate()
1583 dev_err(dev, "Timed out waking device\n"); in cs35l41_exit_hibernate()