19 #define CS35L41_FIRMWARE_OLD_VERSION 0x001C00 /* v0.28.0 */
22 	{ CS35L41_PWR_CTRL1,			0x00000000 },
23 	{ CS35L41_PWR_CTRL2,			0x00000000 },
24 	{ CS35L41_PWR_CTRL3,			0x01000010 },
25 	{ CS35L41_GPIO_PAD_CONTROL,		0x00000000 },
26 	{ CS35L41_GLOBAL_CLK_CTRL,		0x00000003 },
27 	{ CS35L41_TST_FS_MON0,			0x00020016 },
28 	{ CS35L41_BSTCVRT_COEFF,		0x00002424 },
29 	{ CS35L41_BSTCVRT_SLOPE_LBST,		0x00007500 },
30 	{ CS35L41_BSTCVRT_PEAK_CUR,		0x0000004A },
31 	{ CS35L41_SP_ENABLES,			0x00000000 },
32 	{ CS35L41_SP_RATE_CTRL,			0x00000028 },
33 	{ CS35L41_SP_FORMAT,			0x18180200 },
34 	{ CS35L41_SP_HIZ_CTRL,			0x00000002 },
35 	{ CS35L41_SP_FRAME_TX_SLOT,		0x03020100 },
36 	{ CS35L41_SP_FRAME_RX_SLOT,		0x00000100 },
37 	{ CS35L41_SP_TX_WL,			0x00000018 },
38 	{ CS35L41_SP_RX_WL,			0x00000018 },
39 	{ CS35L41_DAC_PCM1_SRC,			0x00000008 },
40 	{ CS35L41_ASP_TX1_SRC,			0x00000018 },
41 	{ CS35L41_ASP_TX2_SRC,			0x00000019 },
42 	{ CS35L41_ASP_TX3_SRC,			0x00000000 },
43 	{ CS35L41_ASP_TX4_SRC,			0x00000000 },
44 	{ CS35L41_DSP1_RX1_SRC,			0x00000008 },
45 	{ CS35L41_DSP1_RX2_SRC,			0x00000009 },
46 	{ CS35L41_DSP1_RX3_SRC,			0x00000018 },
47 	{ CS35L41_DSP1_RX4_SRC,			0x00000019 },
48 	{ CS35L41_DSP1_RX5_SRC,			0x00000020 },
49 	{ CS35L41_DSP1_RX6_SRC,			0x00000021 },
50 	{ CS35L41_DSP1_RX7_SRC,			0x0000003A },
51 	{ CS35L41_DSP1_RX8_SRC,			0x0000003B },
52 	{ CS35L41_NGATE1_SRC,			0x00000008 },
53 	{ CS35L41_NGATE2_SRC,			0x00000009 },
54 	{ CS35L41_AMP_DIG_VOL_CTRL,		0x00008000 },
55 	{ CS35L41_CLASSH_CFG,			0x000B0405 },
56 	{ CS35L41_WKFET_CFG,			0x00000111 },
57 	{ CS35L41_NG_CFG,			0x00000033 },
58 	{ CS35L41_AMP_GAIN_CTRL,		0x00000000 },
59 	{ CS35L41_IRQ1_MASK1,			0xFFFFFFFF },
60 	{ CS35L41_IRQ1_MASK2,			0xFFFFFFFF },
61 	{ CS35L41_IRQ1_MASK3,			0xFFFF87FF },
62 	{ CS35L41_IRQ1_MASK4,			0xFEFFFFFF },
63 	{ CS35L41_GPIO1_CTRL1,			0x81000001 },
64 	{ CS35L41_GPIO2_CTRL1,			0x81000001 },
65 	{ CS35L41_MIXER_NGATE_CFG,		0x00000000 },
66 	{ CS35L41_MIXER_NGATE_CH1_CFG,		0x00000303 },
67 	{ CS35L41_MIXER_NGATE_CH2_CFG,		0x00000303 },
68 	{ CS35L41_DSP1_CCM_CORE_CTRL,		0x00000101 },
431 	{ 0x00002030,	0,	4 }, /*TRIM_OSC_FREQ_TRIM*/
432 	{ 0x00002030,	7,	1 }, /*TRIM_OSC_TRIM_DONE*/
433 	{ 0x0000208c,	24,	6 }, /*TST_DIGREG_VREF_TRIM*/
434 	{ 0x00002090,	14,	4 }, /*TST_REF_TRIM*/
435 	{ 0x00002090,	10,	4 }, /*TST_REF_TEMPCO_TRIM*/
436 	{ 0x0000300C,	11,	4 }, /*PLL_LDOA_TST_VREF_TRIM*/
437 	{ 0x0000394C,	23,	2 }, /*BST_ATEST_CM_VOFF*/
438 	{ 0x00003950,	0,	7 }, /*BST_ATRIM_IADC_OFFSET*/
439 	{ 0x00003950,	8,	7 }, /*BST_ATRIM_IADC_GAIN1*/
440 	{ 0x00003950,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
441 	{ 0x00003950,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
442 	{ 0x00003954,	0,	7 }, /*BST_ATRIM_IADC_OFFSET2*/
443 	{ 0x00003954,	8,	7 }, /*BST_ATRIM_IADC_GAIN2*/
444 	{ 0x00003954,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
445 	{ 0x00003954,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
446 	{ 0x00003958,	0,	7 }, /*BST_ATRIM_IADC_OFFSET3*/
447 	{ 0x00003958,	8,	7 }, /*BST_ATRIM_IADC_GAIN3*/
448 	{ 0x00003958,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
449 	{ 0x00003958,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
450 	{ 0x0000395C,	0,	7 }, /*BST_ATRIM_IADC_OFFSET4*/
451 	{ 0x0000395C,	8,	7 }, /*BST_ATRIM_IADC_GAIN4*/
452 	{ 0x0000395C,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
453 	{ 0x0000395C,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
454 	{ 0x0000416C,	0,	8 }, /*VMON_GAIN_OTP_VAL*/
455 	{ 0x00004160,	0,	7 }, /*VMON_OFFSET_OTP_VAL*/
456 	{ 0x0000416C,	8,	8 }, /*IMON_GAIN_OTP_VAL*/
457 	{ 0x00004160,	16,	10 }, /*IMON_OFFSET_OTP_VAL*/
458 	{ 0x0000416C,	16,	12 }, /*VMON_CM_GAIN_OTP_VAL*/
459 	{ 0x0000416C,	28,	1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
460 	{ 0x00004170,	0,	6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
461 	{ 0x00004170,	6,	1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
462 	{ 0x00004170,	8,	6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
463 	{ 0x00004170,	14,	1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
464 	{ 0x00004170,	16,	9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
465 	{ 0x00004360,	0,	5 }, /*TEMP_GAIN_OTP_VAL*/
466 	{ 0x00004360,	6,	9 }, /*TEMP_OFFSET_OTP_VAL*/
467 	{ 0x00004448,	0,	8 }, /*VP_SARADC_OFFSET*/
468 	{ 0x00004448,	8,	8 }, /*VP_GAIN_INDEX*/
469 	{ 0x00004448,	16,	8 }, /*VBST_SARADC_OFFSET*/
470 	{ 0x00004448,	24,	8 }, /*VBST_GAIN_INDEX*/
471 	{ 0x0000444C,	0,	3 }, /*ANA_SELINVREF*/
472 	{ 0x00006E30,	0,	5 }, /*GAIN_ERR_COEFF_0*/
473 	{ 0x00006E30,	8,	5 }, /*GAIN_ERR_COEFF_1*/
474 	{ 0x00006E30,	16,	5 }, /*GAIN_ERR_COEFF_2*/
475 	{ 0x00006E30,	24,	5 }, /*GAIN_ERR_COEFF_3*/
476 	{ 0x00006E34,	0,	5 }, /*GAIN_ERR_COEFF_4*/
477 	{ 0x00006E34,	8,	5 }, /*GAIN_ERR_COEFF_5*/
478 	{ 0x00006E34,	16,	5 }, /*GAIN_ERR_COEFF_6*/
479 	{ 0x00006E34,	24,	5 }, /*GAIN_ERR_COEFF_7*/
480 	{ 0x00006E38,	0,	5 }, /*GAIN_ERR_COEFF_8*/
481 	{ 0x00006E38,	8,	5 }, /*GAIN_ERR_COEFF_9*/
482 	{ 0x00006E38,	16,	5 }, /*GAIN_ERR_COEFF_10*/
483 	{ 0x00006E38,	24,	5 }, /*GAIN_ERR_COEFF_11*/
484 	{ 0x00006E3C,	0,	5 }, /*GAIN_ERR_COEFF_12*/
485 	{ 0x00006E3C,	8,	5 }, /*GAIN_ERR_COEFF_13*/
486 	{ 0x00006E3C,	16,	5 }, /*GAIN_ERR_COEFF_14*/
487 	{ 0x00006E3C,	24,	5 }, /*GAIN_ERR_COEFF_15*/
488 	{ 0x00006E40,	0,	5 }, /*GAIN_ERR_COEFF_16*/
489 	{ 0x00006E40,	8,	5 }, /*GAIN_ERR_COEFF_17*/
490 	{ 0x00006E40,	16,	5 }, /*GAIN_ERR_COEFF_18*/
491 	{ 0x00006E40,	24,	5 }, /*GAIN_ERR_COEFF_19*/
492 	{ 0x00006E44,	0,	5 }, /*GAIN_ERR_COEFF_20*/
493 	{ 0x00006E48,	0,	10 }, /*VOFF_GAIN_0*/
494 	{ 0x00006E48,	10,	10 }, /*VOFF_GAIN_1*/
495 	{ 0x00006E48,	20,	10 }, /*VOFF_GAIN_2*/
496 	{ 0x00006E4C,	0,	10 }, /*VOFF_GAIN_3*/
497 	{ 0x00006E4C,	10,	10 }, /*VOFF_GAIN_4*/
498 	{ 0x00006E4C,	20,	10 }, /*VOFF_GAIN_5*/
499 	{ 0x00006E50,	0,	10 }, /*VOFF_GAIN_6*/
500 	{ 0x00006E50,	10,	10 }, /*VOFF_GAIN_7*/
501 	{ 0x00006E50,	20,	10 }, /*VOFF_GAIN_8*/
502 	{ 0x00006E54,	0,	10 }, /*VOFF_GAIN_9*/
503 	{ 0x00006E54,	10,	10 }, /*VOFF_GAIN_10*/
504 	{ 0x00006E54,	20,	10 }, /*VOFF_GAIN_11*/
505 	{ 0x00006E58,	0,	10 }, /*VOFF_GAIN_12*/
506 	{ 0x00006E58,	10,	10 }, /*VOFF_GAIN_13*/
507 	{ 0x00006E58,	20,	10 }, /*VOFF_GAIN_14*/
508 	{ 0x00006E5C,	0,	10 }, /*VOFF_GAIN_15*/
509 	{ 0x00006E5C,	10,	10 }, /*VOFF_GAIN_16*/
510 	{ 0x00006E5C,	20,	10 }, /*VOFF_GAIN_17*/
511 	{ 0x00006E60,	0,	10 }, /*VOFF_GAIN_18*/
512 	{ 0x00006E60,	10,	10 }, /*VOFF_GAIN_19*/
513 	{ 0x00006E60,	20,	10 }, /*VOFF_GAIN_20*/
514 	{ 0x00006E64,	0,	10 }, /*VOFF_INT1*/
515 	{ 0x00007418,	7,	5 }, /*DS_SPK_INT1_CAP_TRIM*/
516 	{ 0x0000741C,	0,	5 }, /*DS_SPK_INT2_CAP_TRIM*/
517 	{ 0x0000741C,	11,	4 }, /*DS_SPK_LPF_CAP_TRIM*/
518 	{ 0x0000741C,	19,	4 }, /*DS_SPK_QUAN_CAP_TRIM*/
519 	{ 0x00007434,	17,	1 }, /*FORCE_CAL*/
520 	{ 0x00007434,	18,	7 }, /*CAL_OVERRIDE*/
521 	{ 0x00007068,	0,	9 }, /*MODIX*/
522 	{ 0x0000410C,	7,	1 }, /*VIMON_DLY_NOT_COMB*/
523 	{ 0x0000400C,	0,	7 }, /*VIMON_DLY*/
524 	{ 0x00000000,	0,	1 }, /*extra bit*/
525 	{ 0x00017040,	0,	8 }, /*X_COORDINATE*/
526 	{ 0x00017040,	8,	8 }, /*Y_COORDINATE*/
527 	{ 0x00017040,	16,	8 }, /*WAFER_ID*/
528 	{ 0x00017040,	24,	8 }, /*DVS*/
529 	{ 0x00017044,	0,	24 }, /*LOT_NUMBER*/
534 	{ 0x00002030,	0,	4 }, /*TRIM_OSC_FREQ_TRIM*/
535 	{ 0x00002030,	7,	1 }, /*TRIM_OSC_TRIM_DONE*/
536 	{ 0x0000208c,	24,	6 }, /*TST_DIGREG_VREF_TRIM*/
537 	{ 0x00002090,	14,	4 }, /*TST_REF_TRIM*/
538 	{ 0x00002090,	10,	4 }, /*TST_REF_TEMPCO_TRIM*/
539 	{ 0x0000300C,	11,	4 }, /*PLL_LDOA_TST_VREF_TRIM*/
540 	{ 0x0000394C,	23,	2 }, /*BST_ATEST_CM_VOFF*/
541 	{ 0x00003950,	0,	7 }, /*BST_ATRIM_IADC_OFFSET*/
542 	{ 0x00003950,	8,	7 }, /*BST_ATRIM_IADC_GAIN1*/
543 	{ 0x00003950,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET1*/
544 	{ 0x00003950,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN1*/
545 	{ 0x00003954,	0,	7 }, /*BST_ATRIM_IADC_OFFSET2*/
546 	{ 0x00003954,	8,	7 }, /*BST_ATRIM_IADC_GAIN2*/
547 	{ 0x00003954,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET2*/
548 	{ 0x00003954,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN2*/
549 	{ 0x00003958,	0,	7 }, /*BST_ATRIM_IADC_OFFSET3*/
550 	{ 0x00003958,	8,	7 }, /*BST_ATRIM_IADC_GAIN3*/
551 	{ 0x00003958,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET3*/
552 	{ 0x00003958,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN3*/
553 	{ 0x0000395C,	0,	7 }, /*BST_ATRIM_IADC_OFFSET4*/
554 	{ 0x0000395C,	8,	7 }, /*BST_ATRIM_IADC_GAIN4*/
555 	{ 0x0000395C,	16,	8 }, /*BST_ATRIM_IPKCOMP_OFFSET4*/
556 	{ 0x0000395C,	24,	8 }, /*BST_ATRIM_IPKCOMP_GAIN4*/
557 	{ 0x0000416C,	0,	8 }, /*VMON_GAIN_OTP_VAL*/
558 	{ 0x00004160,	0,	7 }, /*VMON_OFFSET_OTP_VAL*/
559 	{ 0x0000416C,	8,	8 }, /*IMON_GAIN_OTP_VAL*/
560 	{ 0x00004160,	16,	10 }, /*IMON_OFFSET_OTP_VAL*/
561 	{ 0x0000416C,	16,	12 }, /*VMON_CM_GAIN_OTP_VAL*/
562 	{ 0x0000416C,	28,	1 }, /*VMON_CM_GAIN_SIGN_OTP_VAL*/
563 	{ 0x00004170,	0,	6 }, /*IMON_CAL_TEMPCO_OTP_VAL*/
564 	{ 0x00004170,	6,	1 }, /*IMON_CAL_TEMPCO_SIGN_OTP*/
565 	{ 0x00004170,	8,	6 }, /*IMON_CAL_TEMPCO2_OTP_VAL*/
566 	{ 0x00004170,	14,	1 }, /*IMON_CAL_TEMPCO2_DN_UPB_OTP_VAL*/
567 	{ 0x00004170,	16,	9 }, /*IMON_CAL_TEMPCO_TBASE_OTP_VAL*/
568 	{ 0x00004360,	0,	5 }, /*TEMP_GAIN_OTP_VAL*/
569 	{ 0x00004360,	6,	9 }, /*TEMP_OFFSET_OTP_VAL*/
570 	{ 0x00004448,	0,	8 }, /*VP_SARADC_OFFSET*/
571 	{ 0x00004448,	8,	8 }, /*VP_GAIN_INDEX*/
572 	{ 0x00004448,	16,	8 }, /*VBST_SARADC_OFFSET*/
573 	{ 0x00004448,	24,	8 }, /*VBST_GAIN_INDEX*/
574 	{ 0x0000444C,	0,	3 }, /*ANA_SELINVREF*/
575 	{ 0x00006E30,	0,	5 }, /*GAIN_ERR_COEFF_0*/
576 	{ 0x00006E30,	8,	5 }, /*GAIN_ERR_COEFF_1*/
577 	{ 0x00006E30,	16,	5 }, /*GAIN_ERR_COEFF_2*/
578 	{ 0x00006E30,	24,	5 }, /*GAIN_ERR_COEFF_3*/
579 	{ 0x00006E34,	0,	5 }, /*GAIN_ERR_COEFF_4*/
580 	{ 0x00006E34,	8,	5 }, /*GAIN_ERR_COEFF_5*/
581 	{ 0x00006E34,	16,	5 }, /*GAIN_ERR_COEFF_6*/
582 	{ 0x00006E34,	24,	5 }, /*GAIN_ERR_COEFF_7*/
583 	{ 0x00006E38,	0,	5 }, /*GAIN_ERR_COEFF_8*/
584 	{ 0x00006E38,	8,	5 }, /*GAIN_ERR_COEFF_9*/
585 	{ 0x00006E38,	16,	5 }, /*GAIN_ERR_COEFF_10*/
586 	{ 0x00006E38,	24,	5 }, /*GAIN_ERR_COEFF_11*/
587 	{ 0x00006E3C,	0,	5 }, /*GAIN_ERR_COEFF_12*/
588 	{ 0x00006E3C,	8,	5 }, /*GAIN_ERR_COEFF_13*/
589 	{ 0x00006E3C,	16,	5 }, /*GAIN_ERR_COEFF_14*/
590 	{ 0x00006E3C,	24,	5 }, /*GAIN_ERR_COEFF_15*/
591 	{ 0x00006E40,	0,	5 }, /*GAIN_ERR_COEFF_16*/
592 	{ 0x00006E40,	8,	5 }, /*GAIN_ERR_COEFF_17*/
593 	{ 0x00006E40,	16,	5 }, /*GAIN_ERR_COEFF_18*/
594 	{ 0x00006E40,	24,	5 }, /*GAIN_ERR_COEFF_19*/
595 	{ 0x00006E44,	0,	5 }, /*GAIN_ERR_COEFF_20*/
596 	{ 0x00006E48,	0,	10 }, /*VOFF_GAIN_0*/
597 	{ 0x00006E48,	10,	10 }, /*VOFF_GAIN_1*/
598 	{ 0x00006E48,	20,	10 }, /*VOFF_GAIN_2*/
599 	{ 0x00006E4C,	0,	10 }, /*VOFF_GAIN_3*/
600 	{ 0x00006E4C,	10,	10 }, /*VOFF_GAIN_4*/
601 	{ 0x00006E4C,	20,	10 }, /*VOFF_GAIN_5*/
602 	{ 0x00006E50,	0,	10 }, /*VOFF_GAIN_6*/
603 	{ 0x00006E50,	10,	10 }, /*VOFF_GAIN_7*/
604 	{ 0x00006E50,	20,	10 }, /*VOFF_GAIN_8*/
605 	{ 0x00006E54,	0,	10 }, /*VOFF_GAIN_9*/
606 	{ 0x00006E54,	10,	10 }, /*VOFF_GAIN_10*/
607 	{ 0x00006E54,	20,	10 }, /*VOFF_GAIN_11*/
608 	{ 0x00006E58,	0,	10 }, /*VOFF_GAIN_12*/
609 	{ 0x00006E58,	10,	10 }, /*VOFF_GAIN_13*/
610 	{ 0x00006E58,	20,	10 }, /*VOFF_GAIN_14*/
611 	{ 0x00006E5C,	0,	10 }, /*VOFF_GAIN_15*/
612 	{ 0x00006E5C,	10,	10 }, /*VOFF_GAIN_16*/
613 	{ 0x00006E5C,	20,	10 }, /*VOFF_GAIN_17*/
614 	{ 0x00006E60,	0,	10 }, /*VOFF_GAIN_18*/
615 	{ 0x00006E60,	10,	10 }, /*VOFF_GAIN_19*/
616 	{ 0x00006E60,	20,	10 }, /*VOFF_GAIN_20*/
617 	{ 0x00006E64,	0,	10 }, /*VOFF_INT1*/
618 	{ 0x00007418,	7,	5 }, /*DS_SPK_INT1_CAP_TRIM*/
619 	{ 0x0000741C,	0,	5 }, /*DS_SPK_INT2_CAP_TRIM*/
620 	{ 0x0000741C,	11,	4 }, /*DS_SPK_LPF_CAP_TRIM*/
621 	{ 0x0000741C,	19,	4 }, /*DS_SPK_QUAN_CAP_TRIM*/
622 	{ 0x00007434,	17,	1 }, /*FORCE_CAL*/
623 	{ 0x00007434,	18,	7 }, /*CAL_OVERRIDE*/
624 	{ 0x00007068,	0,	9 }, /*MODIX*/
625 	{ 0x0000410C,	7,	1 }, /*VIMON_DLY_NOT_COMB*/
626 	{ 0x0000400C,	0,	7 }, /*VIMON_DLY*/
627 	{ 0x00004000,	11,	1 }, /*VMON_POL*/
628 	{ 0x00017040,	0,	8 }, /*X_COORDINATE*/
629 	{ 0x00017040,	8,	8 }, /*Y_COORDINATE*/
630 	{ 0x00017040,	16,	8 }, /*WAFER_ID*/
631 	{ 0x00017040,	24,	8 }, /*DVS*/
632 	{ 0x00017044,	0,	24 }, /*LOT_NUMBER*/
636 	{ 0x00003854,			 0x05180240 },
637 	{ CS35L41_VIMON_SPKMON_RESYNC,	 0x00000000 },
638 	{ 0x00004310,			 0x00000000 },
639 	{ CS35L41_VPVBST_FS_SEL,	 0x00000000 },
640 	{ CS35L41_OTP_TRIM_30,		 0x9091A1C8 },
641 	{ 0x00003014,			 0x0200EE0E },
642 	{ CS35L41_BSTCVRT_DCM_CTRL,	 0x00000051 },
643 	{ 0x00000054,			 0x00000004 },
644 	{ CS35L41_IRQ1_DB3,		 0x00000000 },
645 	{ CS35L41_IRQ2_DB3,		 0x00000000 },
646 	{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
647 	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
648 	{ CS35L41_PWR_CTRL2,		 0x00000000 },
649 	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
650 	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
651 	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
655 	{ CS35L41_VIMON_SPKMON_RESYNC,	 0x00000000 },
656 	{ 0x00004310,			 0x00000000 },
657 	{ CS35L41_VPVBST_FS_SEL,	 0x00000000 },
658 	{ CS35L41_BSTCVRT_DCM_CTRL,	 0x00000051 },
659 	{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
660 	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
661 	{ CS35L41_PWR_CTRL2,		 0x00000000 },
662 	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
663 	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
664 	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
668 	{ CS35L41_VIMON_SPKMON_RESYNC,	 0x00000000 },
669 	{ 0x00004310,			 0x00000000 },
670 	{ CS35L41_VPVBST_FS_SEL,	 0x00000000 },
671 	{ CS35L41_BSTCVRT_DCM_CTRL,	 0x00000051 },
672 	{ CS35L41_DSP1_YM_ACCEL_PL0_PRI, 0x00000000 },
673 	{ CS35L41_DSP1_XM_ACCEL_PL0_PRI, 0x00000000 },
674 	{ CS35L41_PWR_CTRL2,		 0x00000000 },
675 	{ CS35L41_AMP_GAIN_CTRL,	 0x00000000 },
676 	{ CS35L41_ASP_TX3_SRC,		 0x00000000 },
677 	{ CS35L41_ASP_TX4_SRC,		 0x00000000 },
681 	{ CS35L41_DSP1_RX1_RATE,	0x00000001 },
682 	{ CS35L41_DSP1_RX2_RATE,	0x00000001 },
683 	{ CS35L41_DSP1_RX3_RATE,	0x00000001 },
684 	{ CS35L41_DSP1_RX4_RATE,	0x00000001 },
685 	{ CS35L41_DSP1_RX5_RATE,	0x00000001 },
686 	{ CS35L41_DSP1_RX6_RATE,	0x00000001 },
687 	{ CS35L41_DSP1_RX7_RATE,	0x00000001 },
688 	{ CS35L41_DSP1_RX8_RATE,	0x00000001 },
689 	{ CS35L41_DSP1_TX1_RATE,	0x00000001 },
690 	{ CS35L41_DSP1_TX2_RATE,	0x00000001 },
691 	{ CS35L41_DSP1_TX3_RATE,	0x00000001 },
692 	{ CS35L41_DSP1_TX4_RATE,	0x00000001 },
693 	{ CS35L41_DSP1_TX5_RATE,	0x00000001 },
694 	{ CS35L41_DSP1_TX6_RATE,	0x00000001 },
695 	{ CS35L41_DSP1_TX7_RATE,	0x00000001 },
696 	{ CS35L41_DSP1_TX8_RATE,	0x00000001 },
701 		.id = 0x01,
708 		.id = 0x02,
715 		.id = 0x03,
722 		.id = 0x06,
729 		.id = 0x08,
774 	for (i = 0; i < ARRAY_SIZE(cs35l41_otp_map_map); i++) {  in cs35l41_find_otp_map()
785 		{ CS35L41_TEST_KEY_CTL, 0x00000055 },  in cs35l41_test_key_unlock()
786 		{ CS35L41_TEST_KEY_CTL, 0x000000AA },  in cs35l41_test_key_unlock()
801 		{ CS35L41_TEST_KEY_CTL, 0x000000CC },  in cs35l41_test_key_lock()
802 		{ CS35L41_TEST_KEY_CTL, 0x00000033 },  in cs35l41_test_key_lock()
853 	for (i = 0; i < otp_map_match->num_elements; i++) {  in cs35l41_otp_unpack()
860 					GENMASK(bit_offset + otp_map[i].size - 33, 0)) <<  in cs35l41_otp_unpack()
863 		} else if (bit_offset + otp_map[i].size - 1 >= 0) {  in cs35l41_otp_unpack()
868 		} else /* both bit_offset and otp_map[i].size are 0 */  in cs35l41_otp_unpack()
869 			otp_val = 0;  in cs35l41_otp_unpack()
874 			bit_offset = 0;  in cs35l41_otp_unpack()
878 		if (otp_map[i].reg != 0) {  in cs35l41_otp_unpack()
883 			if (ret < 0) {  in cs35l41_otp_unpack()
890 	ret = 0;  in cs35l41_otp_unpack()
930 	ret = regmap_write(reg, CS35L41_DSP1_CCM_CORE_CTRL, 0);  in cs35l41_register_errata_patch()
931 	if (ret < 0)  in cs35l41_register_errata_patch()
948 	val = 0;  in cs35l41_set_channels()
949 	mask = 0;  in cs35l41_set_channels()
950 	for (i = 0; i < rx_num; i++) {  in cs35l41_set_channels()
953 		mask |= 0x3F << (i * 8);  in cs35l41_set_channels()
957 	val = 0;  in cs35l41_set_channels()
958 	mask = 0;  in cs35l41_set_channels()
959 	for (i = 0; i < tx_num; i++) {  in cs35l41_set_channels()
962 		mask |= 0x3F << (i * 8);  in cs35l41_set_channels()
966 	return 0;  in cs35l41_set_channels()
971 	{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
972 	{ 0x24, 0x32, 0x32, 0x4F, 0x57 },
973 	{ 0x40, 0x32, 0x32, 0x4F, 0x57 },
974 	{ 0x40, 0x32, 0x32, 0x4F, 0x57 }
978 	{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
979 	{ 0x24, 0x49, 0x66, 0xA3, 0xEA },
980 	{ 0x48, 0x49, 0x66, 0xA3, 0xEA },
981 	{ 0x48, 0x49, 0x66, 0xA3, 0xEA }
985 	0x75, 0x6B, 0x3B, 0x28
996 		bst_lbst_val = 0;  in cs35l41_boost_config()
1013 	case 0 ... 19:  in cs35l41_boost_config()
1014 		bst_cbst_range = 0;  in cs35l41_boost_config()
1026 		if (boost_cap < 0) {  in cs35l41_boost_config()
1060 	bst_ipk_scaled = ((boost_ipk - 1600) / 50) + 0x10;  in cs35l41_boost_config()
1072 	return 0;  in cs35l41_boost_config()
1076 	{ 0x00000040,			0x00000055 },
1077 	{ 0x00000040,			0x000000AA },
1078 	{ 0x0000393C,			0x000000C0, 6000},
1079 	{ 0x0000393C,			0x00000000 },
1080 	{ 0x00007414,			0x00C82222 },
1081 	{ 0x0000742C,			0x00000000 },
1082 	{ 0x00000040,			0x000000CC },
1083 	{ 0x00000040,			0x00000033 },
1087 	{ 0x00000040,			0x00000055 },
1088 	{ 0x00000040,			0x000000AA },
1089 	{ 0x00007438,			0x00585941 },
1090 	{ CS35L41_PWR_CTRL1,		0x00000000 },
1091 	{ 0x0000742C,			0x00000009 },
1095 	{ 0x00007438,			0x00580941 },
1096 	{ 0x00000040,			0x000000CC },
1097 	{ 0x00000040,			0x00000033 },
1101 	{ 0x00000040,			0x00000055 },
1102 	{ 0x00000040,			0x000000AA },
1103 	{ 0x0000742C,			0x0000000F },
1104 	{ 0x0000742C,			0x00000079 },
1105 	{ 0x00007438,			0x00585941 },
1106 	{ CS35L41_PWR_CTRL1,		0x00000001 }, // GLOBAL_EN = 1
1110 	{ 0x0000742C,			0x000000F9 },
1111 	{ 0x00007438,			0x00580941 },
1115 	{ 0x00000040,			0x00000055 },
1116 	{ 0x00000040,			0x000000AA },
1117 	{ 0x00007438,			0x00585941 },
1118 	{ 0x00007414,			0x08C82222 },
1119 	{ 0x0000742C,			0x00000009 },
1120 	{ 0x00000040,			0x000000CC },
1121 	{ 0x00000040,			0x00000033 },
1126 	{CS35L41_MDSYNC_EN,        0x00003000},
1128 	{CS35L41_BSTCVRT_VCTRL2,    0x00000002},
1132 	/* SYNC_BST_CTL_RX_EN = 0; SYNC_BST_CTL_TX_EN = 1 */
1133 	{CS35L41_MDSYNC_EN,        0x00001000},
1134 	/* BST_EN = 0 */
1135 	{CS35L41_PWR_CTRL2,        0x00003300},
1137 	{CS35L41_BSTCVRT_VCTRL2,    0x00000002},
1161 		regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001);  in cs35l41_init_boost()
1188 		regmap_write(regmap, CS35L41_GPIO1_CTRL1, 0x00000001);  in cs35l41_safe_reset()
1225 		{CS35L41_PWR_CTRL3,		0},  in cs35l41_global_enable()
1226 		{CS35L41_GPIO_PAD_CONTROL,	0},  in cs35l41_global_enable()
1227 		{CS35L41_PWR_CTRL1,		0, 3000},  in cs35l41_global_enable()
1238 		return 0;  in cs35l41_global_enable()
1241 		return 0;  in cs35l41_global_enable()
1259 		cs35l41_mdsync_down_seq[0].def = pwr_ctrl3;  in cs35l41_global_enable()
1421 	dsp->rev = 0;  in cs35l41_configure_cs_dsp()
1428 	dsp->lock_regions = 0xFFFFFFFF;  in cs35l41_configure_cs_dsp()
1458 	unsigned int sts = 0, i;  in cs35l41_set_cspl_mbox_cmd()
1463 	if (ret < 0) {  in cs35l41_set_cspl_mbox_cmd()
1470 	for (i = 0; i < 5; i++) {  in cs35l41_set_cspl_mbox_cmd()
1474 		if (ret < 0) {  in cs35l41_set_cspl_mbox_cmd()
1487 			return 0;  in cs35l41_set_cspl_mbox_cmd()
1503 	if (ret < 0)  in cs35l41_write_fs_errata()
1519 	regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088);  in cs35l41_enter_hibernate()
1520 	regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188);  in cs35l41_enter_hibernate()
1525 	return 0;  in cs35l41_enter_hibernate()
1535 	for (i = 0; i < pwrmgt_retries; i++) {  in cs35l41_wait_for_pwrmgt_sts()
1554 	for (i = 0; i < sleep_retries; i++) {  in cs35l41_exit_hibernate()
1557 		for (j = 0; j < wake_retries; j++) {  in cs35l41_exit_hibernate()
1568 			return 0;  in cs35l41_exit_hibernate()
1574 		regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0088);  in cs35l41_exit_hibernate()
1577 		regmap_write(regmap, CS35L41_WAKESRC_CTL, 0x0188);  in cs35l41_exit_hibernate()
1580 		regmap_write(regmap, CS35L41_PWRMGT_CTL, 0x3);  in cs35l41_exit_hibernate()