34 #define PW_MGMT1	0x00
35 #define PW_MGMT2	0x01
36 #define SG_SL1		0x02
37 #define SG_SL2		0x03
38 #define MD_CTL1		0x04
39 #define MD_CTL2		0x05
40 #define TIMER		0x06
41 #define ALC_CTL1	0x07
42 #define ALC_CTL2	0x08
43 #define L_IVC		0x09
44 #define L_DVC		0x0a
45 #define ALC_CTL3	0x0b
46 #define R_IVC		0x0c
47 #define R_DVC		0x0d
48 #define MD_CTL3		0x0e
49 #define MD_CTL4		0x0f
50 #define PW_MGMT3	0x10
51 #define DF_S		0x11
52 #define FIL3_0		0x12
53 #define FIL3_1		0x13
54 #define FIL3_2		0x14
55 #define FIL3_3		0x15
56 #define EQ_0		0x16
57 #define EQ_1		0x17
58 #define EQ_2		0x18
59 #define EQ_3		0x19
60 #define EQ_4		0x1a
61 #define EQ_5		0x1b
62 #define FIL1_0		0x1c
63 #define FIL1_1		0x1d
64 #define FIL1_2		0x1e
65 #define FIL1_3		0x1f	/* The maximum valid register for ak4642 */
66 #define PW_MGMT4	0x20
67 #define MD_CTL5		0x21
68 #define LO_MS		0x22
69 #define HP_MS		0x23
70 #define SPK_MS		0x24	/* The maximum valid register for ak4643 */
71 #define EQ_FBEQAB	0x25
72 #define EQ_FBEQCD	0x26
73 #define EQ_FBEQE	0x27	/* The maximum valid register for ak4648 */
79 #define PMADL		(1 << 0) /* MIC Amp Lch and ADC Lch Power Management */
87 #define PMPLL		(1 << 0)
93 #define PMADR		(1 << 0) /* MIC L / ADC R Power Management */
99 #define MGAIN0		(1 << 0) /* MIC amp gain*/
105 #define ZTM(param)	((param & 0x3) << 4) /* ALC Zero Crossing TimeOut */
106 #define WTM(param)	(((param & 0x4) << 4) | ((param & 0x3) << 2))
110 #define LMTH0		(1 << 0) /* ALC Limiter / Recovery Level */
122 #define DIF_MASK	(3 << 0)
123 #define DSP		(0 << 0)
124 #define RIGHT_J		(1 << 0)
125 #define LEFT_J		(2 << 0)
126 #define I2S		(3 << 0)
129 #define FSs(val)	(((val & 0x7) << 0) | ((val & 0x8) << 2))
130 #define PSs(val)	((val & 0x3) << 6)
136 #define DACH		(1 << 0)
151  * max : 0x00 : +12.0 dB
153  * min : 0xFE : -115.0 dB
154  * mute: 0xFF
161 			 0, 0xFF, 1, out_tlv),
162 	SOC_SINGLE("ALC Capture Switch", ALC_CTL1, 5, 1, 0),
167 	SOC_DAPM_SINGLE("Switch", PW_MGMT2, 6, 1, 0);
170 	SOC_DAPM_SINGLE("DACL", SG_SL1, 4, 1, 0),
189 		snd_soc_component_update_bits(component, SG_SL2, LOPS, 0);  in ak4642_lout_event()
193 	return 0;  in ak4642_lout_event()
203 	SND_SOC_DAPM_PGA("HPL Out", PW_MGMT2, 5, 0, NULL, 0),
204 	SND_SOC_DAPM_PGA("HPR Out", PW_MGMT2, 4, 0, NULL, 0),
205 	SND_SOC_DAPM_SWITCH("Headphone Enable", SND_SOC_NOPM, 0, 0,
208 	SND_SOC_DAPM_PGA("DACH", MD_CTL4, 0, 0, NULL, 0),
210 	SND_SOC_DAPM_MIXER_E("LINEOUT Mixer", PW_MGMT1, 3, 0,
211 			   &ak4642_lout_mixer_controls[0],
218 	SND_SOC_DAPM_DAC("DAC", NULL, PW_MGMT1, 2, 0),
244 	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
245 	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
246 	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
247 	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0x08 },
248 	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
249 	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
250 	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
251 	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
252 	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
253 	{ 36, 0x00 },
256 /* The default settings for 0x0 ~ 0x1f registers are the same for ak4642
258    The valid registers for ak4642 are 0x0 ~ 0x1f which is a subset of ak4643,
265 	{  0, 0x00 }, {  1, 0x00 }, {  2, 0x01 }, {  3, 0x00 },
266 	{  4, 0x02 }, {  5, 0x00 }, {  6, 0x00 }, {  7, 0x00 },
267 	{  8, 0xe1 }, {  9, 0xe1 }, { 10, 0x18 }, { 11, 0x00 },
268 	{ 12, 0xe1 }, { 13, 0x18 }, { 14, 0x11 }, { 15, 0xb8 },
269 	{ 16, 0x00 }, { 17, 0x00 }, { 18, 0x00 }, { 19, 0x00 },
270 	{ 20, 0x00 }, { 21, 0x00 }, { 22, 0x00 }, { 23, 0x00 },
271 	{ 24, 0x00 }, { 25, 0x00 }, { 26, 0x00 }, { 27, 0x00 },
272 	{ 28, 0x00 }, { 29, 0x00 }, { 30, 0x00 }, { 31, 0x00 },
273 	{ 32, 0x00 }, { 33, 0x00 }, { 34, 0x00 }, { 35, 0x00 },
274 	{ 36, 0x00 }, { 37, 0x88 }, { 38, 0x88 }, { 39, 0x08 },
294 		snd_soc_component_write(component, L_IVC, 0x91); /* volume */  in ak4642_dai_startup()
295 		snd_soc_component_write(component, R_IVC, 0x91); /* volume */  in ak4642_dai_startup()
311 		snd_soc_component_write(component, TIMER, ZTM(0x3) | WTM(0x3));  in ak4642_dai_startup()
317 	return 0;  in ak4642_dai_startup()
329 		snd_soc_component_update_bits(component, PW_MGMT1, PMADL, 0);  in ak4642_dai_shutdown()
330 		snd_soc_component_update_bits(component, PW_MGMT3, PMADR, 0);  in ak4642_dai_shutdown()
331 		snd_soc_component_update_bits(component, ALC_CTL1, ALC, 0);  in ak4642_dai_shutdown()
341 	int extended_freq = 0;  in ak4642_dai_set_sysclk()
383 	return 0;  in ak4642_dai_set_sysclk()
393 	bcko = 0;  in ak4642_dai_set_fmt()
410 	data = 0;  in ak4642_dai_set_fmt()
426 	return 0;  in ak4642_dai_set_fmt()
433 		[0] = 8000,  in ak4642_set_mcko()
447 		[0] = 256,  in ak4642_set_mcko()
454 	for (ps = 0; ps < ARRAY_SIZE(ps_list); ps++) {  in ak4642_set_mcko()
455 		for (fs = 0; fs < ARRAY_SIZE(fs_list); fs++) {  in ak4642_set_mcko()
459 				return 0;  in ak4642_set_mcko()
464 	return 0;  in ak4642_set_mcko()
486 		snd_soc_component_write(component, PW_MGMT1, 0x00);  in ak4642_set_bias_level()
493 	return 0;  in ak4642_set_bias_level()
528 	return 0;  in ak4642_suspend()
537 	return 0;  in ak4642_resume()
546 	return 0;  in ak4642_probe()
617 		parent_clk_name = of_clk_get_parent_name(np, 0);  in ak4642_of_parse_mcko()
621 	clk = clk_register_fixed_rate(dev, clk_name, parent_clk_name, 0, rate);  in ak4642_of_parse_mcko()
628 #define ak4642_of_parse_mcko(d) 0