1 // SPDX-License-Identifier: GPL-2.0-only
6  * Author: Lars-Peter Clausen <lars@metafoo.de>
24 #include "adau-utils.h"
125 static const DECLARE_TLV_DB_MINMAX(adau1372_digital_tlv, -9563, 0);
126 static const DECLARE_TLV_DB_SCALE(adau1372_pga_tlv, -1200, 75, 0);
189 	SOC_ENUM("ADC 0+1 High-Pass-Filter", adau1372_hpf0_1_enum),
190 	SOC_ENUM("ADC 2+3 High-Pass-Filter", adau1372_hpf2_3_enum),
361 	SND_SOC_DAPM_INPUT("AIN0"),
362 	SND_SOC_DAPM_INPUT("AIN1"),
482 	{ "PGA0", NULL, "AIN0" },
483 	{ "PGA1", NULL, "AIN1" },
581 		adau1372->clock_provider = true;  in adau1372_set_dai_fmt()
585 		adau1372->clock_provider = false;  in adau1372_set_dai_fmt()
588 		return -EINVAL;  in adau1372_set_dai_fmt()
629 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_DELAY_MASK, sai0);  in adau1372_set_dai_fmt()
630 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1,  in adau1372_set_dai_fmt()
652 		return -EINVAL;  in adau1372_hw_params()
656 	slot_width = adau1372->slot_width;  in adau1372_hw_params()
669 		return -EINVAL;  in adau1372_hw_params()
672 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_FS_MASK, sai0);  in adau1372_hw_params()
673 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLKRATE, sai1);  in adau1372_hw_params()
687 		regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0,  in adau1372_set_tdm_slot()
689 		adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;  in adau1372_set_tdm_slot()
690 		adau1372->slot_width = 0;  in adau1372_set_tdm_slot()
696 		return -EINVAL;  in adau1372_set_tdm_slot()
707 		return -EINVAL;  in adau1372_set_tdm_slot()
713 		adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;  in adau1372_set_tdm_slot()
717 		if (adau1372->clock_provider)  in adau1372_set_tdm_slot()
718 			adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4_MASTER;  in adau1372_set_tdm_slot()
720 			adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM4;  in adau1372_set_tdm_slot()
724 		adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM8;  in adau1372_set_tdm_slot()
727 		return -EINVAL;  in adau1372_set_tdm_slot()
730 	adau1372->slot_width = width;  in adau1372_set_tdm_slot()
732 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI0, ADAU1372_SAI0_SAI_MASK, sai0);  in adau1372_set_tdm_slot()
733 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_BCLK_TDMC, sai1);  in adau1372_set_tdm_slot()
736 	regmap_write(adau1372->regmap, ADAU1372_REG_SOUT_CTRL, ~tx_mask);  in adau1372_set_tdm_slot()
751 	return regmap_update_bits(adau1372->regmap, ADAU1372_REG_SAI1, ADAU1372_SAI1_TDM_TS, sai1);  in adau1372_set_tristate()
758 	snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_RATE,  in adau1372_startup()
759 				   &adau1372->rate_constraints);  in adau1372_startup()
769 	regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,  in adau1372_enable_pll()
774 		ret = regmap_read(adau1372->regmap, ADAU1372_REG_PLL(5), &val);  in adau1372_enable_pll()
781 		dev_err(adau1372->dev, "Failed to lock PLL\n");  in adau1372_enable_pll()
786 	if (adau1372->enabled == enable)  in adau1372_set_power()
792 		clk_prepare_enable(adau1372->mclk);  in adau1372_set_power()
793 		if (adau1372->pd_gpio)  in adau1372_set_power()
794 			gpiod_set_value(adau1372->pd_gpio, 0);  in adau1372_set_power()
796 		if (adau1372->switch_mode)  in adau1372_set_power()
797 			adau1372->switch_mode(adau1372->dev);  in adau1372_set_power()
799 		regcache_cache_only(adau1372->regmap, false);  in adau1372_set_power()
805 		if (adau1372->use_pll) {  in adau1372_set_power()
810 		regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,  in adau1372_set_power()
812 		regcache_sync(adau1372->regmap);  in adau1372_set_power()
814 		if (adau1372->pd_gpio) {  in adau1372_set_power()
820 			gpiod_set_value(adau1372->pd_gpio, 1);  in adau1372_set_power()
821 			regcache_mark_dirty(adau1372->regmap);  in adau1372_set_power()
823 			regmap_update_bits(adau1372->regmap, ADAU1372_REG_CLK_CTRL,  in adau1372_set_power()
826 		clk_disable_unprepare(adau1372->mclk);  in adau1372_set_power()
827 		regcache_cache_only(adau1372->regmap, true);  in adau1372_set_power()
830 	adau1372->enabled = enable;  in adau1372_set_power()
910 		regmap_write(adau1372->regmap, ADAU1372_REG_PLL(i), regs[i]);  in adau1372_setup_pll()
928 		return -ENOMEM;  in adau1372_probe()
930 	adau1372->mclk = devm_clk_get(dev, "mclk");  in adau1372_probe()
931 	if (IS_ERR(adau1372->mclk))  in adau1372_probe()
932 		return PTR_ERR(adau1372->mclk);  in adau1372_probe()
934 	adau1372->pd_gpio = devm_gpiod_get_optional(dev, "powerdown", GPIOD_OUT_HIGH);  in adau1372_probe()
935 	if (IS_ERR(adau1372->pd_gpio))  in adau1372_probe()
936 		return PTR_ERR(adau1372->pd_gpio);  in adau1372_probe()
938 	adau1372->regmap = regmap;  in adau1372_probe()
939 	adau1372->switch_mode = switch_mode;  in adau1372_probe()
940 	adau1372->dev = dev;  in adau1372_probe()
941 	adau1372->rate_constraints.list = adau1372_rates;  in adau1372_probe()
942 	adau1372->rate_constraints.count = ARRAY_SIZE(adau1372_rates);  in adau1372_probe()
943 	adau1372->rate_constraints.mask = ADAU1372_RATE_MASK_TDM2;  in adau1372_probe()
952 	rate = clk_get_rate(adau1372->mclk);  in adau1372_probe()
966 		adau1372->use_pll = true;  in adau1372_probe()
979 	 * No pinctrl support yet, put the multi-purpose pins in the most  in adau1372_probe()
1064 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");