Lines Matching +full:0 +full:x0054
10 #define I2S_MISC_CFG (0x003C)
19 #define I2S_TX_CLOCK_ENABLE (1 << 0)
22 #define I2S_TX_DESC_OFF_LEVEL_MASK (0x0F << I2S_TX_DESC_OFF_LEVEL_SHIFT)
24 #define I2S_TX_DESC_IFF_LEVEL_MASK (0x0F << I2S_TX_DESC_IFF_LEVEL_SHIFT)
28 #define I2S_TX_CFG (0x0000)
29 #define I2S_TX_IRQ_CTL (0x0004)
30 #define I2S_TX_IRQ_EN (0x0008)
31 #define I2S_TX_IRQ_IFF_THLD (0x000c)
32 #define I2S_TX_IRQ_OFF_THLD (0x0010)
33 #define I2S_TX_DESC_IFF_ADDR (0x0014)
34 #define I2S_TX_DESC_IFF_LEN (0x0018)
35 #define I2S_TX_DESC_OFF_ADDR (0x001C)
36 #define I2S_TX_DESC_OFF_LEN (0x0020)
37 #define I2S_TX_CFG_2 (0x0024)
41 #define I2S_TX_MASTER_MODE 0
42 #define I2S_TX_INTR_MASK 0x0F
48 #define I2S_RX_CLOCK_ENABLE (1 << 0)
51 #define I2S_RX_DESC_OFF_LEVEL_MASK (0x0F << I2S_RX_DESC_OFF_LEVEL_SHIFT)
53 #define I2S_RX_DESC_IFF_LEVEL_MASK (0x0F << I2S_RX_DESC_IFF_LEVEL_SHIFT)
57 #define I2S_RX_CFG (0x0040) /* 20c0 */
58 #define I2S_RX_IRQ_CTL (0x0044)
59 #define I2S_RX_IRQ_EN (0x0048)
60 #define I2S_RX_IRQ_IFF_THLD (0x004C)
61 #define I2S_RX_IRQ_OFF_THLD (0x0050)
62 #define I2S_RX_DESC_IFF_ADDR (0x0054)
63 #define I2S_RX_DESC_IFF_LEN (0x0058)
64 #define I2S_RX_DESC_OFF_ADDR (0x005C)
65 #define I2S_RX_DESC_OFF_LEN (0x0060)
66 #define I2S_RX_CFG_2 (0x0064)
70 #define I2S_RX_MASTER_MODE 0
71 #define I2S_RX_INTR_MASK 0x0F
73 #define I2S_REG_MAX 0x007C