Lines Matching refs:dd
109 struct mchp_pdmc *dd;
148 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
152 item = snd_soc_enum_val_to_item(e, dd->sinc_order);
162 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
172 if (atomic_read(&dd->busy_stream))
175 if (val == dd->sinc_order)
178 dd->sinc_order = val;
187 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
189 uvalue->value.integer.value[0] = !!dd->audio_filter_en;
198 struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
201 if (atomic_read(&dd->busy_stream))
204 if (dd->audio_filter_en == af)
207 dd->audio_filter_en = af;
217 uinfo->count = info->dd->mic_no;
250 struct mchp_pdmc *dd = info->dd;
262 memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
275 if (dd->channel_mic_map[map_idx].ds_pos)
277 if (dd->channel_mic_map[map_idx].clk_edge)
283 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
292 struct mchp_pdmc *dd = info->dd;
317 if (dd->channel_mic_map[map_idx].ds_pos)
319 if (dd->channel_mic_map[map_idx].clk_edge)
323 regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
423 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
425 regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
428 &mchp_pdmc_chan_constr[dd->mic_no - 1]);
435 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
437 snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
521 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
541 if (channels > dd->mic_no) {
543 channels, dd->mic_no);
547 dd->pdmcen = 0;
549 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
550 if (dd->channel_mic_map[i].ds_pos)
552 if (dd->channel_mic_map[i].clk_edge)
560 atomic_set(&dd->busy_stream, 1);
561 for (osr_start = dd->audio_filter_en ? 64 : 8;
566 round_rate = clk_round_rate(dd->gclk,
583 clk_disable_unprepare(dd->gclk);
586 ret = clk_set_rate(dd->gclk, gclk_rate);
587 clk_prepare_enable(dd->gclk);
594 mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
596 mr_val |= FIELD_PREP(MCHP_PDMC_MR_SINCORDER_MASK, dd->sinc_order);
599 dd->addr.maxburst = maxburst;
600 mr_val |= FIELD_PREP(MCHP_PDMC_MR_CHUNK_MASK, dd->addr.maxburst);
601 dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
614 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd)
628 usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5);
631 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp);
634 regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp);
640 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
652 dd->pdmcen);
654 mchp_pdmc_noise_filter_workaround(dd);
657 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq |
659 dd->suspend_irq = 0;
662 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq);
666 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq |
678 regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
679 dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
680 regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
681 dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
682 regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
683 dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
689 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
710 info->dd = dd;
731 struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
734 ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
736 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
767 struct mchp_pdmc *dd = dev_id;
771 regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
772 regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
775 dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
781 dev_warn(dd->dev, "underrun detected\n");
782 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
786 dev_warn(dd->dev, "overrun detected\n");
787 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
858 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
860 struct device_node *np = dd->dev->of_node;
866 dev_err(dd->dev, "device node not found\n");
870 dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
871 if (dd->mic_no < 0) {
872 dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
873 dd->mic_no);
874 return dd->mic_no;
876 if (!dd->mic_no || dd->mic_no % 2 ||
877 dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
878 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
879 dd->mic_no);
883 dd->mic_no /= 2;
885 dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
892 for (i = 0; i < dd->mic_no; i++) {
899 dev_err(dd->dev,
905 dev_err(dd->dev,
914 dev_err(dd->dev,
922 dev_err(dd->dev,
927 dev_err(dd->dev,
933 dd->channel_mic_map[i].ds_pos = ds;
934 dd->channel_mic_map[i].clk_edge = edge;
937 dd->startup_delay_us = 150000;
938 of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us);
967 struct mchp_pdmc *dd = dev_get_drvdata(dev);
969 regcache_cache_only(dd->regmap, true);
971 clk_disable_unprepare(dd->gclk);
972 clk_disable_unprepare(dd->pclk);
979 struct mchp_pdmc *dd = dev_get_drvdata(dev);
982 ret = clk_prepare_enable(dd->pclk);
984 dev_err(dd->dev,
988 ret = clk_prepare_enable(dd->gclk);
990 dev_err(dd->dev,
995 regcache_cache_only(dd->regmap, false);
996 regcache_mark_dirty(dd->regmap);
997 ret = regcache_sync(dd->regmap);
999 regcache_cache_only(dd->regmap, true);
1000 clk_disable_unprepare(dd->gclk);
1002 clk_disable_unprepare(dd->pclk);
1011 struct mchp_pdmc *dd;
1018 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
1019 if (!dd)
1022 dd->dev = &pdev->dev;
1023 ret = mchp_pdmc_dt_init(dd);
1031 dd->pclk = devm_clk_get(dev, "pclk");
1032 if (IS_ERR(dd->pclk)) {
1033 ret = PTR_ERR(dd->pclk);
1038 dd->gclk = devm_clk_get(dev, "gclk");
1039 if (IS_ERR(dd->gclk)) {
1040 ret = PTR_ERR(dd->gclk);
1052 dd->regmap = devm_regmap_init_mmio(dev, io_base,
1054 if (IS_ERR(dd->regmap)) {
1055 ret = PTR_ERR(dd->regmap);
1061 dev_name(&pdev->dev), dd);
1071 dd->audio_filter_en = true;
1072 dd->sinc_order = 3;
1074 dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1075 platform_set_drvdata(pdev, dd);
1077 pm_runtime_enable(dd->dev);
1078 if (!pm_runtime_enabled(dd->dev)) {
1079 ret = mchp_pdmc_runtime_resume(dd->dev);
1099 regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1100 dev_info(dd->dev, "hw version: %#lx\n",
1106 if (!pm_runtime_status_suspended(dd->dev))
1107 mchp_pdmc_runtime_suspend(dd->dev);
1108 pm_runtime_disable(dd->dev);
1115 struct mchp_pdmc *dd = platform_get_drvdata(pdev);
1117 atomic_set(&dd->busy_stream, 0);
1119 if (!pm_runtime_status_suspended(dd->dev))
1120 mchp_pdmc_runtime_suspend(dd->dev);
1122 pm_runtime_disable(dd->dev);