Lines Matching +full:0 +full:x00010001
11 #define ACP_DEVICE_ID 0x15E2
12 #define ACP63_REG_START 0x1240000
13 #define ACP63_REG_END 0x125C000
15 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
17 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
19 #define ACP_POWERED_ON 0
24 #define ACP_ERROR_MASK 0x20000000
25 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
26 #define PDM_DMA_STAT 0x10
28 #define PDM_DMA_INTR_MASK 0x10000
34 #define ACP_PDM_DISABLE 0
40 #define ACP_SRAM_PTE_OFFSET 0x03800000
42 #define PDM_PTE_OFFSET 0
43 #define PDM_MEM_WINDOW_START 0x4000000
69 #define ACP_AUDIO0_TX_THRESHOLD 0x1c
70 #define ACP_AUDIO1_TX_THRESHOLD 0x1a
71 #define ACP_AUDIO2_TX_THRESHOLD 0x18
72 #define ACP_AUDIO0_RX_THRESHOLD 0x1b
73 #define ACP_AUDIO1_RX_THRESHOLD 0x19
74 #define ACP_AUDIO2_RX_THRESHOLD 0x17
77 #define ACP_SDW_DMA_IRQ_MASK 0x1F800000
78 #define ACP_P1_SDW_DMA_IRQ_MASK 0x60
87 * 0 (SDW0_AUDIO0_TX) 28
101 * 0 (SDW1_AUDIO1_TX) 6
108 #define SDW0_MEM_WINDOW_START 0x4800000
109 #define ACP_SDW_SRAM_PTE_OFFSET 0x03800400
110 #define SDW0_PTE_OFFSET 0x400
111 #define SDW_FIFO_SIZE 0x100
112 #define SDW_DMA_SIZE 0x40
113 #define ACP_SDW0_FIFO_OFFSET 0x100
114 #define ACP_SDW_PTE_OFFSET 0x100
115 #define SDW_FIFO_OFFSET 0x100
116 #define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600))
117 #define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500))
118 #define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000))
133 ACP_CONFIG_0 = 0,
152 ACP_SDW0_AUDIO0_TX = 0,