Lines Matching +full:no +full:- +full:sync +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * Modified 2006-06-01 for AES32 support by Remy Bruno
12 * Modified 2009-04-13 for proper metering by Florian Faber
15 * Modified 2009-04-14 for native float support by Florian Faber
18 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
21 * Modified 2009-04-30 added hw serial number support by Florian Faber
23 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
25 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
27 * Modified 2019-05-23 fix AIO single speed ADAT capture and playback
35 * --------- HDSPM_controlRegister ---------
44 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave
45 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency
57 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
94 * ------------ HDSPM_WR_SETTINGS ----------
143 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
169 /* --- Write registers. ---
170 These are defined as byte-offsets from the iobase value. */
184 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
185 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
192 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
196 /* --- Read registers. ---
197 These are defined as byte-offsets from the iobase value */
200 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
256 /* status is data bytes in MIDI-FIFO (0-128) */
267 /* the meters are regular i/o-mapped registers, but offset
269 when read; the least-significant 4 bits are full-scale counters;
270 the actual peak value is in the most-significant 24 bits.
285 /* --- Control Register bits --------- */
304 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
308 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
313 * -- MADI ONLY
360 /* --- bit helper defines */
377 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
378 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
400 /* AutoSync References - used by "autosync_ref" control switch */
417 /* --- control2 register bits --- */
430 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
435 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
440 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
441 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
444 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
446 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
447 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
478 /* --- status bit helpers */
498 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
505 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
510 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
552 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
568 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
644 "TCO", "Sync In"
649 "Sync In"
652 "MADI", "TCO", "Sync In" };
654 "MADI", "Sync In" };
659 "AES", "SPDIF", "TCO", "Sync In"
664 "AES", "SPDIF", "Sync In"
668 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
671 "ADAT", "AES", "SPDIF", "Sync In" };
674 "No Lock",
816 -1, -1, -1, -1,
817 -1, -1, -1, -1, -1, -1, -1, -1,
818 -1, -1, -1, -1, -1, -1, -1, -1,
819 -1, -1, -1, -1, -1, -1, -1, -1,
829 -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 -1, -1, -1, -1, -1, -1, -1, -1,
833 -1, -1, -1, -1, -1, -1, -1, -1,
834 -1, -1, -1, -1, -1, -1, -1, -1,
844 -1, -1, -1, -1,
845 -1, -1, -1, -1, -1, -1, -1, -1,
846 -1, -1, -1, -1, -1, -1, -1, -1,
847 -1, -1, -1, -1, -1, -1, -1, -1,
848 -1, -1, -1, -1, -1, -1, -1, -1,
849 -1, -1, -1, -1, -1, -1, -1, -1,
850 -1, -1, -1, -1, -1, -1, -1, -1,
859 -1, -1, -1, -1, -1, -1,
860 -1, -1, -1, -1, -1, -1, -1, -1,
861 -1, -1, -1, -1, -1, -1, -1, -1,
862 -1, -1, -1, -1, -1, -1, -1, -1,
863 -1, -1, -1, -1, -1, -1, -1, -1,
864 -1, -1, -1, -1, -1, -1, -1, -1,
874 -1, -1, -1, -1,
875 -1, -1, -1, -1, -1, -1, -1, -1,
876 -1, -1, -1, -1, -1, -1, -1, -1,
877 -1, -1, -1, -1, -1, -1, -1, -1,
878 -1, -1, -1, -1, -1, -1, -1, -1,
879 -1, -1, -1, -1, -1, -1, -1, -1,
888 -1, -1,
889 -1, -1, -1, -1, -1, -1, -1, -1,
890 -1, -1, -1, -1, -1, -1, -1, -1,
891 -1, -1, -1, -1, -1, -1, -1, -1,
892 -1, -1, -1, -1, -1, -1, -1, -1,
893 -1, -1, -1, -1, -1, -1, -1, -1,
894 -1, -1, -1, -1, -1, -1, -1, -1
904 -1, -1, -1, -1, -1, -1, -1, -1,
905 -1, -1, -1, -1, -1, -1, -1, -1,
906 -1, -1, -1, -1, -1, -1, -1, -1,
907 -1, -1, -1, -1, -1, -1, -1, -1,
908 -1, -1, -1, -1, -1, -1, -1, -1,
909 -1, -1, -1, -1, -1, -1, -1, -1
918 -1, -1, -1, -1,
919 -1, -1, -1, -1, -1, -1, -1, -1,
920 -1, -1, -1, -1, -1, -1, -1, -1,
921 -1, -1, -1, -1, -1, -1, -1, -1,
922 -1, -1, -1, -1, -1, -1, -1, -1,
923 -1, -1, -1, -1, -1, -1, -1, -1,
924 -1, -1, -1, -1, -1, -1, -1, -1
934 -1, -1,
935 -1, -1, -1, -1, -1, -1, -1, -1,
936 -1, -1, -1, -1, -1, -1, -1, -1,
937 -1, -1, -1, -1, -1, -1, -1, -1,
938 -1, -1, -1, -1, -1, -1, -1, -1,
939 -1, -1, -1, -1, -1, -1, -1, -1,
940 -1, -1, -1, -1, -1, -1, -1, -1
946 -1, -1, -1, -1, -1, -1, -1, -1,
947 -1, -1, -1, -1, -1, -1, -1, -1,
948 -1, -1, -1, -1, -1, -1, -1, -1,
949 -1, -1, -1, -1, -1, -1, -1, -1,
950 -1, -1, -1, -1, -1, -1, -1, -1,
951 -1, -1, -1, -1, -1, -1, -1, -1
975 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
977 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
996 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */
1057 /* full mixer accessible over mixer ioctl or hwdep-device */
1060 struct hdspm_tco *tco; /* NULL if no TCO detected */
1127 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1137 writel(val, hdspm->iobase + reg);
1142 return readl(hdspm->iobase + reg);
1155 return hdspm->mixer->ch[chan].in[in];
1163 return hdspm->mixer->ch[chan].pb[pb];
1170 return -1;
1175 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1183 return -1;
1188 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1193 /* enable DMA for specific channels, now available for DSP-MADI */
1207 guard(spinlock_irqsave)(&hdspm->lock);
1208 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1209 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0))
1227 * in 96k frame mode.
1230 * user-provided DS/QS bits in the control register
1236 if (hdspm->control_register & HDSPM_QuadSpeed)
1238 else if (hdspm->control_register &
1251 switch (hdspm->io_type) {
1259 /* Check WC sync and get sample rate */
1272 /* Check AES sync and get sample rate */
1273 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1275 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1280 /* Check TCO sync and get sample rate */
1293 rate = 0; /* no lock */
1376 /* maybe a madi input (which is taken if sel sync is madi) */
1450 n = hdspm_decode_latency(hdspm->control_register);
1459 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1460 n = -1;
1468 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1478 switch (hdspm->io_type) {
1486 (hdspm->period_bytes / 4) : 0;
1495 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1496 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1501 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1502 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1509 int n = hdspm->period_bytes;
1510 void *buf = hdspm->playback_buffer;
1525 guard(spinlock_irq)(&s->lock);
1548 s->control_register &= ~HDSPM_LatencyMask;
1549 s->control_register |= hdspm_encode_latency(n);
1551 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1565 switch (hdspm->io_type) {
1598 switch (hdspm->io_type) {
1629 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1633 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1635 /* SLAVE --- */
1640 for future master mode switching */
1642 dev_warn(hdspm->card->dev,
1647 /* hw_param request while in AutoSync mode */
1654 dev_warn(hdspm->card->dev,
1655 "Detected no External Sync\n");
1660 dev_warn(hdspm->card->dev,
1661 "Warning: No AutoSync source for requested rate\n");
1667 current_rate = hdspm->system_sample_rate;
1675 externally-driven rate changes. All we can do is to flag rate
1722 return -EINVAL;
1726 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1727 dev_err(hdspm->card->dev,
1728 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1731 hdspm->capture_pid, hdspm->playback_pid);
1732 return -EBUSY;
1735 hdspm->control_register &= ~HDSPM_FrequencyMask;
1736 hdspm->control_register |= rate_bits;
1737 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1743 if (AES32 == hdspm->io_type && rate != current_rate)
1746 hdspm->system_sample_rate = rate;
1749 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1750 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1751 hdspm->max_channels_in = hdspm->ss_in_channels;
1752 hdspm->max_channels_out = hdspm->ss_out_channels;
1753 hdspm->port_names_in = hdspm->port_names_in_ss;
1754 hdspm->port_names_out = hdspm->port_names_out_ss;
1756 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1757 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1758 hdspm->max_channels_in = hdspm->ds_in_channels;
1759 hdspm->max_channels_out = hdspm->ds_out_channels;
1760 hdspm->port_names_in = hdspm->port_names_in_ds;
1761 hdspm->port_names_out = hdspm->port_names_out_ds;
1763 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1764 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1765 hdspm->max_channels_in = hdspm->qs_in_channels;
1766 hdspm->max_channels_out = hdspm->qs_out_channels;
1767 hdspm->port_names_in = hdspm->port_names_in_qs;
1768 hdspm->port_names_out = hdspm->port_names_out_qs;
1772 return -1;
1797 /*----------------------------------------------------------------------------
1799 ----------------------------------------------------------------------------*/
1804 /* the hardware already does the relevant bit-mask with 0xff */
1805 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1811 /* the hardware already does the relevant bit-mask with 0xff */
1812 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1817 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1824 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1827 return 128 - fifo_bytes_used;
1836 while (snd_hdspm_midi_input_available(hdspm, id) && --count)
1849 guard(spinlock_irqsave)(&hmidi->lock);
1850 if (hmidi->output &&
1851 !snd_rawmidi_transmit_empty (hmidi->output)) {
1852 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1853 hmidi->id);
1858 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1862 snd_hdspm_midi_write_byte (hmidi->hdspm,
1863 hmidi->id,
1879 scoped_guard(spinlock_irqsave, &hmidi->lock) {
1880 n_pending = snd_hdspm_midi_input_available(hmidi->hdspm, hmidi->id);
1882 if (hmidi->input) {
1886 buf[i] = snd_hdspm_midi_read_byte(hmidi->hdspm,
1887 hmidi->id);
1889 snd_rawmidi_receive(hmidi->input, buf,
1893 while (n_pending--)
1894 snd_hdspm_midi_read_byte(hmidi->hdspm,
1895 hmidi->id);
1898 hmidi->pending = 0;
1901 scoped_guard(spinlock_irqsave, &hmidi->hdspm->lock) {
1902 hmidi->hdspm->control_register |= hmidi->ie;
1903 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1904 hmidi->hdspm->control_register);
1916 hmidi = substream->rmidi->private_data;
1917 hdspm = hmidi->hdspm;
1919 guard(spinlock_irqsave)(&hdspm->lock);
1921 if (!(hdspm->control_register & hmidi->ie)) {
1922 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1923 hdspm->control_register |= hmidi->ie;
1926 hdspm->control_register &= ~hmidi->ie;
1929 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1937 guard(spinlock_irqsave)(&hmidi->lock);
1939 /* this does not bump hmidi->istimer, because the
1945 if (hmidi->istimer)
1946 mod_timer(&hmidi->timer, 1 + jiffies);
1954 hmidi = substream->rmidi->private_data;
1955 scoped_guard(spinlock_irqsave, &hmidi->lock) {
1957 if (!hmidi->istimer) {
1958 timer_setup(&hmidi->timer,
1960 mod_timer(&hmidi->timer, 1 + jiffies);
1961 hmidi->istimer++;
1964 if (hmidi->istimer && --hmidi->istimer <= 0)
1965 timer_delete(&hmidi->timer);
1976 hmidi = substream->rmidi->private_data;
1977 guard(spinlock_irq)(&hmidi->lock);
1978 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
1979 hmidi->input = substream;
1988 hmidi = substream->rmidi->private_data;
1989 guard(spinlock_irq)(&hmidi->lock);
1990 hmidi->output = substream;
2001 hmidi = substream->rmidi->private_data;
2002 guard(spinlock_irq)(&hmidi->lock);
2003 hmidi->input = NULL;
2014 hmidi = substream->rmidi->private_data;
2015 guard(spinlock_irq)(&hmidi->lock);
2016 hmidi->output = NULL;
2041 hdspm->midi[id].id = id;
2042 hdspm->midi[id].hdspm = hdspm;
2043 spin_lock_init (&hdspm->midi[id].lock);
2046 if (MADIface == hdspm->io_type) {
2047 /* MIDI-over-MADI on HDSPe MADIface */
2048 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2049 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2050 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2051 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2052 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2053 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2055 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2056 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2057 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2058 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2059 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2060 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2063 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2064 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2065 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2066 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2067 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2068 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2069 } else if ((2 == id) && (MADI == hdspm->io_type)) {
2070 /* MIDI-over-MADI on HDSPe MADI */
2071 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2072 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2073 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2074 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2075 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2076 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2079 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2080 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2081 hdspm->midi[2].dataOut = -1;
2082 hdspm->midi[2].statusOut = -1;
2083 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2084 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2087 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2088 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2089 hdspm->midi[3].dataOut = -1;
2090 hdspm->midi[3].statusOut = -1;
2091 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2092 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2095 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2096 (MADIface == hdspm->io_type)))) {
2097 if ((id == 0) && (MADIface == hdspm->io_type)) {
2099 card->shortname);
2100 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2102 card->shortname);
2105 card->shortname, id+1);
2108 &hdspm->midi[id].rmidi);
2112 snprintf(hdspm->midi[id].rmidi->name,
2113 sizeof(hdspm->midi[id].rmidi->name),
2114 "%s MIDI %d", card->id, id+1);
2115 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2117 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2120 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2124 hdspm->midi[id].rmidi->info_flags |=
2131 card->shortname, id+1);
2133 &hdspm->midi[id].rmidi);
2137 snprintf(hdspm->midi[id].rmidi->name,
2138 sizeof(hdspm->midi[id].rmidi->name),
2139 "%s MTC %d", card->id, id+1);
2140 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2142 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2146 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2158 while (i < hdspm->midiPorts) {
2159 if (hdspm->midi[i].pending)
2160 snd_hdspm_midi_input_read(&hdspm->midi[i]);
2167 /*-----------------------------------------------------------------------------
2169 ----------------------------------------------------------------------------*/
2197 /* master mode, return internal sample rate */
2198 rate = hdspm->system_sample_rate;
2200 /* slave mode, return external sample rate */
2203 rate = hdspm->system_sample_rate;
2225 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2226 uinfo->count = 1;
2227 uinfo->value.integer.min = 27000;
2228 uinfo->value.integer.max = 207000;
2229 uinfo->value.integer.step = 1;
2240 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2249 int rate = ucontrol->value.integer.value[0];
2252 return -EINVAL;
2253 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2265 switch (hdspm->io_type) {
2289 if (hdspm->tco) {
2290 switch (hdspm->io_type) {
2314 if (hdspm->tco) {
2315 switch (hdspm->io_type) {
2335 switch (hdspm->io_type) {
2400 switch (hdspm->io_type) {
2402 switch (kcontrol->private_value) {
2404 ucontrol->value.enumerated.item[0] =
2408 ucontrol->value.enumerated.item[0] =
2412 ucontrol->value.enumerated.item[0] =
2416 ucontrol->value.enumerated.item[0] =
2418 kcontrol->private_value-1);
2423 switch (kcontrol->private_value) {
2425 ucontrol->value.enumerated.item[0] =
2429 ucontrol->value.enumerated.item[0] =
2433 ucontrol->value.enumerated.item[0] =
2437 ucontrol->value.enumerated.item[0] =
2439 kcontrol->private_value-1);
2445 switch (kcontrol->private_value) {
2447 ucontrol->value.enumerated.item[0] =
2451 ucontrol->value.enumerated.item[0] =
2455 ucontrol->value.enumerated.item[0] =
2459 ucontrol->value.enumerated.item[0] =
2463 ucontrol->value.enumerated.item[0] =
2465 kcontrol->private_value -
2473 ucontrol->value.enumerated.item[0] =
2497 * Returns the system clock mode for the given card.
2498 * @returns 0 - master, 1 - slave
2502 switch (hdspm->io_type) {
2505 if (hdspm->settings_register & HDSPM_c0Master)
2510 if (hdspm->control_register & HDSPM_ClockModeMaster)
2519 * Sets the system clock mode.
2520 * @param mode 0 - master, 1 - slave
2522 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2527 (0 == mode));
2544 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2555 return -EBUSY;
2557 val = ucontrol->value.enumerated.item[0];
2581 switch (hdspm->system_sample_rate) {
2593 return -1;
2596 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2599 switch (mode) {
2636 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2648 return -EBUSY;
2649 val = ucontrol->value.enumerated.item[0];
2654 guard(spinlock_irq)(&hdspm->lock);
2676 * Returns the current preferred sync reference setting.
2682 switch (hdspm->io_type) {
2684 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2701 if (hdspm->tco) {
2702 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2710 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2720 if (hdspm->tco) {
2721 switch ((hdspm->settings_register &
2734 switch ((hdspm->settings_register &
2750 if (hdspm->tco) {
2751 switch ((hdspm->settings_register &
2761 switch ((hdspm->settings_register &
2774 return -1;
2779 * Set the preferred sync reference to <pref>. The semantics
2787 switch (hdspm->io_type) {
2789 hdspm->control_register &= ~HDSPM_SyncRefMask;
2794 hdspm->control_register |= HDSPM_SyncRef0;
2797 hdspm->control_register |= HDSPM_SyncRef1;
2800 hdspm->control_register |=
2804 hdspm->control_register |= HDSPM_SyncRef2;
2807 hdspm->control_register |=
2811 hdspm->control_register |=
2815 hdspm->control_register |=
2819 hdspm->control_register |= HDSPM_SyncRef3;
2822 hdspm->control_register |=
2826 return -1;
2833 hdspm->control_register &= ~HDSPM_SyncRefMask;
2834 if (hdspm->tco) {
2839 hdspm->control_register |= HDSPM_SyncRef0;
2842 hdspm->control_register |= HDSPM_SyncRef1;
2845 hdspm->control_register |=
2849 return -1;
2856 hdspm->control_register |= HDSPM_SyncRef0;
2859 hdspm->control_register |=
2863 return -1;
2870 if (hdspm->tco) {
2881 default: return -1;
2893 default: return -1;
2899 if (hdspm->tco) {
2907 default: return -1;
2916 default: return -1;
2922 switch (hdspm->io_type) {
2925 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2926 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2927 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2934 hdspm->control_register);
2946 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2958 ucontrol->value.enumerated.item[0] = psf;
2962 return -1;
2972 return -EBUSY;
2974 val = ucontrol->value.enumerated.item[0];
2978 else if (val >= hdspm->texts_autosync_items)
2979 val = hdspm->texts_autosync_items-1;
2981 guard(spinlock_irq)(&hdspm->lock);
3000 /* This looks at the autosync selected sync reference */
3001 if (AES32 == hdspm->io_type) {
3011 } else if (MADI == hdspm->io_type) {
3039 if (AES32 == hdspm->io_type) {
3041 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3044 } else if (MADI == hdspm->io_type) {
3046 "Sync In", "None" };
3058 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3076 static const char *const texts[] = {"No video", "NTSC", "PAL"};
3100 /* no video */
3104 ucontrol->value.enumerated.item[0] = ret;
3122 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3164 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3182 reg = hdspm->settings_register;
3184 reg = hdspm->control_register;
3195 reg = &(hdspm->settings_register);
3198 reg = &(hdspm->control_register);
3218 u32 regmask = kcontrol->private_value;
3220 guard(spinlock_irq)(&hdspm->lock);
3221 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3229 u32 regmask = kcontrol->private_value;
3234 return -EBUSY;
3235 val = ucontrol->value.integer.value[0] & 1;
3236 guard(spinlock_irq)(&hdspm->lock);
3253 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3259 hdspm->control_register |= HDSPM_InputSelect0;
3261 hdspm->control_register &= ~HDSPM_InputSelect0;
3262 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3280 guard(spinlock_irq)(&hdspm->lock);
3281 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3293 return -EBUSY;
3294 val = ucontrol->value.integer.value[0] & 1;
3295 guard(spinlock_irq)(&hdspm->lock);
3313 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3319 hdspm->control_register |= HDSPM_DS_DoubleWire;
3321 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3322 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3340 guard(spinlock_irq)(&hdspm->lock);
3341 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3353 return -EBUSY;
3354 val = ucontrol->value.integer.value[0] & 1;
3355 guard(spinlock_irq)(&hdspm->lock);
3373 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3375 if (hdspm->control_register & HDSPM_QS_QuadWire)
3380 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3382 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3383 switch (mode) {
3387 hdspm->control_register |= HDSPM_QS_DoubleWire;
3390 hdspm->control_register |= HDSPM_QS_QuadWire;
3393 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3411 guard(spinlock_irq)(&hdspm->lock);
3412 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3424 return -EBUSY;
3425 val = ucontrol->value.integer.value[0];
3430 guard(spinlock_irq)(&hdspm->lock);
3447 u32 reg = hdspm->settings_register & (regmask * 3);
3451 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3453 hdspm->settings_register &= ~(regmask * 3);
3454 hdspm->settings_register |= (regmask * mode);
3455 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3463 u32 regmask = kcontrol->private_value;
3466 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3483 u32 regmask = kcontrol->private_value;
3485 guard(spinlock_irq)(&hdspm->lock);
3486 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3494 u32 regmask = kcontrol->private_value;
3499 return -EBUSY;
3500 val = ucontrol->value.integer.value[0];
3506 guard(spinlock_irq)(&hdspm->lock);
3523 if (hdspm->control_register & HDSPM_QuadSpeed)
3525 if (hdspm->control_register & HDSPM_DoubleSpeed)
3530 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3532 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3533 switch (mode) {
3537 hdspm->control_register |= HDSPM_DoubleSpeed;
3540 hdspm->control_register |= HDSPM_QuadSpeed;
3543 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3561 guard(spinlock_irq)(&hdspm->lock);
3562 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3574 return -EBUSY;
3575 val = ucontrol->value.integer.value[0];
3580 guard(spinlock_irq)(&hdspm->lock);
3601 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3602 uinfo->count = 3;
3603 uinfo->value.integer.min = 0;
3604 uinfo->value.integer.max = 65535;
3605 uinfo->value.integer.step = 1;
3616 source = ucontrol->value.integer.value[0];
3620 source = 2 * HDSPM_MAX_CHANNELS - 1;
3622 destination = ucontrol->value.integer.value[1];
3626 destination = HDSPM_MAX_CHANNELS - 1;
3628 guard(spinlock_irq)(&hdspm->lock);
3630 ucontrol->value.integer.value[2] =
3632 source - HDSPM_MAX_CHANNELS);
3634 ucontrol->value.integer.value[2] =
3650 return -EBUSY;
3652 source = ucontrol->value.integer.value[0];
3653 destination = ucontrol->value.integer.value[1];
3656 return -1;
3658 return -1;
3660 gain = ucontrol->value.integer.value[2];
3662 guard(spinlock_irq)(&hdspm->lock);
3666 source -
3675 source - HDSPM_MAX_CHANNELS,
3702 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3703 uinfo->count = 1;
3704 uinfo->value.integer.min = 0;
3705 uinfo->value.integer.max = 64;
3706 uinfo->value.integer.step = 1;
3716 channel = ucontrol->id.index - 1;
3719 return -EINVAL;
3721 guard(spinlock_irq)(&hdspm->lock);
3722 ucontrol->value.integer.value[0] =
3737 return -EBUSY;
3739 channel = ucontrol->id.index - 1;
3742 return -EINVAL;
3744 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3746 guard(spinlock_irq)(&hdspm->lock);
3779 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3787 static const char *const texts[] = { "No Lock", "Lock" };
3796 switch (hdspm->io_type) {
3851 int status, lock, sync;
3856 sync = (status & (0x100<<idx)) ? 1 : 0;
3858 if (lock && sync)
3868 int status, lock = 0, sync = 0;
3870 switch (hdspm->io_type) {
3875 sync = (status & 0x800) ? 1 : 0;
3881 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3887 sync = (status & 0x200000) ? 1 : 0;
3894 if (lock && sync)
3904 int status2, lock, sync;
3908 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3910 if (sync)
3930 if (hdspm->tco) {
3931 switch (hdspm->io_type) {
3955 return 2; /* Sync */
3958 return 0; /* No signal */
3973 int val = -1;
3975 switch (hdspm->io_type) {
3977 switch (kcontrol->private_value) {
3982 case 8: /* SYNC IN */
3986 kcontrol->private_value-1);
3991 switch (kcontrol->private_value) {
3996 case 5: /* SYNC IN */
4000 kcontrol->private_value-1);
4005 switch (kcontrol->private_value) {
4022 switch (kcontrol->private_value) {
4027 case 10 /* SYNC IN */:
4031 kcontrol->private_value-1);
4037 if (hdspm->tco) {
4038 switch (kcontrol->private_value) {
4053 if (-1 == val)
4056 ucontrol->value.enumerated.item[0] = val;
4069 switch (hdspm->tco->input) {
4080 switch (hdspm->tco->framerate) {
4104 switch (hdspm->tco->wordclock) {
4115 switch (hdspm->tco->samplerate) {
4126 switch (hdspm->tco->pull) {
4143 if (1 == hdspm->tco->term) {
4168 /* TODO freq from app could be supported here, see tco->samplerate */
4179 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4189 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4190 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4215 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4216 "+ 4 %", "- 4 %" };
4226 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4236 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4237 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4261 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4271 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4281 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4282 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4318 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4328 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4329 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4364 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4374 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4375 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4400 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4401 uinfo->count = 1;
4402 uinfo->value.integer.min = 0;
4403 uinfo->value.integer.max = 1;
4414 ucontrol->value.integer.value[0] = hdspm->tco->term;
4425 if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4426 hdspm->tco->term = ucontrol->value.integer.value[0];
4442 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4443 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4450 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4452 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4455 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4457 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4464 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4468 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4470 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4471 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4477 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4478 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4486 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4492 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4518 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4519 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4529 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4538 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4546 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4547 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4551 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4552 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4553 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4554 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4555 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4556 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4557 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4558 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4559 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4560 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4561 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4572 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4578 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4579 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4590 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4606 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4607 if (hdspm->system_sample_rate > 48000) {
4608 hdspm->playback_mixer_ctls[i]->vd[0].access =
4613 hdspm->playback_mixer_ctls[i]->vd[0].access =
4617 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4619 &hdspm->playback_mixer_ctls[i]->id);
4634 switch (hdspm->io_type) {
4669 if (hdspm->system_sample_rate >= 128000) {
4670 limit = hdspm->qs_out_channels;
4671 } else if (hdspm->system_sample_rate >= 64000) {
4672 limit = hdspm->ds_out_channels;
4674 limit = hdspm->ss_out_channels;
4682 hdspm->playback_mixer_ctls[idx] = kctl;
4686 if (hdspm->tco) {
4701 /*------------------------------------------------------------
4703 ------------------------------------------------------------*/
4709 struct hdspm *hdspm = entry->private_data;
4716 snd_iprintf(buffer, "--- TCO ---\n");
4719 control = hdspm->control_register;
4748 snd_iprintf(buffer, " no LTC\n");
4755 snd_iprintf(buffer, " No video\n");
4758 snd_iprintf(buffer, " Sync: lock\n");
4760 snd_iprintf(buffer, " Sync: no lock\n");
4763 switch (hdspm->io_type) {
4773 break; /* no TCO possible */
4813 snd_iprintf(buffer, "No TCO module detected.\n");
4821 struct hdspm *hdspm = entry->private_data;
4833 hdspm->card_name, hdspm->card->number + 1,
4834 hdspm->firmware_rev,
4841 hdspm->serial);
4844 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4846 snd_iprintf(buffer, "--- System ---\n");
4853 hdspm->irq_count);
4855 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4860 (2 * (int)hdspm->period_bytes),
4861 ((status & HDSPM_BufferPositionMask) - 64) %
4862 (2 * (int)hdspm->period_bytes),
4878 hdspm->control_register, hdspm->control2_register,
4882 snd_iprintf(buffer, "--- Settings ---\n");
4888 x, (unsigned long) hdspm->period_bytes);
4891 str_on_off(hdspm->control_register & HDSPM_LineOut));
4894 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4896 str_on_off(hdspm->control_register & HDSPM_clr_tms),
4897 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4898 str_on_off(hdspm->control_register & HDSPM_AutoInp));
4901 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4912 pref_sync_ref = "MADI Sync";
4918 pref_sync_ref = "Sync In";
4924 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4928 hdspm->system_sample_rate);
4931 snd_iprintf(buffer, "--- Status:\n");
4937 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4939 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4944 autosync_ref = "Sync In";
4953 autosync_ref = "MADI Sync";
4959 autosync_ref = "---";
4968 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
4983 struct hdspm *hdspm = entry->private_data;
4997 hdspm->card_name, hdspm->card->number + 1,
4998 hdspm->firmware_rev);
5001 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5003 snd_iprintf(buffer, "--- System ---\n");
5010 hdspm->irq_count);
5012 "HW pointer: id = %d, rawptr = %d (%d->%d) "
5017 (2 * (int)hdspm->period_bytes),
5018 ((status & HDSPM_BufferPositionMask) - 64) %
5019 (2 * (int)hdspm->period_bytes),
5035 hdspm->control_register, hdspm->control2_register,
5038 snd_iprintf(buffer, "--- Settings ---\n");
5044 x, (unsigned long) hdspm->period_bytes);
5047 (hdspm->
5052 str_on_off(hdspm->control_register & HDSPM_clr_tms),
5053 str_on_off(hdspm->control_register & HDSPM_Emphasis),
5054 str_on_off(hdspm->control_register & HDSPM_Dolby));
5059 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5061 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5065 hdspm->system_sample_rate);
5068 hdspm->control_register & HDSPM_DS_DoubleWire?
5071 hdspm->control_register & HDSPM_QS_DoubleWire?
5073 hdspm->control_register & HDSPM_QS_QuadWire?
5076 snd_iprintf(buffer, "--- Status:\n");
5082 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
5089 "Sync " : "No Lock",
5117 autosync_ref = "Sync In"; break;
5119 autosync_ref = "---"; break;
5133 struct hdspm *hdspm = entry->private_data;
5135 unsigned int lock, sync;
5146 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5148 snd_iprintf(buffer, "Clock mode : %s\n",
5156 sync = 0x100;
5159 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5162 (status1 & sync) ? 1 : 0,
5166 sync = sync<<1;
5169 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5174 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5179 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5191 struct hdspm *hdspm = entry->private_data;
5208 struct hdspm *hdspm = entry->private_data;
5213 for (i = 0; i < hdspm->max_channels_in; i++) {
5214 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5221 struct hdspm *hdspm = entry->private_data;
5226 for (i = 0; i < hdspm->max_channels_out; i++) {
5227 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5236 switch (hdspm->io_type) {
5253 snd_card_ro_proc_new(hdspm->card, "hdspm", hdspm, read);
5254 snd_card_ro_proc_new(hdspm->card, "ports.in", hdspm,
5256 snd_card_ro_proc_new(hdspm->card, "ports.out", hdspm,
5261 snd_card_ro_proc_new(hdspm->card, "debug", hdspm,
5266 /*------------------------------------------------------------
5268 ------------------------------------------------------------*/
5272 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5278 hdspm->settings_register = 0;
5280 switch (hdspm->io_type) {
5283 hdspm->control_register =
5289 hdspm->settings_register = 0x1 + 0x1000;
5292 hdspm->control_register =
5297 hdspm->control_register =
5298 HDSPM_ClockModeMaster | /* Master Clock Mode on */
5302 HDSPM_Professional; /* Professional mode */
5306 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5308 if (AES32 == hdspm->io_type) {
5309 /* No control2 register for AES32 */
5311 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5313 hdspm->control2_register = 0;
5316 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5325 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5334 /*------------------------------------------------------------
5336 ------------------------------------------------------------*/
5363 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5364 now-hdspm->last_interrupt, status & 0xFFC0);
5365 hdspm->last_interrupt = now;
5372 hdspm->irq_count++;
5376 if (hdspm->capture_substream)
5377 snd_pcm_period_elapsed(hdspm->capture_substream);
5379 if (hdspm->playback_substream)
5380 snd_pcm_period_elapsed(hdspm->playback_substream);
5385 while (i < hdspm->midiPorts) {
5387 hdspm->midi[i].statusIn) & 0xff) &&
5388 (status & hdspm->midi[i].irq)) {
5392 hdspm->control_register &= ~hdspm->midi[i].ie;
5394 hdspm->control_register);
5395 hdspm->midi[i].pending = 1;
5403 queue_work(system_highpri_wq, &hdspm->midi_work);
5409 /*------------------------------------------------------------
5411 ------------------------------------------------------------*/
5424 struct snd_pcm_runtime *runtime = substream->runtime;
5428 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5429 other = hdspm->capture_substream;
5431 other = hdspm->playback_substream;
5433 if (hdspm->running)
5434 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5436 runtime->status->hw_ptr = 0;
5439 struct snd_pcm_runtime *oruntime = other->runtime;
5442 oruntime->status->hw_ptr =
5443 runtime->status->hw_ptr;
5460 scoped_guard(spinlock_irq, &hdspm->lock) {
5462 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5463 this_pid = hdspm->playback_pid;
5464 other_pid = hdspm->capture_pid;
5466 this_pid = hdspm->capture_pid;
5467 other_pid = hdspm->playback_pid;
5477 if (params_rate(params) != hdspm->system_sample_rate) {
5480 return -EBUSY;
5483 if (params_period_size(params) != hdspm->period_bytes / 4) {
5486 return -EBUSY;
5493 /* how to make sure that the rate matches an externally-set one ? */
5495 scoped_guard(spinlock_irq, &hdspm->lock) {
5498 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5508 dev_info(hdspm->card->dev,
5525 dev_info(hdspm->card->dev,
5530 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5533 int c = hdspm->channel_map_out[i];
5543 hdspm->playback_buffer =
5544 (unsigned char *) substream->runtime->dma_area;
5545 dev_dbg(hdspm->card->dev,
5547 hdspm->playback_buffer);
5550 int c = hdspm->channel_map_in[i];
5560 hdspm->capture_buffer =
5561 (unsigned char *) substream->runtime->dma_area;
5562 dev_dbg(hdspm->card->dev,
5564 hdspm->capture_buffer);
5568 dev_dbg(hdspm->card->dev,
5570 snd_pcm_direction_name(substream->stream),
5574 dev_dbg(hdspm->card->dev,
5576 snd_pcm_direction_name(substream->stream),
5583 * preferred sync reference. Since we don't want to break
5584 * sync settings, we have to skip the remaining part of this
5587 if (hdspm->io_type == AES32) {
5594 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5595 dev_info(hdspm->card->dev,
5598 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5600 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5601 dev_info(hdspm->card->dev,
5604 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5606 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5616 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5622 hdspm->playback_buffer = NULL;
5627 hdspm->capture_buffer = NULL;
5640 unsigned int channel = info->channel;
5642 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5643 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) {
5644 dev_info(hdspm->card->dev,
5647 return -EINVAL;
5650 channel = array_index_nospec(channel, hdspm->max_channels_out);
5651 if (hdspm->channel_map_out[channel] < 0) {
5652 dev_info(hdspm->card->dev,
5655 return -EINVAL;
5658 info->offset = hdspm->channel_map_out[channel] *
5661 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) {
5662 dev_info(hdspm->card->dev,
5665 return -EINVAL;
5668 channel = array_index_nospec(channel, hdspm->max_channels_in);
5669 if (hdspm->channel_map_in[channel] < 0) {
5670 dev_info(hdspm->card->dev,
5673 return -EINVAL;
5676 info->offset = hdspm->channel_map_in[channel] *
5680 info->first = 0;
5681 info->step = 32;
5711 guard(spinlock)(&hdspm->lock);
5712 running = hdspm->running;
5715 running |= 1 << substream->stream;
5718 running &= ~(1 << substream->stream);
5722 return -EINVAL;
5724 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5725 other = hdspm->capture_substream;
5727 other = hdspm->playback_substream;
5735 running |= 1 << s->stream;
5737 running &= ~(1 << s->stream);
5743 && substream->stream ==
5748 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5752 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5757 if (!hdspm->running && running)
5759 else if (hdspm->running && !running)
5761 hdspm->running = running;
5824 struct hdspm *hdspm = rule->private;
5830 if (r->min > 96000 && r->max <= 192000) {
5832 .min = hdspm->qs_in_channels,
5833 .max = hdspm->qs_in_channels,
5837 } else if (r->min > 48000 && r->max <= 96000) {
5839 .min = hdspm->ds_in_channels,
5840 .max = hdspm->ds_in_channels,
5844 } else if (r->max < 64000) {
5846 .min = hdspm->ss_in_channels,
5847 .max = hdspm->ss_in_channels,
5859 struct hdspm *hdspm = rule->private;
5865 if (r->min > 96000 && r->max <= 192000) {
5867 .min = hdspm->qs_out_channels,
5868 .max = hdspm->qs_out_channels,
5872 } else if (r->min > 48000 && r->max <= 96000) {
5874 .min = hdspm->ds_out_channels,
5875 .max = hdspm->ds_out_channels,
5879 } else if (r->max < 64000) {
5881 .min = hdspm->ss_out_channels,
5882 .max = hdspm->ss_out_channels,
5894 struct hdspm *hdspm = rule->private;
5900 if (c->min >= hdspm->ss_in_channels) {
5907 } else if (c->max <= hdspm->qs_in_channels) {
5914 } else if (c->max <= hdspm->ds_in_channels) {
5928 struct hdspm *hdspm = rule->private;
5934 if (c->min >= hdspm->ss_out_channels) {
5941 } else if (c->max <= hdspm->qs_out_channels) {
5948 } else if (c->max <= hdspm->ds_out_channels) {
5964 struct hdspm *hdspm = rule->private;
5968 list[0] = hdspm->qs_in_channels;
5969 list[1] = hdspm->ds_in_channels;
5970 list[2] = hdspm->ss_in_channels;
5978 struct hdspm *hdspm = rule->private;
5982 list[0] = hdspm->qs_out_channels;
5983 list[1] = hdspm->ds_out_channels;
5984 list[2] = hdspm->ss_out_channels;
5991 struct snd_pcm_runtime *runtime = substream->runtime;
5992 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
5994 scoped_guard(spinlock_irq, &hdspm->lock) {
5996 runtime->hw = (playback) ? snd_hdspm_playback_subinfo :
6000 if (!hdspm->capture_substream)
6003 hdspm->playback_pid = current->pid;
6004 hdspm->playback_substream = substream;
6006 if (!hdspm->playback_substream)
6009 hdspm->capture_pid = current->pid;
6010 hdspm->capture_substream = substream;
6017 switch (hdspm->io_type) {
6038 if (AES32 == hdspm->io_type) {
6039 runtime->hw.rates |= SNDRV_PCM_RATE_128000;
6045 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6051 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6056 SNDRV_PCM_HW_PARAM_RATE, -1);
6064 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6066 guard(spinlock_irq)(&hdspm->lock);
6069 hdspm->playback_pid = -1;
6070 hdspm->playback_substream = NULL;
6072 hdspm->capture_pid = -1;
6073 hdspm->capture_substream = NULL;
6089 struct hdspm *hdspm = hw->private_data;
6103 levels = &hdspm->peak_rms;
6105 levels->input_peaks[i] =
6106 readl(hdspm->iobase +
6108 levels->playback_peaks[i] =
6109 readl(hdspm->iobase +
6111 levels->output_peaks[i] =
6112 readl(hdspm->iobase +
6115 levels->input_rms[i] =
6116 ((uint64_t) readl(hdspm->iobase +
6118 (uint64_t) readl(hdspm->iobase +
6120 levels->playback_rms[i] =
6121 ((uint64_t)readl(hdspm->iobase +
6123 (uint64_t)readl(hdspm->iobase +
6125 levels->output_rms[i] =
6126 ((uint64_t)readl(hdspm->iobase +
6128 (uint64_t)readl(hdspm->iobase +
6132 if (hdspm->system_sample_rate > 96000) {
6133 levels->speed = qs;
6134 } else if (hdspm->system_sample_rate > 48000) {
6135 levels->speed = ds;
6137 levels->speed = ss;
6139 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6143 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6146 return -EFAULT;
6189 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6190 return -EFAULT;
6198 scoped_guard(spinlock_irq, &hdspm->lock) {
6202 info.system_sample_rate = hdspm->system_sample_rate;
6212 return -EFAULT;
6218 status.card_type = hdspm->io_type;
6225 switch (hdspm->io_type) {
6252 return -EFAULT;
6260 hdspm_version.card_type = hdspm->io_type;
6261 strscpy(hdspm_version.cardname, hdspm->card_name,
6263 hdspm_version.serial = hdspm->serial;
6264 hdspm_version.firmware_rev = hdspm->firmware_rev;
6266 if (hdspm->tco)
6271 return -EFAULT;
6276 return -EFAULT;
6277 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6279 return -EFAULT;
6283 return -EINVAL;
6309 hdspm->hwdep = hw;
6310 hw->private_data = hdspm;
6311 strscpy(hw->name, "HDSPM hwdep interface");
6313 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6314 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6315 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6316 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6322 /*------------------------------------------------------------
6324 ------------------------------------------------------------*/
6330 pcm = hdspm->pcm;
6335 &hdspm->pci->dev,
6337 dev_dbg(hdspm->card->dev, " Preallocated %zd Bytes\n", wanted);
6355 /* ------------- ALSA Devices ---------------------------- */
6362 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6366 hdspm->pcm = pcm;
6367 pcm->private_data = hdspm;
6368 strscpy(pcm->name, hdspm->card_name);
6375 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6388 for (i = 0; i < hdspm->midiPorts; i++)
6397 dev_dbg(card->dev, "Create card...\n");
6403 while (i < hdspm->midiPorts) {
6419 dev_dbg(card->dev, "proc init...\n");
6422 hdspm->system_sample_rate = -1;
6423 hdspm->last_external_sample_rate = -1;
6424 hdspm->last_internal_sample_rate = -1;
6425 hdspm->playback_pid = -1;
6426 hdspm->capture_pid = -1;
6427 hdspm->capture_substream = NULL;
6428 hdspm->playback_substream = NULL;
6430 dev_dbg(card->dev, "Set defaults...\n");
6435 dev_dbg(card->dev, "Update mixer controls...\n");
6438 dev_dbg(card->dev, "Initializing complete?\n");
6442 dev_err(card->dev, "error registering card\n");
6446 dev_dbg(card->dev, "... yes now\n");
6455 struct pci_dev *pci = hdspm->pci;
6459 hdspm->irq = -1;
6460 hdspm->card = card;
6462 spin_lock_init(&hdspm->lock);
6463 INIT_WORK(&hdspm->midi_work, hdspm_midi_work);
6465 pci_read_config_word(hdspm->pci,
6466 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6468 strscpy(card->mixername, "Xilinx FPGA");
6469 strscpy(card->driver, "HDSPM");
6471 switch (hdspm->firmware_rev) {
6473 hdspm->io_type = RayDAT;
6474 hdspm->card_name = "RME RayDAT";
6475 hdspm->midiPorts = 2;
6478 hdspm->io_type = AIO;
6479 hdspm->card_name = "RME AIO";
6480 hdspm->midiPorts = 1;
6483 hdspm->io_type = MADIface;
6484 hdspm->card_name = "RME MADIface";
6485 hdspm->midiPorts = 1;
6488 if ((hdspm->firmware_rev == 0xf0) ||
6489 ((hdspm->firmware_rev >= 0xe6) &&
6490 (hdspm->firmware_rev <= 0xea))) {
6491 hdspm->io_type = AES32;
6492 hdspm->card_name = "RME AES32";
6493 hdspm->midiPorts = 2;
6494 } else if ((hdspm->firmware_rev == 0xd2) ||
6495 ((hdspm->firmware_rev >= 0xc8) &&
6496 (hdspm->firmware_rev <= 0xcf))) {
6497 hdspm->io_type = MADI;
6498 hdspm->card_name = "RME MADI";
6499 hdspm->midiPorts = 3;
6501 dev_err(card->dev,
6503 hdspm->firmware_rev);
6504 return -ENODEV;
6512 pci_set_master(hdspm->pci);
6514 hdspm->iobase = pcim_iomap_region(pci, 0, "hdspm");
6515 if (IS_ERR(hdspm->iobase))
6516 return PTR_ERR(hdspm->iobase);
6518 hdspm->port = pci_resource_start(pci, 0);
6520 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
6521 (unsigned long)hdspm->iobase, hdspm->port,
6522 hdspm->port + io_extent - 1);
6524 if (devm_request_irq(&pci->dev, pci->irq, snd_hdspm_interrupt,
6526 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
6527 return -EBUSY;
6530 dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
6532 hdspm->irq = pci->irq;
6533 card->sync_irq = hdspm->irq;
6535 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
6536 sizeof(*hdspm->mixer));
6537 hdspm->mixer = devm_kzalloc(&pci->dev, sizeof(*hdspm->mixer), GFP_KERNEL);
6538 if (!hdspm->mixer)
6539 return -ENOMEM;
6541 hdspm->port_names_in = NULL;
6542 hdspm->port_names_out = NULL;
6544 switch (hdspm->io_type) {
6546 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6547 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6548 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6550 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6552 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6554 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6556 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6558 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6560 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6563 hdspm->max_channels_out = hdspm->max_channels_in =
6565 hdspm->port_names_in = hdspm->port_names_out =
6567 hdspm->channel_map_in = hdspm->channel_map_out =
6574 hdspm->ss_in_channels = hdspm->ss_out_channels =
6576 hdspm->ds_in_channels = hdspm->ds_out_channels =
6578 hdspm->qs_in_channels = hdspm->qs_out_channels =
6581 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6583 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6585 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6588 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6590 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6592 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6597 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6598 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6599 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6600 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6601 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6602 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6605 dev_info(card->dev, "AEB input board found\n");
6606 hdspm->ss_in_channels += 4;
6607 hdspm->ds_in_channels += 4;
6608 hdspm->qs_in_channels += 4;
6612 dev_info(card->dev, "AEB output board found\n");
6613 hdspm->ss_out_channels += 4;
6614 hdspm->ds_out_channels += 4;
6615 hdspm->qs_out_channels += 4;
6618 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6619 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6620 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6622 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6623 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6624 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6626 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6627 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6628 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6629 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6630 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6631 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6636 hdspm->ss_in_channels = hdspm->ss_out_channels =
6638 hdspm->ds_in_channels = hdspm->ds_out_channels =
6640 hdspm->qs_in_channels = hdspm->qs_out_channels =
6643 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6644 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6646 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6648 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6650 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6652 hdspm->channel_map_in = hdspm->channel_map_out =
6655 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6657 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6659 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6668 switch (hdspm->io_type) {
6673 hdspm->midiPorts++;
6674 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6675 if (hdspm->tco)
6678 dev_info(card->dev, "AIO/RayDAT TCO module found\n");
6680 hdspm->tco = NULL;
6687 hdspm->midiPorts++;
6688 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6689 if (hdspm->tco)
6692 dev_info(card->dev, "MADI/AES TCO module found\n");
6694 hdspm->tco = NULL;
6699 hdspm->tco = NULL;
6703 switch (hdspm->io_type) {
6705 if (hdspm->tco) {
6706 hdspm->texts_autosync = texts_autosync_aes_tco;
6707 hdspm->texts_autosync_items =
6710 hdspm->texts_autosync = texts_autosync_aes;
6711 hdspm->texts_autosync_items =
6717 if (hdspm->tco) {
6718 hdspm->texts_autosync = texts_autosync_madi_tco;
6719 hdspm->texts_autosync_items = 4;
6721 hdspm->texts_autosync = texts_autosync_madi;
6722 hdspm->texts_autosync_items = 3;
6731 if (hdspm->tco) {
6732 hdspm->texts_autosync = texts_autosync_raydat_tco;
6733 hdspm->texts_autosync_items = 9;
6735 hdspm->texts_autosync = texts_autosync_raydat;
6736 hdspm->texts_autosync_items = 8;
6741 if (hdspm->tco) {
6742 hdspm->texts_autosync = texts_autosync_aio_tco;
6743 hdspm->texts_autosync_items = 6;
6745 hdspm->texts_autosync = texts_autosync_aio;
6746 hdspm->texts_autosync_items = 5;
6752 if (hdspm->io_type != MADIface) {
6753 hdspm->serial = (hdspm_read(hdspm,
6755 /* id contains either a user-provided value or the default
6757 * fill card->id with the serial number.
6761 * this case, we don't set card->id to avoid collisions
6764 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6765 snprintf(card->id, sizeof(card->id),
6766 "HDSPMx%06x", hdspm->serial);
6767 snd_card_set_id(card, card->id);
6771 dev_dbg(card->dev, "create alsa devices.\n");
6784 struct hdspm *hdspm = card->private_data;
6786 if (hdspm->port) {
6787 cancel_work_sync(&hdspm->midi_work);
6790 hdspm->control_register &=
6795 hdspm->control_register);
6809 return -ENODEV;
6812 return -ENOENT;
6815 err = snd_devm_card_new(&pci->dev, index[dev], id[dev],
6820 hdspm = card->private_data;
6821 card->private_free = snd_hdspm_card_free;
6822 hdspm->dev = dev;
6823 hdspm->pci = pci;
6829 if (hdspm->io_type != MADIface) {
6830 snprintf(card->shortname, sizeof(card->shortname), "%s_%x",
6831 hdspm->card_name, hdspm->serial);
6832 snprintf(card->longname, sizeof(card->longname),
6834 hdspm->card_name, hdspm->serial,
6835 hdspm->port, hdspm->irq);
6837 snprintf(card->shortname, sizeof(card->shortname), "%s",
6838 hdspm->card_name);
6839 snprintf(card->longname, sizeof(card->longname),
6841 hdspm->card_name, hdspm->port, hdspm->irq);