Lines Matching +full:min +full:- +full:sample +full:- +full:rate +full:- +full:hz
1 // SPDX-License-Identifier: GPL-2.0-or-later
35 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
254 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
255 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
256 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
257 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
258 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
259 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
260 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
261 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
262 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
296 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
297 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
303 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
304 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
313 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
325 if (copy_from_iter_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
327 return -EFAULT;
338 if (copy_to_iter_fromio(rme96->iobase + RME96_IO_REC_BUFFER + pos,
340 return -EFAULT;
467 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
479 rme96->areg |= RME96_AR_CDATA;
481 rme96->areg &= ~RME96_AR_CDATA;
483 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
484 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
486 rme96->areg |= RME96_AR_CCLK;
487 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
491 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
492 rme96->areg |= RME96_AR_CLATCH;
493 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
495 rme96->areg &= ~RME96_AR_CLATCH;
496 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
503 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
504 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
506 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
507 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
514 writel(rme96->wcreg | RME96_WCR_PD,
515 rme96->iobase + RME96_IO_CONTROL_REGISTER);
516 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
522 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
523 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
531 rme96->wcreg |= RME96_WCR_MONITOR_0;
533 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
536 rme96->wcreg |= RME96_WCR_MONITOR_1;
538 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
540 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
547 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
548 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
557 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
561 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
565 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
569 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
573 return -EINVAL;
575 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
583 int n, rate;
586 if (rme96->areg & RME96_AR_ANALOG) {
588 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
589 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
592 rate = 32000;
595 rate = 44100;
598 rate = 48000;
601 return -1;
603 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
606 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
607 if (rme96->rcreg & RME96_RCR_LOCK) {
608 /* ADAT rate */
610 if (rme96->rcreg & RME96_RCR_T_OUT) {
616 if (rme96->rcreg & RME96_RCR_VERF) {
617 return -1;
620 /* S/PDIF rate */
621 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
622 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
623 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
627 if (rme96->rcreg & RME96_RCR_T_OUT) {
630 return -1;
639 return -1;
645 int rate, dummy;
647 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
649 rate = snd_rme96_capture_getrate(rme96, &dummy);
650 if (rate > 0) {
652 return rate;
656 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
657 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
658 switch (rate) {
660 rate = 32000;
663 rate = 44100;
666 rate = 48000;
669 return -1;
671 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
676 int rate)
680 ds = rme96->wcreg & RME96_WCR_DS;
681 switch (rate) {
683 rme96->wcreg &= ~RME96_WCR_DS;
684 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
688 rme96->wcreg &= ~RME96_WCR_DS;
689 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
693 rme96->wcreg &= ~RME96_WCR_DS;
694 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
698 rme96->wcreg |= RME96_WCR_DS;
699 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
703 rme96->wcreg |= RME96_WCR_DS;
704 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
708 rme96->wcreg |= RME96_WCR_DS;
709 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
713 return -EINVAL;
715 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
716 (ds && !(rme96->wcreg & RME96_WCR_DS)))
718 /* change to/from double-speed: reset the DAC (if available) */
722 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
729 int rate)
731 switch (rate) {
733 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
737 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
741 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
745 if (rme96->rev < 4) {
746 return -EINVAL;
748 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
752 if (rme96->rev < 4) {
753 return -EINVAL;
755 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
759 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
763 return -EINVAL;
765 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
776 rme96->wcreg &= ~RME96_WCR_MASTER;
777 rme96->areg &= ~RME96_AR_WSEL;
781 rme96->wcreg |= RME96_WCR_MASTER;
782 rme96->areg &= ~RME96_AR_WSEL;
786 rme96->wcreg |= RME96_WCR_MASTER;
787 rme96->areg |= RME96_AR_WSEL;
790 return -EINVAL;
792 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
793 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
800 if (rme96->areg & RME96_AR_WSEL) {
803 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
815 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
819 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
823 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
827 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
828 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
829 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
830 rme96->rev > 4))
833 return -EINVAL;
835 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
840 return -EINVAL;
842 rme96->areg |= RME96_AR_ANALOG;
843 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
844 if (rme96->rev < 4) {
858 return -EINVAL;
861 rme96->areg &= ~RME96_AR_ANALOG;
862 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
864 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
871 if (rme96->areg & RME96_AR_ANALOG) {
874 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
875 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
892 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
893 rme96->playback_frlog = frlog;
895 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
896 rme96->capture_frlog = frlog;
905 rme96->wcreg &= ~RME96_WCR_MODE24;
908 rme96->wcreg |= RME96_WCR_MODE24;
911 return -EINVAL;
913 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
922 rme96->wcreg &= ~RME96_WCR_MODE24_2;
925 rme96->wcreg |= RME96_WCR_MODE24_2;
928 return -EINVAL;
930 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
940 rme96->wcreg &= ~RME96_WCR_ISEL;
943 rme96->wcreg |= RME96_WCR_ISEL;
949 rme96->wcreg &= ~RME96_WCR_IDIS;
950 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
958 struct snd_pcm_runtime *runtime = substream->runtime;
959 int err, rate, dummy;
962 runtime->dma_area = (void __force *)(rme96->iobase +
964 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
965 runtime->dma_bytes = RME96_BUFFER_SIZE;
967 spin_lock_irq(&rme96->lock);
968 rate = 0;
969 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
971 rate = snd_rme96_capture_getrate(rme96, &dummy);
972 if (rate > 0) {
974 if ((int)params_rate(params) != rate) {
975 err = -EIO;
989 if (rme96->capture_periodsize != 0) {
990 if (params_period_size(params) << rme96->playback_frlog !=
991 rme96->capture_periodsize)
993 err = -EBUSY;
997 rme96->playback_periodsize =
998 params_period_size(params) << rme96->playback_frlog;
999 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1001 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1002 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1003 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1008 spin_unlock_irq(&rme96->lock);
1022 struct snd_pcm_runtime *runtime = substream->runtime;
1023 int err, isadat, rate;
1025 runtime->dma_area = (void __force *)(rme96->iobase +
1027 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1028 runtime->dma_bytes = RME96_BUFFER_SIZE;
1030 spin_lock_irq(&rme96->lock);
1033 spin_unlock_irq(&rme96->lock);
1039 spin_unlock_irq(&rme96->lock);
1043 rate = snd_rme96_capture_getrate(rme96, &isadat);
1044 if (rate > 0) {
1045 if ((int)params_rate(params) != rate) {
1046 spin_unlock_irq(&rme96->lock);
1047 return -EIO;
1049 if ((isadat && runtime->hw.channels_min == 2) ||
1050 (!isadat && runtime->hw.channels_min == 8)) {
1051 spin_unlock_irq(&rme96->lock);
1052 return -EIO;
1057 if (rme96->playback_periodsize != 0) {
1058 if (params_period_size(params) << rme96->capture_frlog !=
1059 rme96->playback_periodsize)
1061 spin_unlock_irq(&rme96->lock);
1062 return -EBUSY;
1065 rme96->capture_periodsize =
1066 params_period_size(params) << rme96->capture_frlog;
1067 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1068 spin_unlock_irq(&rme96->lock);
1078 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1080 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1082 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1083 if (rme96->rcreg & RME96_RCR_IRQ)
1084 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1087 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1088 if (rme96->rcreg & RME96_RCR_IRQ_2)
1089 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1092 rme96->wcreg |= RME96_WCR_START;
1094 rme96->wcreg &= ~RME96_WCR_START;
1096 rme96->wcreg |= RME96_WCR_START_2;
1098 rme96->wcreg &= ~RME96_WCR_START_2;
1099 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1110 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1112 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1113 (rme96->rcreg & RME96_RCR_IRQ_2)))
1118 if (rme96->rcreg & RME96_RCR_IRQ) {
1120 snd_pcm_period_elapsed(rme96->playback_substream);
1121 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1123 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1125 snd_pcm_period_elapsed(rme96->capture_substream);
1126 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1147 size = rme96->playback_periodsize;
1149 size = rme96->capture_periodsize;
1163 int rate, dummy;
1165 struct snd_pcm_runtime *runtime = substream->runtime;
1168 spin_lock_irq(&rme96->lock);
1169 if (rme96->playback_substream) {
1170 spin_unlock_irq(&rme96->lock);
1171 return -EBUSY;
1173 rme96->wcreg &= ~RME96_WCR_ADAT;
1174 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1175 rme96->playback_substream = substream;
1176 spin_unlock_irq(&rme96->lock);
1178 runtime->hw = snd_rme96_playback_spdif_info;
1179 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1181 rate = snd_rme96_capture_getrate(rme96, &dummy);
1182 if (rate > 0) {
1184 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1185 runtime->hw.rate_min = rate;
1186 runtime->hw.rate_max = rate;
1191 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1192 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1193 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1194 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1201 int isadat, rate;
1203 struct snd_pcm_runtime *runtime = substream->runtime;
1206 runtime->hw = snd_rme96_capture_spdif_info;
1208 rate = snd_rme96_capture_getrate(rme96, &isadat);
1209 if (rate > 0) {
1211 return -EIO;
1212 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1213 runtime->hw.rate_min = rate;
1214 runtime->hw.rate_max = rate;
1218 spin_lock_irq(&rme96->lock);
1219 if (rme96->capture_substream) {
1220 spin_unlock_irq(&rme96->lock);
1221 return -EBUSY;
1223 rme96->capture_substream = substream;
1224 spin_unlock_irq(&rme96->lock);
1233 int rate, dummy;
1235 struct snd_pcm_runtime *runtime = substream->runtime;
1238 spin_lock_irq(&rme96->lock);
1239 if (rme96->playback_substream) {
1240 spin_unlock_irq(&rme96->lock);
1241 return -EBUSY;
1243 rme96->wcreg |= RME96_WCR_ADAT;
1244 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1245 rme96->playback_substream = substream;
1246 spin_unlock_irq(&rme96->lock);
1248 runtime->hw = snd_rme96_playback_adat_info;
1249 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1251 rate = snd_rme96_capture_getrate(rme96, &dummy);
1252 if (rate > 0) {
1254 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1255 runtime->hw.rate_min = rate;
1256 runtime->hw.rate_max = rate;
1267 int isadat, rate;
1269 struct snd_pcm_runtime *runtime = substream->runtime;
1272 runtime->hw = snd_rme96_capture_adat_info;
1275 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1276 return -EIO;
1278 rate = snd_rme96_capture_getrate(rme96, &isadat);
1279 if (rate > 0) {
1281 return -EIO;
1283 runtime->hw.rates = snd_pcm_rate_to_rate_bit(rate);
1284 runtime->hw.rate_min = rate;
1285 runtime->hw.rate_max = rate;
1288 spin_lock_irq(&rme96->lock);
1289 if (rme96->capture_substream) {
1290 spin_unlock_irq(&rme96->lock);
1291 return -EBUSY;
1293 rme96->capture_substream = substream;
1294 spin_unlock_irq(&rme96->lock);
1306 spin_lock_irq(&rme96->lock);
1310 rme96->playback_substream = NULL;
1311 rme96->playback_periodsize = 0;
1312 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1313 spin_unlock_irq(&rme96->lock);
1315 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1316 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1317 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1327 spin_lock_irq(&rme96->lock);
1331 rme96->capture_substream = NULL;
1332 rme96->capture_periodsize = 0;
1333 spin_unlock_irq(&rme96->lock);
1342 spin_lock_irq(&rme96->lock);
1346 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1347 spin_unlock_irq(&rme96->lock);
1356 spin_lock_irq(&rme96->lock);
1360 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1361 spin_unlock_irq(&rme96->lock);
1378 sync = (rme96->playback_substream && rme96->capture_substream) &&
1379 (rme96->playback_substream->group ==
1380 rme96->capture_substream->group);
1385 if (substream != rme96->playback_substream)
1386 return -EBUSY;
1395 if (substream != rme96->playback_substream)
1396 return -EBUSY;
1416 return -EINVAL;
1435 sync = (rme96->playback_substream && rme96->capture_substream) &&
1436 (rme96->playback_substream->group ==
1437 rme96->capture_substream->group);
1442 if (substream != rme96->capture_substream)
1443 return -EBUSY;
1452 if (substream != rme96->capture_substream)
1453 return -EBUSY;
1473 return -EINVAL;
1542 if (rme96->irq >= 0) {
1544 rme96->areg &= ~RME96_AR_DAC_EN;
1545 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1547 vfree(rme96->playback_suspend_buffer);
1548 vfree(rme96->capture_suspend_buffer);
1554 struct rme96 *rme96 = pcm->private_data;
1555 rme96->spdif_pcm = NULL;
1561 struct rme96 *rme96 = pcm->private_data;
1562 rme96->adat_pcm = NULL;
1568 struct pci_dev *pci = rme96->pci;
1571 rme96->irq = -1;
1572 spin_lock_init(&rme96->lock);
1581 rme96->port = pci_resource_start(rme96->pci, 0);
1583 rme96->iobase = devm_ioremap(&pci->dev, rme96->port, RME96_IO_SIZE);
1584 if (!rme96->iobase) {
1585 dev_err(rme96->card->dev,
1586 "unable to remap memory region 0x%lx-0x%lx\n",
1587 rme96->port, rme96->port + RME96_IO_SIZE - 1);
1588 return -EBUSY;
1591 if (devm_request_irq(&pci->dev, pci->irq, snd_rme96_interrupt,
1593 dev_err(rme96->card->dev, "unable to grab IRQ %d\n", pci->irq);
1594 return -EBUSY;
1596 rme96->irq = pci->irq;
1597 rme96->card->sync_irq = rme96->irq;
1600 pci_read_config_byte(pci, 8, &rme96->rev);
1603 err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1604 1, 1, &rme96->spdif_pcm);
1608 rme96->spdif_pcm->private_data = rme96;
1609 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1610 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1611 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1612 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1614 rme96->spdif_pcm->info_flags = 0;
1617 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1619 rme96->adat_pcm = NULL;
1621 err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1622 1, 1, &rme96->adat_pcm);
1625 rme96->adat_pcm->private_data = rme96;
1626 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1627 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1628 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1629 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1631 rme96->adat_pcm->info_flags = 0;
1634 rme96->playback_periodsize = 0;
1635 rme96->capture_periodsize = 0;
1641 rme96->wcreg =
1647 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1649 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1650 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1653 writel(rme96->areg | RME96_AR_PD2,
1654 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1655 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1659 rme96->areg |= RME96_AR_DAC_EN;
1660 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1663 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1664 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1667 rme96->vol[0] = rme96->vol[1] = 0;
1673 err = snd_rme96_create_switches(rme96->card, rme96);
1691 struct rme96 *rme96 = entry->private_data;
1693 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1695 snd_iprintf(buffer, rme96->card->longname);
1696 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1699 if (rme96->wcreg & RME96_WCR_IDIS) {
1702 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1726 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1733 snd_iprintf(buffer, " sample rate: %d Hz\n",
1736 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1737 snd_iprintf(buffer, " sample format: 24 bit\n");
1739 snd_iprintf(buffer, " sample format: 16 bit\n");
1743 if (rme96->wcreg & RME96_WCR_SEL) {
1748 snd_iprintf(buffer, " sample rate: %d Hz\n",
1750 if (rme96->wcreg & RME96_WCR_MODE24) {
1751 snd_iprintf(buffer, " sample format: 24 bit\n");
1753 snd_iprintf(buffer, " sample format: 16 bit\n");
1755 if (rme96->areg & RME96_AR_WSEL) {
1756 snd_iprintf(buffer, " sample clock source: word clock\n");
1757 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1758 snd_iprintf(buffer, " sample clock source: internal\n");
1760 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1762 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1764 snd_iprintf(buffer, " sample clock source: autosync\n");
1766 if (rme96->wcreg & RME96_WCR_PRO) {
1771 if (rme96->wcreg & RME96_WCR_EMP) {
1776 if (rme96->wcreg & RME96_WCR_DOLBY) {
1777 snd_iprintf(buffer, " non-audio (dolby): on\n");
1779 snd_iprintf(buffer, " non-audio (dolby): off\n");
1802 snd_iprintf(buffer, " attenuation: -6 dB\n");
1805 snd_iprintf(buffer, " attenuation: -12 dB\n");
1808 snd_iprintf(buffer, " attenuation: -18 dB\n");
1811 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1812 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1818 snd_card_ro_proc_new(rme96->card, "rme96", rme96, snd_rme96_proc_read);
1832 spin_lock_irq(&rme96->lock);
1833 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1834 spin_unlock_irq(&rme96->lock);
1844 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1845 spin_lock_irq(&rme96->lock);
1846 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1847 change = val != rme96->wcreg;
1848 rme96->wcreg = val;
1849 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1850 spin_unlock_irq(&rme96->lock);
1866 switch (rme96->pci->device) {
1875 if (rme96->rev > 4) {
1886 return -EINVAL;
1896 spin_lock_irq(&rme96->lock);
1897 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1899 switch (rme96->pci->device) {
1908 if (rme96->rev > 4) {
1910 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1911 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1922 if (ucontrol->value.enumerated.item[0] >= items) {
1923 ucontrol->value.enumerated.item[0] = items - 1;
1926 spin_unlock_irq(&rme96->lock);
1936 switch (rme96->pci->device) {
1945 if (rme96->rev > 4) {
1955 val = ucontrol->value.enumerated.item[0] % items;
1958 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1964 spin_lock_irq(&rme96->lock);
1967 spin_unlock_irq(&rme96->lock);
1983 spin_lock_irq(&rme96->lock);
1984 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1985 spin_unlock_irq(&rme96->lock);
1995 val = ucontrol->value.enumerated.item[0] % 3;
1996 spin_lock_irq(&rme96->lock);
1999 spin_unlock_irq(&rme96->lock);
2007 "0 dB", "-6 dB", "-12 dB", "-18 dB"
2017 spin_lock_irq(&rme96->lock);
2018 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2019 spin_unlock_irq(&rme96->lock);
2029 val = ucontrol->value.enumerated.item[0] % 4;
2030 spin_lock_irq(&rme96->lock);
2034 spin_unlock_irq(&rme96->lock);
2050 spin_lock_irq(&rme96->lock);
2051 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2052 spin_unlock_irq(&rme96->lock);
2062 val = ucontrol->value.enumerated.item[0] % 4;
2063 spin_lock_irq(&rme96->lock);
2066 spin_unlock_irq(&rme96->lock);
2073 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2074 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2076 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2078 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2084 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2087 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2089 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2094 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2095 uinfo->count = 1;
2103 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2113 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2114 spin_lock_irq(&rme96->lock);
2115 change = val != rme96->wcreg_spdif;
2116 rme96->wcreg_spdif = val;
2117 spin_unlock_irq(&rme96->lock);
2123 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2124 uinfo->count = 1;
2132 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2142 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2143 spin_lock_irq(&rme96->lock);
2144 change = val != rme96->wcreg_spdif_stream;
2145 rme96->wcreg_spdif_stream = val;
2146 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2147 rme96->wcreg |= val;
2148 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2149 spin_unlock_irq(&rme96->lock);
2155 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2156 uinfo->count = 1;
2162 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2171 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2172 uinfo->count = 2;
2173 uinfo->value.integer.min = 0;
2174 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2183 spin_lock_irq(&rme96->lock);
2184 u->value.integer.value[0] = rme96->vol[0];
2185 u->value.integer.value[1] = rme96->vol[1];
2186 spin_unlock_irq(&rme96->lock);
2200 return -EINVAL;
2202 spin_lock_irq(&rme96->lock);
2203 vol = u->value.integer.value[0];
2204 if (vol != rme96->vol[0] && vol <= maxvol) {
2205 rme96->vol[0] = vol;
2208 vol = u->value.integer.value[1];
2209 if (vol != rme96->vol[1] && vol <= maxvol) {
2210 rme96->vol[1] = vol;
2215 spin_unlock_irq(&rme96->lock);
2272 .name = "Sample Clock Source",
2313 rme96->spdif_ctl = kctl;
2334 struct rme96 *rme96 = card->private_data;
2339 rme96->playback_pointer = readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
2341 rme96->capture_pointer = readl(rme96->iobase + RME96_IO_GET_REC_POS)
2345 memcpy_fromio(rme96->playback_suspend_buffer,
2346 rme96->iobase + RME96_IO_PLAY_BUFFER, RME96_BUFFER_SIZE);
2347 memcpy_fromio(rme96->capture_suspend_buffer,
2348 rme96->iobase + RME96_IO_REC_BUFFER, RME96_BUFFER_SIZE);
2351 rme96->areg &= ~RME96_AR_DAC_EN;
2352 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2359 struct rme96 *rme96 = card->private_data;
2362 writel(0, rme96->iobase + RME96_IO_SET_PLAY_POS
2363 + rme96->playback_pointer);
2364 writel(0, rme96->iobase + RME96_IO_SET_REC_POS
2365 + rme96->capture_pointer);
2368 memcpy_toio(rme96->iobase + RME96_IO_PLAY_BUFFER,
2369 rme96->playback_suspend_buffer, RME96_BUFFER_SIZE);
2370 memcpy_toio(rme96->iobase + RME96_IO_REC_BUFFER,
2371 rme96->capture_suspend_buffer, RME96_BUFFER_SIZE);
2374 writel(rme96->areg | RME96_AR_PD2,
2375 rme96->iobase + RME96_IO_ADDITIONAL_REG);
2376 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2380 rme96->areg |= RME96_AR_DAC_EN;
2381 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
2396 snd_rme96_free(card->private_data);
2410 return -ENODEV;
2414 return -ENOENT;
2416 err = snd_devm_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2420 card->private_free = snd_rme96_card_free;
2421 rme96 = card->private_data;
2422 rme96->card = card;
2423 rme96->pci = pci;
2429 rme96->playback_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2430 if (!rme96->playback_suspend_buffer)
2431 return -ENOMEM;
2432 rme96->capture_suspend_buffer = vmalloc(RME96_BUFFER_SIZE);
2433 if (!rme96->capture_suspend_buffer)
2434 return -ENOMEM;
2437 strcpy(card->driver, "Digi96");
2438 switch (rme96->pci->device) {
2440 strcpy(card->shortname, "RME Digi96");
2443 strcpy(card->shortname, "RME Digi96/8");
2446 strcpy(card->shortname, "RME Digi96/8 PRO");
2449 pci_read_config_byte(rme96->pci, 8, &val);
2451 strcpy(card->shortname, "RME Digi96/8 PAD");
2453 strcpy(card->shortname, "RME Digi96/8 PST");
2457 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2458 rme96->port, rme96->irq);
2471 return snd_card_free_on_error(&pci->dev, __snd_rme96_probe(pci, pci_id));