Lines Matching defs:wcreg
214 u32 wcreg; /* cached write control register value */
254 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
255 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
514 writel(rme96->wcreg | RME96_WCR_PD,
516 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
522 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
523 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
531 rme96->wcreg |= RME96_WCR_MONITOR_0;
533 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
536 rme96->wcreg |= RME96_WCR_MONITOR_1;
538 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
540 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
547 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
548 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
557 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
561 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
565 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
569 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
575 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
647 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
656 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
657 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
671 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
680 ds = rme96->wcreg & RME96_WCR_DS;
683 rme96->wcreg &= ~RME96_WCR_DS;
684 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
688 rme96->wcreg &= ~RME96_WCR_DS;
689 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
693 rme96->wcreg &= ~RME96_WCR_DS;
694 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
698 rme96->wcreg |= RME96_WCR_DS;
699 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
703 rme96->wcreg |= RME96_WCR_DS;
704 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
708 rme96->wcreg |= RME96_WCR_DS;
709 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
715 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
716 (ds && !(rme96->wcreg & RME96_WCR_DS)))
722 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
776 rme96->wcreg &= ~RME96_WCR_MASTER;
781 rme96->wcreg |= RME96_WCR_MASTER;
786 rme96->wcreg |= RME96_WCR_MASTER;
792 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
803 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
815 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
819 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
823 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
835 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
864 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
874 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
875 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
892 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
895 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
905 rme96->wcreg &= ~RME96_WCR_MODE24;
908 rme96->wcreg |= RME96_WCR_MODE24;
913 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
922 rme96->wcreg &= ~RME96_WCR_MODE24_2;
925 rme96->wcreg |= RME96_WCR_MODE24_2;
930 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
940 rme96->wcreg &= ~RME96_WCR_ISEL;
943 rme96->wcreg |= RME96_WCR_ISEL;
949 rme96->wcreg &= ~RME96_WCR_IDIS;
950 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
969 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
998 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
999 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1000 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1077 rme96->wcreg |= RME96_WCR_START;
1079 rme96->wcreg &= ~RME96_WCR_START;
1081 rme96->wcreg |= RME96_WCR_START_2;
1083 rme96->wcreg &= ~RME96_WCR_START_2;
1084 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1156 rme96->wcreg &= ~RME96_WCR_ADAT;
1157 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1162 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1222 rme96->wcreg |= RME96_WCR_ADAT;
1223 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1228 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1288 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1614 rme96->wcreg =
1622 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1672 if (rme96->wcreg & RME96_WCR_IDIS) {
1675 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1709 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1716 if (rme96->wcreg & RME96_WCR_SEL) {
1723 if (rme96->wcreg & RME96_WCR_MODE24) {
1730 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1739 if (rme96->wcreg & RME96_WCR_PRO) {
1744 if (rme96->wcreg & RME96_WCR_EMP) {
1749 if (rme96->wcreg & RME96_WCR_DOLBY) {
1806 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1818 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1819 change = val != rme96->wcreg;
1820 rme96->wcreg = val;
2108 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2109 rme96->wcreg |= val;
2110 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);